Capacitance measurement system and methods

Abstract

A first capacitor and a second capacitor are charged until voltage at the second capacitor settles to a settling voltage. While charging, the first capacitor is alternately switched between a current source and ground. When the settling voltage is reached, charging of the first capacitor is halted. The second capacitor continues to be charged until voltage at the second capacitor reaches a reference voltage. The amount of time it takes for the settling voltage to reach the reference voltage corresponds to a measure of capacitance on the first capacitor.

Description

FIELD

Embodiments of the present invention generally relate to capacitive sensors, and methods and systems that measure capacitance.

BACKGROUND

A capacitive sensor generally includes an electrode or an array of electrodes. When an object such as a finger or stylus is brought within range of an electrode, the capacitance of the electrode is changed by an amount that depends, at least in part, on the distance from the object to the electrode. For example, a set of electrodes may be arranged in parallel to define a sensing region, and the position of an object relative to the sensing region can be determined based upon the change in capacitance per electrode induced by the object. In simple terms, a profile of capacitance versus electrode can be used to unambiguously determine the position of an object in, for example, the x-direction—the x-coordinate corresponds to the peak of the profile. A second set of parallel electrodes arrayed perpendicular to the first set can be similarly used to determine the position of the object in the y-direction. A single electrode can be used to determine proximity (the z-direction).

Accurate measurements of capacitance changes induced by an object are needed so that the position of the object can be accurately determined. Accurate measurements of the background capacitance (e.g., the about of capacitance that is present even if an object is not in proximity) are also needed to account for noise that may be introduced by changes in ambient temperature or the presence of contaminants on the surface of the sensor, for example.

SUMMARY

Capacitive sensors should be noise resistant and should be able to achieve high resolution. Embodiments in accordance with the present invention provide these and other advantages.

In one embodiment, a current source charges a first capacitor (e.g., a senor capacitor) and a second capacitor (e.g., an internal capacitor) until voltages at the capacitors equilibrate at a settling voltage. In another embodiment, a third capacitor (e.g., a modification or external capacitor) is also charged until the voltages at each capacitor equilibrate at the settling voltage. In one embodiment, the first capacitor is alternately switched between the current source and ground until the settling voltage is reached. Sensitivity is proportional to signal-to-noise ratio (SNR). Switching of the first (e.g., sensor) capacitor reduces the outside noise sources on that capacitor that could inadvertently couple into the system.

When the settling voltage is reached, the first (sensor) capacitor is disconnected from the current source. The first capacitor can be switched to ground and disconnected from the second capacitor and optional third capacitor, so no coupled noise from the sensor affects the settled voltage. The current source will continue to charge the second capacitor until voltage at the second capacitor reaches a reference voltage (the third capacitor, if used, is similarly charged). The amount of time it takes for the settling voltage to reach the reference voltage corresponds to a measure of capacitance on the first capacitor. In one embodiment, a counter counts the number of cycles generated by an oscillator as the voltage increases from the settling voltage to the reference voltage.

In one embodiment, a comparator is used to compare the voltage at the capacitor(s) to the reference voltage. In one such embodiment, a low pass filter is coupled between the capacitor(s) and the comparator to reduce the effect of high frequency noise. In another such embodiment, the voltage is increased using a single slope analog-to-digital converter (ADC) that includes the current source, the counter and the comparator. The current source can be calibrated so that the settling voltage is just below the reference voltage, so that the count of oscillator cycles will have a larger dynamic range, increasing resolution.

In summary, high sensitivity and high resolution capacitance measurement systems and methods are described. The capacitance on the first capacitor can be accurately measured in the absence of an object to more precisely determined background capacitance. In the presence of an object, the change in capacitance on the first capacitor can be accurately measured, to detect the object with increased sensitivity and/or to more precisely locate the object relative to a sensing region. These and other objects and advantages of the various embodiments of the present invention will be recognized by those of ordinary skill in the art after reading the following detailed description of the embodiments that are illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate various embodiments of the present invention and, together with the description, serve to explain the principles of those embodiments.

FIG. 1 illustrates one embodiment of a capacitance measuring system, with switches set in one position.

FIG. 2 illustrates one embodiment of a capacitance measuring system, with switches set in another position.

FIG. 3 illustrates voltage versus time in the presence of an object, as measured in a capacitance measuring system according to an embodiment of the present invention.

FIG. 4 illustrates voltage versus time in the absence of an object, as measured in a capacitance measuring system according to an embodiment of the present invention.

FIG. 5 is a flowchart of one embodiment of a method for measuring capacitance according to the present invention.

FIG. 6 illustrates a flowchart 600 for one embodiment of a method for setting up a capacitance measurement device according to the present invention

FIG. 7A illustrates an embodiment of a capacitance sensing front end 700 of system 100 (FIG. 1).

FIG. 7B illustrates an embodiment of a capacitance sensing front end 700 of system 100 (FIG. 1).

FIG. 8 illustrates an embodiment of a capacitance sensing front end 800 of system 100 (FIGS. 1 and 7).

FIG. 9 illustrates another embodiment of a capacitance sensing front end 900 of system 100 (FIGS. 1 and 8).

FIG. 10A illustrates an embodiment of a method for scanning a sensor or sensors including three clocks, or oscillators (SYSCLK).

FIG. 10B illustrates an embodiment of a method for scanning capacitance sensors wherein an oscillator is adjusted in response to the scan outputs.

DETAILED DESCRIPTION

Reference will now be made in detail to the various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternates, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 1 illustrates one embodiment of a capacitance measuring system 100. In the example of FIG. 1, system 100 includes a number of capacitors Cs(1), Cs(2), . . . , Cs(N), which may be referred to as sensor capacitors or sensing capacitors, any one of which may also be referred to herein as a first capacitor. System 100 also includes a capacitor Cint, which may be referred to as a sampling capacitor or internal capacitor and which may also be referred to herein as a second capacitor. In one embodiment, system 100 also includes a capacitor Cmod, which may be referred to as a modification capacitor or external capacitor and which may also be referred to herein as a third capacitor. The capacitor Cint may be internal to a chip, and the capacitor Cmod may be external to the chip. The capacitor Cmod, though optional, can improve noise resistance and hence can increase sensitivity. The capacitor Cmod can also reduce or eliminate large voltage swings within the system.

The system 100 also includes a current source 110. IN one embodiment, current source 110 is an adjustable, digital current source that, once adjusted, supplies a constant charging current iDAC. The current source 110 is connected to the capacitors Cint and Cmod by a bus 115. In one embodiment, the bus 115 is an analog bus.

System 100 also includes switching circuitry that includes a number of switches such as switches 120 and 121. The current source 110 can be connected to the capacitors Cs(1), Cs(2), . . . , Cs(N), depending on the position of an intervening switch such as switch 120. The capacitors Cs(1), Cs(2), . . . , Cs(N) can also be connected to ground, depending on the position of an intervening switch such as switch 121. If, for example, capacitor Cs(1) is connected to ground by closing switch 121, then switch 120 is open so that capacitor Cs(1) is disconnected from the current source 110 (see FIG. 2). Conversely, if capacitor Cs(1) is connected to current source 110 by closing switch 120, then switch 121 is opened.

In the example of FIG. 1, system 100 also includes an optional low pass filter (LPF) 130, a comparator 135, an oscillator 140, a counter (or timer) 145, and processing circuitry 150 (e.g., a microprocessor). The low pass filter 130, if present, helps to prevent the input of high frequency noise to the comparator 135.

In operation, system 100 measures the capacitance on each of the sensor capacitors Cs(1), Cs(2), . . . , Cs(N). In the example of FIG. 1, capacitance is measured on one sensor capacitor at a time. In general, the capacitance on a selected capacitor (e.g., Cs(1)) is translated into an effective resistance by switching the capacitor Cs(1) between the bus 115 and ground (effective resistance is sometimes referred to as a capacitive reactance, measured in ohms). Switching of the capacitor Cs(1) reduces the outside noise sources on that capacitor that could inadvertently couple into the system 100. The current source 110 is used to create a voltage drop across the effective resistance. The voltage drop is sampled using the sampling capacitor Cint and measured using the current source 110, oscillator 140 and counter 145.

More specifically, in the first stage of operation, the selected capacitor (e.g., Cs(1)) is connected to bus 115 and current source 110 by closing switch 120 (switch 121 is open). Change flows into the capacitors Cs(1), Cint and Cmod from the current source 110. During the first stage, the capacitor Cs(1) is alternately switched between the bus 115 and ground by appropriately opening and closing the switches 120 and 121, until the settling voltage is reached. Each time the capacitor Cs(1) is switched between bus 115 and ground, an amount of charge is removed from the parallel capacitors Cint and Cmod. Charge from the capacitors Cint and Cmod can be transferred to Cs(1) until the voltage—referred to herein as the settling voltage—is the same at each of these capacitors.

In one embodiment, the capacitors Cint and Cmod are precharged to a preset voltage (e.g., the comparator 135 reference voltage Vref) using a voltage source (not shown). By starting at a preset voltage, the time needed to reach the settling voltage can be reduced.

As mentioned above, each time the capacitor Cs(1) is switched between bus 115 and ground, an amount of charge Q_sensor is removed from the parallel capacitors Cint and Cmod:Q_sensor=C_sensorV.

Over time, this charge movement acts like a current:Q_sensor/t=C_sensorV/t.

The amount of current depends on the capacitance of sensor Cs(1) (C_sensor), the switching frequency f (the frequency at which the sensor capacitor Cs(1) is switched between bus 115 and ground), and the voltage:I_sensor=fC_sensorV.

Solving for voltage:

$V=\frac{I_{\mathrm{sensor}}}{{\mathrm{fC}}_{\mathrm{sensor}}}.$

The capacitance on Cs(1) can be thought of as a resistor based on Ohm's Law, resulting an effective resistance of:R=1/(fC_sensor).

The constant charging current iDAC flows through this effective resistance. The voltage across the effective resistance is the resulting voltage on the capacitors Cint and Cmod:

$V=\frac{1}{{\mathrm{fC}}_{\mathrm{sensor}}}\left(\mathrm{iDAC}\right).$

Thus, the switching circuitry (e.g., switches 120 and 121) acts as a capacitance-to-voltage converter. Eventually, the charge will distribute (equilibrate) across the capacitors Cs(1), Cint and Cmod until the voltage is the same at each capacitor. The settling voltage is given by equation (1) and is based on the switching frequency f, the capacitance C_sensor of Cs(1), and the amount of current iDAC. The capacitors Cint and Cmod act in effect as bypass capacitors that stabilize the resulting voltage.

Once the voltage settles to the settling voltage, the capacitor Cs(1) can be disconnected from current source 110. In addition, the capacitor Cs(1) can be switched to ground and disconnected from the capacitors Cint and Cmod (switch 121 is closed and switch 120 is opened; refer to FIG. 2), so that no coupled noise from the sensor affects the settled voltage. The settling voltage is held on the capacitors Cint and Cmod. The capacitor Cs(1) may remain connected to the capacitors Cint and Cmod, but better noise immunity is provided if it is disconnected.

Capacitance is measured in the second stage of operation. Once the capacitor Cs(1) is disconnected from current source 110 at the end of the first stage, the capacitors Cint and Cmod are charged by current source 110 until the voltage on those capacitors increases from the settling voltage to the threshold voltage (reference voltage Vref) of comparator 135. The amount of current supplied by the current source 110 in the second stage may be different from that of the first stage. A counter 145 counts the number of oscillator 140 cycles until the voltage reaches the reference voltage. The number of counts is related to the size of the capacitance Cint and Cmod:

$\frac{\Delta V}{t}=\frac{\mathrm{iDAC}}{C_{\mathrm{int}}+C_{\mathrm{mod}}}.$

Solving for t:

$t=\frac{\left(C_{\mathrm{int}}+C_{\mathrm{mod}}\right)\Delta V}{\mathrm{iDAC}}.$

The above equation can be transformed to counts:

$\mathrm{Counts}=\frac{\left(C_{\mathrm{int}}+C_{\mathrm{mod}}\right)\Delta V}{\mathrm{iDAC}}{f}_0;$ where f₀ is the clock or cycle frequency of the oscillator 140 (which may be different from the frequency f of equation (1) above).

The number of counts corresponds to the about of capacitance on the capacitors Cint and Cmod, and therefore also corresponds to the amount of capacitance that was on the sensor capacitor Cs(1) (before it was switched to ground at the end of the first stage). The number of counts increases when the sensor capacitance increases.

The first and second stages described above can be repeated to measure the capacitance on each of the other sensor capacitors Cs(2), . . . , Cs(N), and then repeated again starting with sensor capacitor Cs(1). Between measurement sequences, the current source 110 can be turned off, allowing the voltage on the capacitors Cint and Cmod to decrease; in one embodiment, the voltage decreases to the comparator reference voltage Vref. At the start of the next measurement sequence, the voltage will again be set to the settling voltage, as described above.

Capacitance measuring system 100 can be used as part of an interface (e.g., a touchpad or touchscreen) in an electronic device such as, but not limited to, a computing device (e.g., desktop, laptop, notebook), a handheld device (e.g., cell phone, smart phone, music player, game player, camera), or a peripheral device (e.g., keyboard). Capacitance measuring system 100 can be incorporated as part of a sensing system that can be used, for example, to determine whether or not an object (e.g., a user's finger, a probe, a stylus, etc.) is near or in contact with a sensing region. The sensor electrodes (specifically, the traces connecting the sensor capacitors to the rest of the system) may be made of any conductive material, including substantially transparent material such as indium tin oxide (ITO).

The capacitance measuring system described herein can also be sued to detect the presence of moisture, contaminants or the like on the surface of a sensing region. In general, capacitance measuring system 100 can be used to detect an element (e.g., an object or a substance) that is proximate to a sensing region. An element in contact with the sensing region is also proximate to that region, and locating the position of an element within the sensing region also includes detecting the element.

The presence of, for example, a finger in proximity to or in contact with the sensor capacitor Cs(1) will increase the capacitance on that sensor which, as shown by equation (1) above, will decrease the effective resistance of that capacitor. The lower effective resistance results in a lower settling voltage across the capacitors Cint and Cmod. Thus, it will take longer for the current source 110 to increase the voltage from the settling voltage to the reference voltage Vref, resulting in more counts relative to the number of counts that would be recorded in the absence of a finger.

FIG. 3 illustrates voltage versus time in the presence of an object, as measured in capacitance measuring system 100 (FIG. 2) according to an embodiment of the present invention. Time t0 corresponds to the beginning of the second stage of operation mentioned above, and so the voltage held on the capacitors Cint and Cmod (and also on the bus 115) is the settling voltage. In the embodiment of FIG. 2, the voltage on the capacitors Cint and Cmod (and on the bus 115) is increased using a single slope ADC that includes the current source 110, the counter 145 and the comparator 135. Other types of ADCs (e.g., a multi-slope ADC) can be used instead of a single slope ADC. At time t1, the voltage reaches the threshold voltage (Vref) on the comparator 135. In the example of FIG. 2, the counter counts the number of cycles generated by oscillator 140 between time t0 and time t1.

FIG. 4 illustrates voltage versus time in the absence of an object, as measured in a capacitance measuring system 100 (FIG. 2) according to an embodiment of the present invention. Relative to FIG. 3, the settling voltage is higher in the absence of an object. The voltage increases from the settling voltage to the threshold voltage at the same rate as in FIG. 3 but reaches the threshold voltage faster, resulting in fewer counts between time t0 and time t1 relative to FIG. 3.

To provide consistent sensitivity, the settling voltage is calibrated. The amount of current iDAC during the first operating stage (when the sensor capacitor is alternately switched between ground and the current source 110) determines the settling voltage. In one embodiment, at startup of the system 100 (in the absence of an object), a successive approximation technique is used to find a current iDAC that results in a settling voltage that is just below the threshold voltage Vref.

For example, the current source 110 may be controlled by an eight-bit signal. In successive approximation, the most significant bit is set and the resultant settling voltage is compared to the threshold voltage. Depending on the result of the comparison, the most significant bit either remains set or is cleared, and the next most significant bit is set. This process is repeated to determine the current iDAC that results in a settling voltage that is just below the threshold voltage Vref. As can be deduced from FIGS. 3 and 4, the dynamic range of the counts with an object present versus not present is greater as a result.

As mentioned above, the amount of current provided by current source 110 during the first stage of operation (during which the capacitors Cs(1), Cint and Cmod settle to the settling voltage) and during the second stage of operation (when the voltage on the capacitors Cint and Cmod is increased from the settling voltage to the threshold voltage) can be the same or different.

With reference again to FIG. 2, processing circuitry 150 can determine the presence of an object near a sensor capacitor Cs(1), Cs(2), . . . , Cs(N) by comparing the most recent count for a capacitor to either the count recorded for that capacitor from the preceding measurement sequence or a stored baseline value. The object will be closest to the sensor capacitor that experiences the highest count. Movement of an object relative to the sensor capacitors can be detected by monitoring the count per sensor capacitor over time.

The stored baseline value will account for the presence of contaminants, for example, that may have accumulated on the surface of the sensor surface (e.g., on the surface of a touchpad). In general, the stored baseline value can account for effects that may affect the performance (accuracy) of system 100. The stored baseline value can be updated over time.

FIG. 5 is a flowchart 500 of one embodiment of a method for measuring capacitance according to the present invention. Although specific steps are disclosed in flowchart 500, such steps are exemplary. That is, embodiments of the present invention are well-suited to performing various other steps or variations of the steps recited in flowchart 500. The steps in flowchart 500 may be performed in any order different that presented and that the steps in flowchart 500 are not necessarily performed in the sequence illustrated. Furthermore, the features of the various embodiments described above can be used alone or in combination.

In block 510, with reference also to FIG. 1, a current source charges a first capacitor (e.g., sensor capacitor Cs(1)) and a second capacitor (e.g., capacitor Cint) until their respective voltages equilibrate at a settling voltage. In one embodiment, the first capacitor is switched back and forth between the current source and ground until the settling voltage is reached. In actuality, due to the switching of the first capacitor, there is charging by the current source and discharging from the first capacitor, but the net effect is charging. In one embodiment, the current source also charges a third capacitor (e.g., capacitor Cmod) until the voltages at each capacitor equilibrate at the settling voltage.

In block 520, when the settling voltage is reached, the first capacitor (Cs(1)) is disconnected from the current source. In one embodiment, the first capacitor (Cs(1)) is also switched to ground and disconnected from the capacitors Cint and Cmod. The current source continues to charge the second capacitor (Cint) and the optional third capacitor (Cmod) until voltages at the respective capacitors reach a reference voltage that is greater than the settling voltage.

In block 530, in one embodiment, oscillatory cycles are counted until the settling voltage reaches the reference voltage. In general, the amount of time it takes for the settling voltage reaches the reference voltage is determined.

Blocks 510, 520, and 530 can be repeated for each sensor capacitor Cs(1), Cs(2), . . . , Cs(N). The count per sensor capacitor can be compared across the sensor to determine the position of an object, and the count per sensor can be compared to a preceding count to detect the presence of an object (or to determine that a previously detected object is no longer presence).

FIG. 6 is a flowchart 600 of one embodiment of a method for setting up a capacitance measurement device according to the present invention. In block 610, parameters that configure the capacitance measurement device are loaded. Such parameters may include the value for the programmable current source (110, FIG. 1), routing to the capacitance sensing input under test, oscillator speeds sources for the digital conversion (140, FIG. 140 and block 530, FIG. 5), and reference voltages for the comparator (135, FIG. 1). Parameters loaded in block 610 may include other adjustable or preset values or configurations used in the capacitance measurement device. Such parameters may be used to adjust the sensitivity, interconnect, timing or output of the capacitance sensing device.

In block 620, the current source (110, FIG. 1) is set up and an external capacitor is set up (Cmod, FIG. 1). The current source may set up using parameters of block 610 and is configured to charge the sensed capacitor (see FIG. 1) at a certain rate. The external capacitor may be used to filter the capacitance sensing and provide a more stable measurement. The enabling of the external capacitor may include writing to its register location to configure the external capacitor to a certain value. In one embodiment, the external capacitor may be integrated into the sensing integrated circuit. In this embodiment, there may be four or more capacitance settings. In another embodiment, the external capacitor may be external to the sensing integrated circuit. In this embodiment, enabling the external capacitor is accomplished by enabling the pin I/O to which it is coupled.

In block 630, the external capacitor is placed on a bus (115, FIG. 1). The external capacitor may be placed on the bus by closing a switch coupled to both the bus and to the external capacitor.

In block 640, the successive approximation routine is performed. Because the external capacitor is already coupled to the bus when the successive approximation of block 640 is executed, a possible overflow condition and subsequent recalibration caused by the addition of a larger capacitor on the sensing circuit after calibration is avoided, improving the efficiency of the capacitance measurement. The overflow condition is avoided because the actual scans of the sensor have the external capacitor coupled to the bus. Because the actual scans of the sensor have the external bus coupled to the bus, coupling the external capacitor to the bus during the successive approximation step provides a better calibration.

In block 650, the sensors are scanned. Sensors may be illustrated by Cs(1), . . . , Cs(N) of FIG. 1. The scanning of the sensors is illustrated in FIG. 5 and described above.

FIG. 7A illustrates one embodiment of a capacitance sensing front end 700 of system 100 (FIG. 1). Front end 700 may include a capacitor CS to me measured. Capacitor CS may have one electrode coupled to a ground potential. The other electrode of capacitor CD may be coupled to an programmable current DAC (IDAC) 710 which is configured to supply a current to the capacitor CS and sensing front end from a voltage potential, V_DD. The output of IDAC 710 and capacitor CS may be coupled alternately to an analog multiplexer bus (AMUX) 740 through switch 720 and to a ground potential through switch 722. Switch 720 may be used to couple capacitor 720 to the sensing circuitry, which is also coupled to AMUX 740. Switch 722 may be used to couple capacitor CS to ground, resetting the potential on capacitor CS. The sensing circuitry, including capacitor Cmod and comparator 750 may also be coupled to AMUX 740. In one embodiment, capacitor Cmod may have a capacitance to ground. Closing switch 720 couples capacitor CS to capacitor Cmod a comparator 750 through AMUX 740 for the scan described in FIG. 5.

FIG. 7B illustrates another embodiment of a capacitance sensing front end 700 of system 100 (FIG. 1). In this embodiment the connection of Cmod to the input of comparator 750 and to switch 720 is through a pin tap 760. Direct coupling of the comparator 750 input, Cmod and switch 720 removes parasitic capacitance that is added by the AMUX (740, FIG. 7A) and reduces noise coupling into the input of comparator 750. Removal of AMUX-induces parasitic capacitance and the reduction of noise coupling into the input of comparator 750 improves performance of the capacitance sensing circuit by providing a cleaner measured signal to the counter and processing circuitry (145 and 150, FIG. 1). While this embodiment is shown with a pin tap 760, other embodiment may include a direct connection to an internal capacitor and Cmod. In such embodiments, a pin tap may not be necessary, but a direct connection to an internal capacitor provides the same benefits to the measurement system by removing parasitic capacitance and reducing the noise coupled into the measurement circuitry.

FIG. 8 illustrates another embodiment of a capacitance sensing front end 800 of system 100 (FIGS. 1 and 7). In this embodiment, a register buffer (REG BUF) is coupled intermediate to switch 820 and pin tap 860 (analogous to switch 720 and pin tap 760, FIG. 7). In this embodiment, REG BUF 870 may be a programmable reference buffer. REG BUF 870 may be set to a number of reference voltages and use to charge the pin tap (or AMUX of FIG. 7A) to a reference voltage. In this embodiment the parasitic capacitance the capacitance sensing front end 800 and the pin tap 870 may be compensated for by rapidly charging the measurement circuit before beginning the actual scan.

FIG. 9 illustrates another embodiment of a capacitance sensing front end 900 of system 100 (FIGS. 1 and 8). In this embodiment, a second comparator 955 is coupled to pin tap 960 in parallel to comparator 950 (analogous to comparator 750, FIG. 7). In this embodiment comparators 950 and 955 may use different reference voltages VREF1 (comparator 950) and VREF2 (comparator 955). The use of two comparators allows for fast, hardware-based changes to sensitivity, which may improve performance and speed up dynamic sensing thresholds for applications with rapidly changing conditions.

Capacitance sensing is sensitive to noisy environments. High-frequency noise sources may couple into the sensing circuitry in such a way that hardware improvements alone are not sufficient to buffer or block the signal. In such situations, it may be necessary to perform a second level of processing or control. FIGS. 10A and 10B illustrate two embodiments for improving the capacitance sensing performance by measuring or interacting with a noise source.

FIG. 10A illustrates a first embodiment, three clocks, or oscillators (SYSCLK), are used to scan the sensor(s). For scan 1 1021, SYSCLK 1 1011 is the oscillator frequency. The scan output of scan 1 1021 is stored in a memory location (not shown) and a second scan, scan 2 1022 is performed using a second oscillator frequency, SYSCLK 2 1012. The output of scan 2 1022 is stored in a memory location (not shown) and a third scan, scan 3 1023 is performed using a third oscillator frequency, SYSCLK 3 1013. The output of the scan 3 is stored in a memory location (not shown). All of the stored values are then processed together. If the aggregate of all of the scans, 1, 2 and 3, is such that a conductive object is present on the sensor, the capacitance sensing circuit outputs such a result. In one embodiment, the processing of the three scans may be by voting. In this embodiment, each scan has a discrete output, on or off. If there are more “ons” than “offs,” a conductive object is determined to be present on the sensor.

While FIG. 10A illustrates an embodiment using three scans and three oscillator frequencies, one of ordinary skill in the art would understand that more or fewer scans and oscillator frequencies may be used. One of ordinary skill in the art would also understand that the number of oscillator frequencies may be fewer than the number of scans. That is, multiple scans may have the same oscillator frequencies. For such embodiments, the multiple scans may be used to remove low-frequency periodic noise from the capacitance sensing system.

FIG. 10B illustrates another embodiment of a method for scanning capacitance sensors where in the oscillator is adjusted in response to the scan outputs. In this embodiment, the output of the scan 1090 is a sensing result and a signal sent to IMO ADJUST 1080. IMO ADJUST 1080 may be used to change the internal main oscillator (IMO) frequency of the sensing device. The signal from scan 1090 may be a command to change the IMO or to keep it the same. Adjusting the IMO frequency may move the sensing circuit out of phase with possible noise sources. The output of IMO ADJUST 1080 is sent to IMO TRIM 1070, wherein the IMO frequency is trimmed for use by the capacitance sensing circuitry. The trimmed IMO frequency is then sent to SYSCLK 1060 and divided down and routed to the necessary circuit elements for performing a capacitance sensing scan. Once the scan is completed, the result may sent to the processing circuitry and again to IMO adjust 1080. The embodiment illustrated in FIG. 10B may allow for dynamic, real-time adjustment of capacitance sensing parameters in response to noise signals in the system. It also may improve the rate of scanning by not requiring multiple scans of each sensor at different frequencies to determine a result. One of ordinary skill in the art would understand that the methods illustrated by FIGS. 10A and 10B may be combined to achieve possible better noise performance still.

Embodiments of the present invention are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.

Claims

1. A system for measuring capacitance comprising: a current source coupled to a first node of a first capacitor and to a first node of a second capacitor, the current source configured to supply charge to the first and second capacitors, wherein the charge supplied to the first and second capacitors generates a voltage potential across the first and second capacitors;a first switch configured to couple the current source and the first node of the first capacitor to the first node of the second capacitor;a second switch configured to couple the first node of the first capacitor to a second node of the second capacitor; anda circuit configured to measure the voltage potential across the first and second capacitors, wherein, the second capacitor is coupled to the measurement circuit after the current source is configured and coupled to the first node of the first capacitor and after a voltage potential across the first capacitor has reached a settling voltage, andthe current source is configured to provide a charge on the first capacitor according to a predetermined charge rate.

2. The system of claim 1 wherein the first and second capacitors are coupled to the current source and to the voltage measurement circuit through a multiplexer bus.

3. The system of claim 1, wherein the second capacitor is coupled to the voltage measurement circuit and the current source through a pin tap.

4. The system of claim 1, wherein the voltage measurement circuit comprises a first comparator comprising a first input coupled to the first and second capacitors, a second input coupled to a first reference voltage, and an output coupled to a processing means.

5. The system of claim 4, wherein the voltage measurement circuit further comprises a second comparator comprising a first input coupled to the first and second capacitors, a second input coupled to a second reference voltage, and an output coupled to a processing means.

6. The system of claim 1 further comprising a reference buffered coupled intermediate to the current source and the second capacitor.

7. The system of claim 6, wherein the reference buffer is configured to charge the second capacitor at a rate substantially greater than the programmable current source.

8. The system of claim 1, wherein the first capacitor is a capacitance sensing input configured to have a variable capacitance in response to capacitance coupling to an activating element.

9. The system of claim 8, wherein the variable capacitance is capacitance between the first node of the first capacitor and a ground potential.

10. The system of claim 8, wherein the variable capacitance is a mutual capacitance between the first node of the first capacitor and a drive electrode, the drive electrode configured to provide a variable voltage signal.

11. A method for measuring a capacitive input comprising: configuring a current source to charge a first capacitor, wherein a first node of the first capacitor is the capacitive input and wherein the current source has an adjustable output;coupling the first capacitor and the current source to a multiplexer bus;coupling a second capacitor to the multiplexer bus;charging a first capacitor and a second capacitor until voltage at said second capacitor settles to a settling voltage derived from the current source, a settling time, and the capacitance of the first capacitor, wherein during said charging said first capacitor is switched back and forth between a current source and ground;when said settling voltage is reached, halting charging of said first capacitor while continuing to charge said second capacitor until voltage at said second capacitor reaches a reference voltage that is greater than said settling voltage; anddetermining a measure of time for said settling voltage to reach said reference voltage, wherein said measure of time corresponds to a measure of capacitance on said first capacitor.

12. The method of claim 11 further comprising: charging a third capacitor until voltages at said second and third capacitors settle to said settling voltage; andafter said settling voltage is reached and said charging of said first capacitor is halted, continuing charging said third capacitor until voltage at said third capacitor reaches said reference voltage.

13. The method of claim 11 wherein said charging further comprises supplying a constant charging current to said first and second capacitors using a digital current source.

14. The method of claim 11 wherein said determining comprises counting a first number of oscillatory cycles until said settling voltage reaches said reference voltage, wherein said first number corresponds to said measure of capacitance on said first capacitor.

15. The method of claim 14 further comprising: halting charging of said second capacitor and reducing voltage at said second capacitor to less than said threshold voltage after voltage at said second capacitor reaches said threshold voltage;charging said first and second capacitors until voltage at said second capacitor settles to said settling voltage;halting charging of said first capacitor while continuing to charge said second capacitor until voltage at said second capacitor again reaches said reference voltage when said settling voltage is again reached; andcounting a second number of oscillatory cycles until voltage at said second capacitor reaches said reference voltage.

16. The method of claim 15 further comprising comparing said first and second numbers to identify a change in said measure of capacitance on said first capacitor.

17. The method of claim 11 wherein said first capacitor is one of a plurality of capacitors, wherein said method further comprises measuring capacitance for each capacitor of said plurality of capacitors.

18. The method of claim 11 further comprising detecting an element in sensing range of at least one of said capacitors based on capacitances measured for said plurality of capacitors.

19. The method of claim 11 further comprising switching said first capacitor to ground and disconnecting said first capacitor from said second capacitor after said settling voltage is reached.

20. The method of claim 11 further comprising: comparing the measure of time to a reference measure of time;adjusting an output of an internal main oscillator in response to the comparison;adjusting at least one of a plurality of trim values for the internal main oscillator after adjusting the output of the internal main oscillator;configuring an oscillator for the measuring of the capacitive input after adjusting the at least one the plurality of trim values; andrepeating the measuring of the capacitive input.

21. An apparatus comprising a programmable current source coupled to a first variable capacitor and a switch network, the switch network configured to couple the programmable current source alternately to a ground potential and to a second capacitor and an input of a voltage measurement circuit, wherein the programmable current source is coupled to the second capacitor only after the voltage on the first variable capacitor and the second capacitor reaches a settling voltage.

22. The apparatus of claim 21 wherein the voltage measurement comprises a first comparator comprising a first input coupled to the first and second capacitors, a second input coupled to a first reference voltage, and an output coupled to a processing means.

23. The apparatus of claim 22 wherein the voltage measurement further comprises a second comparator comprising a first input coupled to the first and second capacitors, a second input coupled to a second reference voltage, and an output coupled to a processing means.

24. The apparatus of claim 21 further comprising a reference buffer coupled intermediate to the switch network and the second capacitor, wherein the reference buffer is configured to charge the second capacitor at a rate substantially greater than the programmable current source.

25. The system of claim 21, wherein the variable capacitor comprises a first node coupled to the measurement current source and a second node to a ground potential.

26. The system of claim 21, wherein the variable capacitor is a mutual capacitor between a first node of the variable capacitor and a drive electrode, the drive electrode configured to provide a variable voltage signal.