Patent Application
20240084453
The present disclosure relates to the technical field of semiconductor manufacturing technologies and, more particularly, to semiconductor processing equipment and a carrier device of the semiconductor processing equipment.
A Metal-organic Chemical Vapor Deposition (MOCVD) method shows good step coverage and resistivity characteristics in processes of forming a metal or metal nitride barrier layer and an adhesion layer. The MOCVD method has become an important method for implementing the processes of forming the barrier and the adhesion layer. MOCVD equipment also becomes mainstream equipment for integrated circuit manufacturing.
In the MOCVD method, a metal-organic compound is used as a source for metal or metal nitride. At a high temperature, the source undergoes a thermal decomposition reaction. By-products such as carbon, hydrogen, and oxygen are separated in a gaseous form. The metal or metal nitride deposits to form a thin film. The thin film formed by thermal decomposition includes many impurities. The resistivity of the thin film is high. The thin film needs to be processed using plasma to remove the impurities of the thin film to reduce the resistivity. To improve production efficiency, the MOCVD equipment for implementing the thin film preparation method needs to finish the thin film thermal deposition and in-situ plasma processing in the same chamber. The plasma is generated by radiofrequency (RF) capacitive-coupled discharge, which requires the chamber to satisfy both the flow field and thermal field requirements of the CVD process and the requirements of the RF system and prevent abnormal discharge.
During the film formation process, the MOCVD equipment needs to heat the wafer to a certain temperature to cause the source to be stably thermal-decomposed. Thus, the base for carrying the wafer needs to have a heating function. The base includes a heater. An edge ring is arranged around the base. An annular gap is arranged at the area facing the base and the edge ring to form an edge purge channel. When the wafer is placed on the base, the edge of the edge ring can block a part of the opening of the edge purge channel. During the thermal deposition process, gas passes the edge purge channel to blow the edge of the wafer. Thus, the thin film deposition is avoided on the back surface and side surface of the wafer, the temperature of the annular ring is reduced, and the thin film deposition at the surface of the annular ring is reduced. During the plasma processing process, gas does not pass through the edge purge channel. However, the channel communicates with the chamber. Charges are cumulated at the surface of the wafer prepared by an insulation material (a metal or metal nitride thin film is deposited on the base made of silicone oxide). The surface of the wafer has a high level. The base is grounded to be a zero level. Thus, the back surface of the wafer is prone to discharge or ignite in the edge purge channel in a plasma environment and a constant electric field, which affects the process stability and causes particle contamination.
One aspect of the present disclosure provides a carrier device in semiconductor processing equipment, including a base and an edge ring. The base includes a base body configured to carry a wafer. An outer diameter of the base body is smaller than a diameter of the wafer. The edge ring surrounds the base. An outer diameter of the edge ring is greater than the diameter of the wafer. An outer circumferential surface of the base body faces and is spaced from an inner circumferential surface of the edge ring to form a first annular channel. The first annular channel is configured to communicate with a gas supply system. When the base body carries the wafer, an upper surface of the edge ring faces and is spaced from a lower surface of the wafer to form a second annular channel. The first annular channel communicates with the second annular channel. A first width of the first annular channel in a radial direction of the base and a second width of the second annular channel in an axial direction of the base are smaller than or equal to twice a plasma sheath layer thickness generated when the semiconductor processing equipment performs a predetermined process.
Another aspect of the present disclosure provides semiconductor processing equipment. The semiconductor processing equipment includes a process chamber, an upper electrode mechanism, and a lower electrode mechanism. The upper electrode mechanism includes a showerhead and an upper electrode power supply. The showerhead is arranged at a top of the process chamber. The upper electrode power supply is electrically connected to the showerhead. The lower electrode mechanism includes a carrier device configured to carry a wafer and grounded. The carrier device includes a base body configured to carry a wafer. An outer diameter of the base body is smaller than a diameter of the wafer. The edge ring surrounds the base. An outer diameter of the edge ring is greater than the diameter of the wafer. An outer circumferential surface of the base body faces and is spaced from an inner circumferential surface of the edge ring to form a first annular channel. The first annular channel is configured to communicate with a gas supply system. When the base body carries the wafer, an upper surface of the edge ring faces and is spaced from a lower surface of the wafer to form a second annular channel. The first annular channel communicates with the second annular channel. A first width of the first annular channel in a radial direction of the base and a second width of the second annular channel in an axial direction of the base are smaller than or equal to twice a plasma sheath layer thickness generated when the semiconductor processing equipment performs a predetermined process.
The present disclosure includes the following beneficial effects.
In the carrier device of the semiconductor processing equipment of embodiments of the present disclosure, the outer circumferential surface of the base body can face and be spaced from the inner circumferential surface of the edge ring to form the first annular channel. When the base body carries the wafer, the upper surface of the edge ring can face and be spaced from the lower surface of the wafer to form the second annular channel. The first annular channel can communicate with the second annular channel and form the edge purge channel with the inlet channel of the first step member. When the edge purge channel blows gas, the back surface and side surface of the wafer can be purged, which prevents the thin film deposition on the back surface and side surface of the wafer. Thus, the uniformity of the thin film can be improved, the temperature of the edge ring can be reduced, and the thin film deposition on the surface of the edge ring can be reduced. Based on the edge purge channel, by causing the first width of the first annular channel in the radial direction of the base and the second width of the second annular channel in the axial direction of the base to be smaller than or equal to twice the plasma sheath layer thickness generated when the semiconductor processing equipment performs the predetermined processes. Thus, by ensuring the channel under the edge of the wafer to be smooth, the space of the edge purge channel can be reduced, which prevents the back surface of the wafer from discharging or sparking in the channel. Then, the process stability can be improved, and the particle contamination can be reduced.
To cause those skilled in the art to better understand the technical solutions of the present disclosure, semiconductor processing equipment and a carrier device in the semiconductor process equipment of embodiments of the present disclosure are described in detail below in connection with the accompanying drawings.
Embodiments of the present disclosure provide semiconductor process equipment. The semiconductor process equipment can be, for example, the Metal-organic Chemical Vapor Deposition (MOCVD) equipment.
As shown in
A carrier device is arranged in the chamber body 1. The carrier device includes a base 6 and an edge ring 7 surrounding the base 6. The base 6 can be configured to carry the wafer 8 and can also function as a heater to heat the wafer 8 to a temperature required for thin film deposition. The base 6 can be made of a metal material (e.g., aluminum or stainless steel) and can be grounded. The edge ring 7 can be made of a metal material (e.g., aluminum or stainless steel) and can be configured to prevent a thin film from depositing on the surface of the base 6 (including the back surface) during the process.
As shown in
In some embodiments, the surface of the edge ring 7 (e.g., the upper surface of the edge ring 7 in
In some embodiments, the base body includes a main body 6a and a second annular protrusion 6b protruding from the outer peripheral surface of the main body 6a. In some embodiments, as shown in
Further, as shown in
During the deposition process, the inlet channel 61 can be configured to blow the gas into the edge purge channel. The gas can blow out from the edge of the wafer 8 through the edge purge channel, which prevents the thin film from being deposited on the back surface and edge of the wafer 8. During performing a plasma processing process, the inlet channel 61 does not blow a gas. However, since the edge purge channel communicates with the reaction chamber, the insulated wafer 8 can be charged in the plasma environment to form a high potential, while the edge ring 7 and the base 6 are both grounded at zero potential. Thus, a voltage difference can exist between the wafer 8 and the edge ring 7 and the base 6. Thus, sparks need to be prevented between the edge ring 7 and the bottom surface and side surface of the wafer 8. However, in the sizes of the base 6, the edge ring 7, and the wafer 8, H1, H2, W1, and W2 can be greater than 1.3 mm. H2 and W1 can be close to 4 mm, which causes the internal space of the edge purge channel to be large. When the semiconductor processing equipment performs a predetermined process such as the plasma processing process, as the RF power applied to the reaction chamber increases, the process pressure becomes higher, the voltage on the wafer surface increases, the thickness of the plasma sheath layer generated by the process becomes smaller (can be reduced to below 500 micrometers). Thus, discharging can easily occur in the edge purge channel with a large space, which can affect the process stability and cause particle contamination. In addition, since W3 is smaller than 1 mm, the distance between the edge of the wafer 8 and the first annular protrusion can be close. Thus, the electric field strength between the edge of the wafer and the first annular protrusion can be high, and the arc discharging can easily occur.
To address the above issues, embodiments of the present disclosure provide a carrier device in the semiconductor process equipment. The carrier device can be, for example, applied to the MOCVD equipment. In some embodiments, as shown in
The base 6 includes a base body and a first step member 6c arranged at the bottom of the base body and protruding relative to the outer peripheral surface of the base body. In some embodiments, the base body includes a main body 6a and a second annular protrusion 6b protruding from the outer peripheral surface of the main body 6a. In some embodiments, the structure of the base body is not limited to this. In some embodiments, the base body may not be arranged at the second annular protrusion 6b, which is not limited in embodiments of the present disclosure.
The edge ring 11 is arranged at the first step member 6c. The outer diameter of the base body (including the main body 6a and the second annular protrusion 6b) is smaller than the diameter of the wafer 8, and the outer diameter of the edge ring 11 is larger than the diameter of the wafer 8. Moreover, the outer peripheral surface of the base body faces and is spaced from the inner peripheral surface of the edge ring 11 to form a first annular channel 13a. When the base body carries the wafer 8, the upper surface of the edge ring 11 faces and is spaced from the back surface (i.e., lower surface) of the wafer 8 to form a second annular channel 13b. The first annular channel 13a can communicate with the second annular channel 13b, and an inlet channel 61 is arranged at the first step member 6c. An outlet end of the inlet channel 61 can communicate with the first annular channel 13a. The first annular channel 13a and the second annular channel 13b can form the edge purge channel. During the deposition process, the inlet channel 61 can blow the gas into the edge purge channel, and the gas can pass through the edge purge channel to blow out from the edge of the wafer 8, which prevents the thin film from being deposited on the back surface and the edge of the wafer 8. During the plasma processing process, the inlet channel 61 does not blow gas.
In some embodiments, the first step member 6c can be saved. Thus, the edge ring 11 can be fixed to the base 6 relatively in any other suitable manner, and the first annular channel 13a can communicate with the gas supply system directly or through another pipe structure.
In a plasma, since a mass of an electron is smaller than a mass of an ion, and the moving speed of the electron is faster than the moving speed of the ion, the electron can first be adhered to the surface of the electrode to form a negative potential. The negatively charged electrode can repel electrons and attract ions to form an area near the electrode with an electron density smaller than an ion density. The area can be referred to as a plasma sheath layer, and the thickness of the area can be referred to as a plasma sheath layer thickness. In a limited area, the plasma can form a “sandwich” structure of sheath-neutral plasma-sheath. When the distance between electrodes (or walls) is less than twice the plasma sheath layer thickness, only overlapping plasma sheath layers can fit between the electrodes, and the neutral plasma area can be exhausted. Thus, free electrons can be significantly reduced, which causes a lack of collision ionization and causes the discharge to be impossible to be maintained. Thus, in a plasma environment, the width of the slot and the diameter of the pipe may need to be smaller than twice the plasma sheath layer thickness to prevent the discharge. The two members with significant potential differences can have a stronger electric field with a smaller distance. Thus, sparks can occur more easily. Thus, the members may need to maintain a sufficient insulation distance.
Based on the above principle, to prevent sparks between the edge ring 11 and the bottom surface and side surface of the wafer 8, a first width of the first annular channel 13a in a radial direction of the base 6 and a second width of the second annular channel 13b in an axial direction of the base 6 can be both less than or equal to twice of the plasma sheath layer thickness generated during the predetermined process (e.g., plasma processing process) performed by the semiconductor process equipment. Thus, the channel under the edge of the wafer can be ensured to be unblocked, the space of the edge purge channel can be reduced, which can suppress the occurrence of discharge or sparks on the back surface of the wafer 8 in the channel. Therefore, the process stability can be improved, and the particle contamination can be reduced to cause the process chamber to be applied under high power and high-pressure conditions and expand the process window.
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, the axial cross-sectional shape of the first annular channel 13a can be in a bent line shape. Thus, a “maze-like” edge purge channel can be formed, which can block the plasma from entering to a certain degree to further suppress the discharge or sparks of the back surface of the wafer in the channel.
The first annular channel 13a in the bent line shape can include a plurality of structures. For example, in some embodiments, as shown in
Moreover, the inner peripheral surface of the channel member 11b includes a first sub-surface 111, a second sub-surface 112, and a third sub-surface 113. The first sub-surface 111 faces and is spaced from the outer peripheral surface of the main body 6a to form the first annular sub-channel 131. The second sub-surface 112 and the second protrusion 6b face and are spaced from the end surface of the main body 6a (i.e., the upper end surface of the second annular protrusion 6b in
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, the first ring 11b1 and the annular body 11a have an integral structure. The second ring 11b2 has separate structures with both the first ring 11b1 and the annular body 11a. By causing the first ring 11b1 and the annular body 11a to have the integral structure, the structural stability can be improved. By causing the second ring 11b2 to have separate structures from the first ring 11b1 and the annular body 11a, the processing convenience and the design flexibility of the edge purge channel can be improved.
In some embodiments, the radial distance B4 between the inner peripheral surface of the first annular protrusion 12 and the side surface of the wafer 8 can be greater than twice the plasma sheath layer thickness. Thus, the plasma can stably discharge in the groove formed between the edge of the wafer 8 and the inner peripheral surface of the first annular protrusion 12, and the radial distance B4 can be sufficient to reduce the spatial electric field between the wafer 8 and the edge ring 11 with different potentials to further prevent the arc discharge. In some embodiments, the radial distance B4 can be greater than 1 mm.
Furthermore, the vertical height C1 of the main body 6a in the base body and the vertical height C2 of the second annular protrusion 6b can be set as needed.
In some embodiments, the surface of the edge ring 11 exposed in the plasma environment can be a surface after the insulation processing. Thus, the upper surface of the edge ring can be charged in the plasma environment to form a negative potential. Thus, the potential of the upper surface of the edge ring can be consistent with the potential of the upper surface of the wafer, or the voltage difference between the upper surface of the edge ring and the upper surface of the wafer can be small. Thus, the probability of discharging can be further reduced. The insulation processing can be performed in a plurality of methods, e.g., surface oxidation or ceramic coating.
In some embodiments, edge corners of the base 6 and the edge ring 11 can be rounded corners. Thus, the probability of the occurrence of the tip discharge can be reduced. The combination of rounded processing and surface insulation processing can be used to suppress the arc discharge between the wafer 8 and the edge ring 11.
In some embodiments, the inlet channel 61 can include a plurality of outlets, which are distributed uniformly in a circumferential direction along the first annular channel 13a. Thus, the gas can uniformly enter the first annular channel 13a to improve the process uniformity. In some embodiments, the inlet channel 61 can include a plurality of vertical holes and a plurality of horizontal channels. Outlets of the plurality of vertical holes can be used as the outlets of the inlet channel 61, which communicate with the first annular channel 13a, and can be uniformly distributed along the circumferential direction of the first annular channel 13a. the inlets of the vertical holes can communicate with outlets of the horizontal channels in a one-to-one correspondence. The inlets of the horizontal channels can converge at the center position of the base 6 and can communicate with the gas supply system.
In some embodiments, the base 6 can be made of a metal material or an insulation material. The insulation ring 11 can be made of a metal material or an insulation material. For the base 6 and the insulation ring 11 made of the metal material, the installation of the base 6 and the insulation ring 11 needs to consider thermal expansion. Thus, the width of the edge purge channel needs to be smaller than twice the plasma sheath layer thickness and also reserves a certain space for the thermal expansion of the base 6 and the insulation ring 11. In addition, if the deposited thin film is a metal material, the base 6 and the insulation ring 11 can be made of the metal material. If the deposited thin film is the insulation material (e.g., silicone oxide), the base 6 and the insulation ring 11 can be made of the insulation material (e.g., ceramic).
In summary, in the carrier device of the semiconductor processing equipment of embodiments of the present disclosure, the outer circumferential surface of the base body can face and be spaced from the inner circumferential surface of the edge ring to form the first annular channel. When the base body carries the wafer, the upper surface of the edge ring can face and be spaced from the lower surface of the wafer to form the second annular channel. The first annular channel can communicate with the second annular channel and form the edge purge channel with the inlet channel of the first step member. When the edge purge channel blows gas, the back surface and side surface of the wafer can be purged, which prevents the thin film deposition on the back surface and side surface of the wafer. Thus, the uniformity of the thin film can be improved, the temperature of the edge ring can be reduced, and the thin film deposition on the surface of the edge ring can be reduced. Based on the edge purge channel, by causing the first width of the first annular channel in the radial direction of the base and the second width of the second annular channel in the axial direction of the base to be smaller than or equal to twice the plasma sheath layer thickness generated when the semiconductor processing equipment performs the predetermined processes. Thus, by ensuring the channel under the edge of the wafer to be smooth, the space of the edge purge channel can be reduced, which prevents the back surface of the wafer from discharging or sparking in the channel. Then, the process stability can be improved, and the particle contamination can be reduced.
As another technical solution, embodiments of the present disclosure provide semiconductor processing equipment. The semiconductor processing equipment is similar to the semiconductor processing equipment shown in
In some embodiments, the semiconductor processing equipment can be metal-organic chemical vapor deposition equipment.
In the semiconductor processing equipment of embodiments of the present disclosure, with the carrier device of embodiments of the present disclosure, the channel under the edge of the wafer can be smooth, and the back surface of the wafer can be prevented from discharging or sparking in the channel. Thus, the process stability can be improved, and the particle contamination can be reduced.
The above embodiments are merely exemplary embodiments of embodiments of the present disclosure. The present disclosure is not limited to this. For those skilled in the art, modifications and improvements can be made without departing from the spirit and essence of the present disclosure. These modifications and improvements are within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110560026.1 | May 2021 | CN | national |
This application is a continuation of International Application No. PCT/CN2022/093044, filed on May 16, 2022, which claims the priority of Chinese Patent Application No. 202110560026.1, filed on May 21, 2021, the entire contents of all of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2022/093044 | May 2022 | US |
| Child | 18516653 | US |
