Patent Application
20080050922
We have observed that an integrated dielectric etch process for inter-level connect structures performed in a capacitively coupled etch chamber sometimes experiences a problem of chamber contamination caused by sputtering copper in the barrier open step. Opening the barrier necessarily exposes the underlying copper to the barrier etching environment. As always, some amount of over etching of the barrier is required to assure that all the barrier material is removed from over the entire wafer and in spite of any process drift. However, barrier materials are necessarily relatively rugged and difficult to etch. Removal of the barrier layer seems to necessitate reactive ion etching with ion energies of at least 20 eV. Such high ion energies will also sputter copper atoms from the relatively soft underlying copper contact 12 of
We believe that the process drift arises from copper contamination of the chamber. We confirmed this belief by pasting silicon coupons on the showerhead 42 and measuring by X-ray photoelectron spectroscopy (XPS) copper contamination on the coupons after repeated chamber use and then after chamber cleaning. The tests demonstrated the presence of copper after chamber use and the removal of the copper after the chamber cleaning of the invention.
Much of the experimental data was derived from tests using copper-covered non-production wafers based on other results which show that photoresist etch rates are nearly equally degraded after etching 25 production wafer in the integrated process and after etching for 30 seconds a wafer having a blanket copper surface in a process designed for the photoresist etch. Accordingly, rather than use expensive production wafers for much of the development work, copper-covered test wafers were subjected to conditions intended for dielectric etching of production wafers.
We believe that the copper deposited on chamber parts, especially the showerhead electrode, greatly affect the etching chemistry and needs to be removed. Although manual wet cleaning of the chamber is conventionally performed, the quick onset of degraded etch rate would necessitate manual cleaning on a schedule severely reducing chamber throughput as well as incurring heavy personnel costs. It is possible to use a separate chamber for the barrier open, which itself seems to suffer little from the process drift caused by copper contamination. However, an integrated process is much preferred in which the entire dielectric etch sequence is performed in a single etch reactor.
According to the invention, the etch chamber is dry cleaned on a frequent basis, for example, once for each wafer cycle. In this embodiment, a wafer cycle is performed according to the process illustrated in the flow chart of
A waferless chamber clean is preferred because it increases throughput and reduces wafer scheduling complexities. However, the waferless chamber clean exposes the pedestal electrode to the chamber cleaning plasma. Accordingly, in a dummy-wafer cleaning embodiment of the invention, after the etched production wafer has been removed from the chamber in step 126, in step 130, a dummy wafer is inserted into the etch chamber and placed upon the pedestal electrode during the chamber cleaning step 128. A dummy wafer is a non-production wafer which is used repeatedly in the cleaning step 128 to protect the pedestal electrode. After the chamber cleaning, in step 132, the dummy wafer 132 is removed from the cleaned chamber before the process returns to its start for another cycle.
It is of course understood that the chamber cleaning step 128 and the dummy wafer transfer steps 130, 132 if any may be considered to be performed at the beginning of the wafer cycle. Nonetheless, at least in these two embodiments, the chamber cleaning is performed for every wafer cycle to recover the original conditions in the plasma etching chamber.
Etching recipes are summarized in TABLE 1 for three steps of the production etching and for two types of waferless chamber recovery.
The values of the parameters are quoted for a 300 mm chamber. The gas flows are given in units of sccm (standard cubic centimeter). The three production etch recipes are exemplary for those used to etch the lower portion of the tri-layer photomask, to etch the silicon carbide (SiC) barrier, and the final ashing step. Silicon carbide may be considered a dielectric in this application because it is etched with etching gases similar to those used for the main dielectric layer. The fluorocarbon etch of the main dielectric layer is not presented here since it seems to be relatively unaffected by the copper contamination and depends upon the details of the dielectric, for example, whether silica or a low-k dielectric. These recipes do not account for the control of radial uniformity provided by the differential gas feed and the magnetic coils around the top of the chamber, features needing optimization but not crucial to the present invention.
The table summarizes two types of chamber recovery, oxidizing and reducing. In both types of waferless recovery the VHF source applied a high plasma source power to generate an intense plasma in the area adjacent the showerhead and distant from the wafer pedestal. However, no biasing power is applied to the unprotected pedestal. Added pedestal biasing would accelerate plasma ions to the pedestal and tend to sputter etch it. Instead, the plasma etching is concentrated on the showerhead and other chamber parts.
The oxidizing recovery uses only oxygen gas (O2) as an etch gas. Other oxidizing gases could be substituted, for example, ozone (O3). Although the oxygen cleaning was productive, its results were less favorable than for the reducing clean.
The reducing chemistry uses a combination of hydrogen and nitrogen as the reducing etch gases. Recovery tests were performed using only hydrogen and using only nitrogen. Hydrogen alone was somewhat effective; nitrogen alone was productive but less so than hydrogen alone. The best observed results were obtained with the combination of hydrogen and nitrogen. The chamber recovery of the invention may use other reducing gases, for example, ammonia (NH3), which contains both hydrogen and nitrogen.
The reducing chamber recovery provides better results than the oxidizing chamber recovery in recovering the dielectric etch rates. However, a sequence of oxidizing and reducing chamber recovery, for example, an oxidizing chamber clean followed by a reducing chamber clean, seems to provide even better results and can result in dielectric etch rates above the initial values.
Copper and metal contamination during a dielectric etch presents unique problems. Metallic layers such as copper and other metals and their alloys tend to form looser atomic bonds than dielectrics or silicon so that they are more easily sputtered by energetic dielectric etching ions. Metal compounds, especially oxides, are usually not volatile so that sputtered metals, even if originating from metal nitride dielectrics such as TaN, are more likely to settle on chamber parts than be exhausted from the system.
We believe that the reducing chemistry more effectively cleans copper contamination form the chamber. Copper and other metals undergoing a fluorocarbon etch tend to form metal fluoride residues on the chamber parts such as CuFx. Aluminum fluoride is particularly difficult to remove. Metal fluorides can be reduced in a reducing clean.
A long-term test was performed by applying the SiC barrier open etch to a silicon wafer pasted with five 2 cm×2 cm copper tape for a 2.8% copper exposure. After each barrier open step, a waferless recovery was performed applying the above reducing recovery for 20 s followed an oxidizing plasma clean for 30 s including 1900 sccm of O2 and 2000 W of source power at a chamber pressure of 500 milliTorr. Periodically, the photoresist and ashing rates were measured on other test wafers covered with photoresist. The results over 100 wafer cycles are presented in the graph of
A recovery using a dummy wafer of blank silicon has the advantage of protecting the sensitive parts of the pedestal including electrostatic chuck and thermal gas channels during the recovery. Three dummy-wafer recovery recipes were developed. The separate recipes are summarized in TABLE 2.
Since the pedestal is protected during the recovery step, significant wafer bias may be applied to the pedestal to thus increase the density of the plasma. The fluorocarbon (F/C) recovery shows positive effects but significantly less than the oxidizing or reducing recovery. Again, the reducing recovery, especially with the combination of hydrogen and nitrogen, is more effective than the oxidizing recovery in restoring the production etch rates.
Although the insertion of dummy wafers during chamber cleaning allows more aggressive etching to effect the cleaning, the dummy wafer presents a handling and scheduling problem which reduces the system throughput. Throughput with a dummy-wafer recovery would be increased if the recovery could be postponed till after a significant number of production wafers were etched, for example, the approximately 25 wafers contained in a cassette. That is, if the sensitivity of the dielectric etch steps to copper contamination can be reduced by optimizing the dielectric etch conditions, recovery need not be performed for every wafer cycle. Then, a small number, preferably one, of dummy wafers may be loaded into the cassette and transferred into the etch chamber in turn when the chamber is cleaned once or only a few times per cassette rather than for every production wafer.
In some circumstance, it is possible to perform the chamber cleaning with the production wafer supported on the pedestal.
Although the chamber recovery of the invention has been described for structures including a copper layer underlying a dielectric layer such as a barrier layer, it may be applied to other structures with different underlying metal layers, such as aluminum metallization comprising no more than 10 at % of non-aluminum elements. Similarly, the barrier layer may be materials other than silicon carbide, such as silicon nitride (Si3N4), silicon oxynitride, or BLoK dielectric, which is a barrier material developed by Applied Materials and comprising silicon nitride and carbon. Although the invention has been described for the VHF-powered diode chamber of
The invention thus substantially reduces process drift in the dielectric etching of advanced integrated circuits, particularly those utilizing copper metallization.
