1. Field of the Invention
The invention relates to a chip package and method for forming the same, and in particular relates to a chip package formed by using a wafer-level packaging process.
2. Description of the Related Art
The chip package packaging process is one important step when forming electronic products. A chip package not only protects the chips from environmental contaminants, but also provides electrical connections between electronic elements in the chip and electronic elements outside of the chip.
Chip package technologies which can reduce the sizes of the chip packages, can fabricate the chip packages in mass production, can ensure the quality of the chip packages, and can reduce the time and cost of fabrication, have become important issues.
An embodiment of the invention provides a chip package, including: a chip, including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed on the chip; and a spacer layer disposed between the chip and the cover substrate, wherein a cavity is created and surrounded by the spacer layer, the chip and the cover substrate on the device region, and wherein the spacer layer directly contacts the chip, and no adhesive glue is disposed between the chip and the spacer layer.
An embodiment of the invention provides a method for forming a chip package, including: providing a wafer, including: a semiconductor substrate having a first surface and a second surface; a plurality of device regions formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a plurality of conducting pad structures disposed in the dielectric layer, and each of the conducting pad structures is electrically connected to one of the device regions; providing a cover substrate; forming a spacer layer on the wafer or the cover substrate; mounting the cover substrate onto the wafer such that the spacer layer is located between the wafer and the cover substrate, wherein a plurality of cavities is created and surrounded by the spacer layer, the wafer and the cover substrate, and each of the cavities is located over one of the device regions, and wherein the spacer layer directly contacts the wafer, and there is no adhesive glue disposed between the wafer and the spacer layer; and performing a dicing process along a plurality of predetermined scribe lines of the wafer for forming a plurality of separated chip packages.
An embodiment of the invention provides a chip package, including: a chip, including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses disposed on the first surface and on the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein a cavity is created and surrounded by the spacer layer, the chip and the cover substrate on the device region; and at least one main lens disposed on the cover substrate and in the cavity, wherein a width of the main lens is greater than a width of each of the micro-lenses.
An embodiment of the invention provides a method for forming a semiconductor structure, including: providing a wafer, including: a semiconductor substrate having a first surface; a plurality of device regions formed in the semiconductor substrate; and a plurality of micro-lenses disposed on the first surface and on the device regions; providing a cover substrate; forming a plurality of main lenses on the cover substrate, wherein a width of each of the main lenses is greater than a width of each of the micro-lenses; forming a spacer layer on the wafer or the cover substrate; and mounting the cover substrate onto the wafer such that the spacer layer is located between the wafer and the cover substrate, wherein a plurality of cavities are created and surrounded by the spacer layer, the wafer and the cover substrate, and each of the cavities is located over one of the device regions, and each of the cavities accommodates at least one of the main lenses corresponding to at least two of the micro-lenses.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, descriptions of a first layer “on,” “overlying,” (and like descriptions) a second layer, include embodiments where the first and second layers are in direct contact and those where one or more layers are interposed between the first and second layers.
A chip package according to an embodiment of the present invention may be used to package a variety of chips. For example, the chip package of the embodiments of the invention may be applied to active or passive elements, or electronic components with digital or analog circuits (digital or analog circuits), such as optoelectronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, and physical sensors for detecting the physical quantity variation of heat, light, or pressure. Particularly, a wafer scale package (wafer scale package; WSP) process may be applied to package semiconductor chips such as image sensor devices, light-emitting diodes (light-emitting diodes; LEDs), solar cells (solar cells), RF circuits (RF circuits), accelerators (accelerators), gyroscopes (gyroscopes), micro actuators (micro actuator), surface acoustic wave devices (surface acoustic wave devices), pressure sensors (pressure sensors), ink printer heads (ink printer heads), or power MOSFET modules (power MOSFET modules).
The wafer scale package process mentioned above mainly means that after the package process is accomplished during the wafer stage, the wafer with chips is cut to independent packages. However, in a specific embodiment, separated chips may be redistributed overlying a supporting wafer and then be packaged, which may also be referred to as a wafer scale package process. In addition, the above mentioned wafer scale package process may also be adapted to form chip packages of multi-layer integrated circuit devices (multi-layer integrated circuit devices) by stacking (stack) a plurality of wafers having integrated circuits. In one embodiment, the diced package is a chip scale package (CSP). The size of the chip scale package (CSP) may be only slightly larger than the size of the packaged chip. For example, the size of the chip package is not larger than 120% of the size of the packaged chip.
The wafer 10 may further comprise a dielectric layer 106 disposed on the surface 100a of the semiconductor substrate 100 and a plurality of conducting pad structures 104 disposed in the dielectric layer 106. Each of the conducting pad structures 104 electrically connects to one of the device regions 102. In an embodiment, an optical element 108 may be optionally formed in the device regions 102. The optical element 108 may comprise a lens/or a color filter layer.
Then, a cover substrate 110 is provided. The cover substrate 110 may have a size and profile similar to the size and profile of the wafer 10. The cover substrate 110 may be a transparent substrate, such as a glass substrate. In an embodiment, the cover substrate 110 may be an IR glass substrate.
Then, a spacer layer 112 may be formed on the wafer 10 or the cover substrate 110. In the embodiment shown in
For example, in an embodiment, a spacer material layer (not shown) may be formed on the cover substrate 110 using a spray coating process or a spin coating process. Then, exposure and development processes may be performed to the spacer material layer for patterning the spacer material layer as the spacer layer 112 shown in
Then, as shown in
The embodiments of the present invention are not limited to this. In another embodiment, as shown in
As shown in
As shown in
As shown in
Then, a dicing process may be performed along a plurality of scribe lines SC of the wafer 10 for forming a plurality of separated chip packages. The dicing process may be single cutting or segmented cutting processes. As shown in
Then, as shown in
Then, a dicing process may be performed along a plurality of predetermined scribe lines SC of the wafer 10 for forming a plurality of separated chip packages. The dicing process may be single cutting or segmented cutting processes. As shown in
However, it should be noted that the embodiments of the present invention are not limited to this, the first dicing process further comprises dicing a first portion and a second portion of the cover substrate 110 at different times such that a portion of the cover substrate 110 between the first and second portions of the cover substrate 110 may be separated naturally. For example, a portion of the cover substrate 110 at a left side of the scribe line SC and a portion of the cover substrate 110 at a right side of the scribe line SC are diced at different times such that the middle portion of the cover substrate 110 can be separated naturally.
Then, as shown in
There are many variations of the embodiments of the present invention. For example,
As shown in
The spacer layer 112 may be a stack of a plurality of patterned material layers formed by performing multiple deposition, exposure and development processes. Alternatively, the spacer layer 112 may be a single layer of the patterned spacer material.
Firstly, referring to
In another embodiment, the main lenses 120 may first be formed on the cover substrate 110, and then the spacer layer 112 is formed. In this case, because the height H1 of the main lens 120 is much less than the height H2 of the spacer layer 112, the uniformity of the heights of the main lenses 120 formed first is due to the flat surface of the cover substrate 110 facilitating a uniform coating, and the uniformity of the heights of the spacer layer 112 formed second is also due to the height H1 of the main lens 120 being very small.
In one embodiment, the spacer layer 112 is a transparent film. In this case, the steps for forming the spacer layer 112 may be described as follows. A transparent material layer (such as a transparent photoresist material, not shown) is fully coated on the cover substrate 110. Although the transparent material layer covers alignment marks (not shown) on the cover substrate 110, the transparent material layer is light transmissive, so the alignment marks may be accurately detected to perform a photolithography process, so as to pattern the transparent material layer.
In one embodiment, the material of the spacer layer 112 is a photoresist layer with viscosity while being heated and/or compressed. Therefore, during the subsequent wafer-bonding process, the spacer layer 112 may be compressed and/or heated to have viscosity so as to directly adhere to the cover substrate 110 and the wafer.
Referring to
In one embodiment, the wafer 10 may further include a dielectric layer 106 and a conducting pad structure 104. The dielectric layer 106 is disposed on the surface 100a, and the conducting pad structure 104 is disposed in the dielectric layer 106 and electrically connected to the device regions 102. Specifically, the projection of the spacer layer 112 on the surface 100a may be between the projection of the conducting pad structure 104 on the surface 100a and the projection of the device region 102 on the surface 100a. In brief, the spacer layer 112 may be located between the conducting pad structure 104 and the device region 102. In other embodiments not shown, the spacer layer 112 may be located on the conducting pad structure 104.
In one embodiment, a color filter layer CF may be formed on the device regions 102, wherein the color filter layer CF has red filter films R, green filter films G and blue filter films B, and the micro-lenses 108a are located on the red filter films R, the green filter films G and the blue filter films B, respectively.
Then, the cover substrate 110 is flipped and is disposed on the wafer 10, such that the spacer layer 112 is located between the wafer 10 and the cover substrate 110, wherein cavities 109 may be created and surrounded by the spacer layer 112, the wafer 10 and the cover substrate 110. Each cavity 109 is located on a corresponding device region 102, and each cavity 109 accommodates micro-lenses 108a and one or more main lens(es) 120.
Although,
It should be noted that the width W1 of each main lens 120 is greater than the width W2 of each micro-lens 108a (such as about 90 nm). In one embodiment, the projection of the main lens 120 on the surface 100a overlaps the projections of at least two micro-lenses 108a on the surface 100a. That is, one main lens 120 may be located right above the micro-lenses 108a at the same time. For example, the projection of a main lens 120 on the surface 100a overlaps three micro-lenses 108a respectively located on the red filter film R, the green filter film G and the blue filter film B (not shown).
It should be noted that, although the present embodiment illustrates the forming of the spacer layer 112 on the cover substrate 110, the present invention is not limited thereto. In other embodiments, the spacer layer 112 may be formed on the wafer 10 first, ant then the cover substrate 110 with the main lenses 120 is assembled with the wafer 10.
Then, referring to
Then, a dicing process may be performed along the predetermined scribing lines SC of the wafer 10 to form chip packages separated from each other. The dicing process may be a single cutting or segmented cutting processes. As shown in
A chip (cut from the wafer) in the chip package 600 may include a semiconductor substrate 100, a device region 102 and micro-lenses 108a. In one embodiment, the chip 610 is a chip processed by a thinning process, and the thickness T of the chip 610 ranges from about 20 μm to about 50 μm.
It should be noted that the present embodiment forms the main lens 120 and the micro-lenses 108a in a single chip package 600, such that the chip package 600 with a small size may have the functions of a conventional optical lens with a large size, and thus the chip package 600 may replace the conventional optical lens to effectively reduce the total volume of optical apparatuses (such as cameras).
Then, as shown in
As a result, the subsequent processes (such as the process of forming the spacer layer 112) may be performed on a more planar surface, and the main lenses 120 are protected from the contamination of the subsequent processes (such as the process of forming the spacer layer 112).
In one embodiment, the process of forming the transparent planar layer 130 includes, for example, performing a chemical vapor deposition process on the surface 110a of the cover substrate 110 to form an oxide layer covering the main lenses 120. In another embodiment, the transparent planar layer 130 includes, for example, polymer materials or other suitable transparent insulating materials.
Firstly, the process of
Then, a dicing process is performed along predetermined scribing lines SC of the wafer 10 to form chip packages separated form each other. The dicing process may be single cutting or segmented cutting processes.
As shown in
Then, as shown in
The chip package technology provided by the embodiments of the present invention may reduce the sizes of the chip packages, fabricate the chip packages in mass production, ensure the quality of the chip packages, and/or reduce the time and cost of fabrication.
The present embodiments of the present invention forms the main lens and the micro-lenses in a single chip package, such that the chip package with a small size may have functions of a conventional optical lens with a large size, and thus the chip package may replace the conventional optical lens to effectively reduce the volume of optical apparatuses.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
This application claims the benefit of U.S. Provisional Application No. 61/662,188, filed on Jun. 20, 2012, the entirety of which is incorporated by reference herein.
Number | Date | Country | |
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61662188 | Jun 2012 | US |