Patent Application
20080017405
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the office upon request and payment of the necessary fee.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
Referring to
A triangular tip 6021 formed on the copper region 602 extends toward the grounding trace 202. In this embodiment, a tip 2021 formed on the grounding trace 202 corresponds to the tip 6021, which shortens the distance between the tip 6021 and the grounding trace 202. Similarly, a tip 6041 formed on the copper region 604 extends toward the grounding trace 204. A tip 2041 formed on the grounding trace 204 corresponds to the tip 6041.
Further, the grounding trace can have no tips, for example grounding trace 206. The copper regions 606 and 608 have two tips 6061 and 6081, respectively, toward the grounding trace 206. As the tips 6061 and 6081 are close to the grounding trace 206, no tips are needed on the grounding trace 206.
The tips on the copper region have potential difference from the grounding trace, whereby static electricity discharges from the tips to the grounding trace. The static electricity transmitted from exterior environment via the signal trace 100 to the circuit board 1000 discharges to the grounding traces 202, 204 and 206. The amount, shape and positions of the tip are not limited, according to circuit design and layout. The distance between the tip to the grounding trace is as small as possible, but limited by the minimal distance between two traces formed during manufacture. Too small a distance may cause trace short. For the current technology, the minimal distance is 5 mil.
The invention is applied to a main board (CAYMAN-RH) produced by GIGA-BYTE technology Co., LTD. Static electricity test is performed on the USB interface. For the circuit layout of
In addition, for some circuit boards with high voltage limits, the Zener diode can be combined with the tips. In such a condition, the copper regions 602, 604, 606 and 608 and pads 400 can be served as pads for the Zener diode electrically connecting to the circuit board 1000. Two pads 400 are connected to the power trace 300 and the grounding trace 206. The combination of Zener diode and the tips raises the voltage limit to 9 kV.
The tip can be formed on the pads for the Zener diode in certain circuit boards, thereby raising the voltage limit of the circuit board. The invention provides flexibility in anti-static design. Tips are added to the original circuit layout, which can reach the same voltage limit as the Zener diode used in conventional technology. The combination of the tips and the Zener diode can reach even higher voltage limit.
In addition to the Zener diode, the invention can also be applied to the pads for anti-static element of Video chips or other I/O traces needed protection from static electricity.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
