Circuit board and circuit structure

Abstract

A circuit board for carrying a chip is provided. The circuit board includes a substrate, a wiring layer and a solder mask. The wiring layer including a cutting line pattern defining a cutting region is disposed on the substrate. The solder mask including a chip region, a first opening and a second opening is disposed on the substrate and the wiring layer. The chip region is disposed inside the cutting region. The chip is suitable to be disposed in the chip region, wherein the chip overlaps the chip region. The first opening and the second opening are respectively disposed outside two adjacent lateral sides of the chip region for exposing a part of the cutting line pattern. The exposed part of the cutting line pattern is used for measuring the position of the chip relative to the substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Prior Art) is a perspective illustrating a chip is positioned according to a positioning mark on a circuit board according to a conventional technology;

FIG. 2 is a top view of a circuit board according to an embodiment of the invention;

FIG. 3 is a cross-sectional view along the cross-sectional line AA of FIG. 2;

FIG. 4 is a top view of a circuit board according to another embodiment of the invention; and

FIG. 5 is a perspective of a circuit structure according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 is a top view of a circuit board according to an embodiment of the invention. FIG. 3 is a cross-sectional view along the cross-sectional line M′ of FIG. 2. Referring to both FIG. 2 and FIG. 3, the circuit board 300 includes a substrate 310, a wiring layer 320 and a solder mask 330. In the present embodiment of the invention, the substrate 310 can be a single-layered core dielectric layer. Besides, the substrate 310 can be formed by a plurality of wiring layers and a plurality of dielectric layers alternating with one another, wherein a wiring layer is disposed between every two adjacent dielectric layers.

The wiring layer 320 is disposed on the substrate 310. The wiring layer 320 includes a circuit pattern 322 and a cutting line pattern 324. In the present embodiment of the invention, the circuit pattern 322 includes a plurality of internal pads 322a, external pads 322b and traces 322c, wherein the traces 322c are electrically connected between the internal pads 322a and the external pads 322b. The cutting line pattern 324 defines a cutting region C on the substrate 310, wherein the circuit pattern 324 is disposed outside the cutting region C. For example, the cutting line pattern 324 is formed by a plurality of metal wires, and the metal wires further form the cutting region C.

The solder mask 330 is disposed on the substrate 310 and the wiring layer 320. The solder mask 330 has a chip region D, a first opening 332 and a second opening 334. The chip region D is disposed inside the cutting region C. The first opening 332 and the second opening 334 are respectively disposed outside two adjacent lateral sides of the chip region D for exposing a part of the cutting line pattern 324. Besides, in the present embodiment of the invention, the solder mask 330 further has a plurality of third openings 336 and a plurality of fourth openings 338, wherein the third openings 336 and the fourth openings 338 respectively expose the internal pads 322a and the external pads 322b.

Preferably, the internal pads 322a, the external pads 322b and the part of the cutting line pattern 324 exposed by the first opening 332 and the second opening 334 further respectively include a metal layer 322a′, 322b′ and 324′ for preventing the internal pads 322a, the external pads 322b and the part of the cutting line pattern 324 exposed by the first opening 332 and the second opening 334 from being eroded or oxidized. The metal layer 322a′, 322b′ and 324′ are made of gold for example.

The circuit board 300 of the present embodiment of the invention can have a single cutting region C or a plurality of cutting regions C. FIG. 4 is a top view of a circuit board according to another embodiment of the invention. The circuit board 300′ is similar to the circuit board 300 except that the cutting line pattern 324 of the circuit board 300′ defines a plurality of cutting regions C. Preferably, an opening exists between any two adjacent cutting regions C, and the cutting regions C are arranged in a matrix.

According to the circuit board 300 disclosed in the invention, a chip is disposed on the circuit board 300 to form a circuit structure. Then, the cutting line pattern 324 exposed by the first opening 332 and the second opening 334 are used as a positioning mark for measuring the position of the circuit board 300 relative to the chip. The details of the circuit structure are stated below.

FIG. 5 is a perspective of a circuit structure according to an embodiment of the invention. The circuit structure 500 includes a circuit board 300 and a chip 400. The chip 400 is disposed on the solder mask 330, and a rear side of the chip 400 faces the circuit board 300. The chip 400 is disposed inside the chip region D, and the chip 400 overlaps the chip region D. Thus, the first openings 332 and the second openings 334 are respectively disposed outside two adjacent lateral sides of the chip 400.

According to the circuit board 500 disclosed in the invention, the part of the cutting line pattern 324 exposed by the first opening 332 and the second opening 334 are used as a positioning mark for measuring the position of the circuit board 300 relative to the chip 400. Firstly, a pad 410 is selected from a plurality of pads 410 on the chip 400 to be a fiducial pad 410′. Next, the distance from the fiducial pad 410′ to the part of the cutting line pattern 324 exposed by the first opening 332 is measured by a measuring device using the fiducial pad 410′ as a starting point. Then, the distance from the fiducial pad 410′ to the part of the cutting line pattern 324 exposed by the second opening 334 is measured using the fiducial pad 410′ as a starting point. Thus, the position of the circuit board 300 relative to the chip 400 is measured in the present embodiment of the invention. Once the position of the circuit board 300 relative to the chip 400 is measured, the pad 410 is electrically connected to the internal pad 322a via wire bonding process in the present embodiment of the invention.

Preferably, the present embodiment of the invention can further adjust the relative position between the chip 400 and the first opening 332 as well as the relative position between the chip 400 and the second opening 334 for improving the efficiency of measuring the position of the circuit board 300 relative to the chip 400. For example, in the present embodiment of the invention, the positions of the first opening 332 and the second opening 334 can be adjusted such that the first opening 332 and the second opening 334 are respectively disposed in the extended direction along the first lateral side 402 and the second lateral side 404 of the chip 400. Thus, in the present embodiment of the invention, the fiducial pad 410′ is used as the original point and the measuring device is moved along the extended direction of the first lateral side 402 for measuring the distance between the fiducial pad 410′ and the part of the cutting line pattern 324 exposed by the first opening 332. Afterwards, the fiducial pad 410′ is used as the original point, and the measuring device is moved along the extended direction of the second lateral side 404 for measuring the distance between the fiducial pad 410′ and the part of the cutting line pattern 324 exposed by the second opening 334.

According to the above disclosure of the invention, a part of the existing cutting line pattern is used as a positioning mark, hence the positioning mark of the invention does not reduce the layout space of other circuits disposed on the surface of the circuit board

As the first and the second openings are respectively disposed in the extended directions along the first and the second lateral sides of the chip in the invention, the technology of the invention measures the position of the circuit board relative to the chip faster than conventional technology does.

While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. A circuit board for carrying a chip, the circuit board comprising: a substrate;a wiring layer disposed on the substrate, wherein the wiring layer comprises a cutting line pattern defining a cutting region; anda solder mask disposed on the substrate and the wiring layer, wherein the solder mask comprises a chip region, a first opening and a second opening, the chip region is disposed inside the cutting region, the chip is suitable to be disposed on the chip region and overlaps the chip region, the first opening and the second opening are respectively disposed outside two adjacent lateral sides of the chip region for exposing a part of the cutting line pattern, and the exposed part of the cutting line pattern are used for measuring the position of the chip relative to the substrate.

2. The circuit board according to claim 1, further comprising a metal layer disposed on the exposed part of the cutting line pattern.

3. The circuit board according to claim 1, wherein the metal layer is made of gold.

4. A circuit structure, comprising: a circuit board, comprising: a substrate;a wiring layer disposed on the substrate, wherein the wiring layer comprises a cutting line pattern defining a cutting region; anda solder mask disposed on the substrate and the wiring layer, wherein the solder mask comprises a first opening and a second opening; anda chip disposed on the solder mask, wherein a rear side of the chip faces the substrate, the chip is disposed inside the cutting region, the first opening and the second opening are respectively disposed outside two adjacent lateral sides of the chip region for exposing a part of the cutting line pattern, and the exposed part of the cutting line pattern is used for measuring the position of the chip relative to the substrate.

5. The circuit structure according to claim 4, further comprising a metal layer disposed on the exposed part of the cutting line pattern.

6. The circuit structure according to claim 5, wherein the metal layer is made of gold.

7. The circuit structure according to claim 4, wherein the chip has a first lateral side and a second lateral side adjacent to the first lateral side, the first opening is substantially disposed along the extended direction of the first lateral side, and the second opening is substantially disposed along the extended direction of the second lateral side.