Patent Application
20220408563
This application claims the priority benefit of Taiwan application serial no. 110122308, filed on Jun. 18, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to a carrier for packaging, and more particularly, to a circuit board and a manufacturing method thereof.
With the advancement of manufacturing technology, light emitting diodes (LEDs) have been continuously enhanced through research and development, and their luminous efficiency and brightness are gradually enhanced, thereby expanding and adapting to the needs of various products. However, when the electric power and operating current of the LEDs are increased, the LEDs will generate more heat relatively, so that the LEDs are prone to be overheated, and thus their performance are affected, and even causing the failure of the LEDs.
The current carrier used for LED packaging has poor stability due to the inability to effectively dissipate heat. In addition, the cost of manufacturing a heat dissipation carrier is high. Therefore, how to improve the heat dissipation effect of the carrier with favorable stability in a low-cost manner is an urgent problem to be resolved at present.
The disclosure provides a circuit board, which has favorable heat dissipation and stability.
The disclosure provides a manufacturing method of a circuit board, which may reduce the manufacturing cost and have good manufacturing yield.
The circuit board of the disclosure includes a metal substrate, a resin layer, an insulating layer, and a first conductive structure. The metal substrate has a first through hole. The first through hole has a first width. A portion of the resin layer is disposed in the second through hole. The second resin layer has a second through hole. The second through hole has a second width. The insulating layer is disposed on at least one surface of the metal substrate.
A portion of the insulating layer contacts the resin layer. The first conductive structure is disposed in the second through hole. The first conductive structure penetrates through the metal substrate. The first width is greater than the second width.
The manufacturing method of the circuit board of the disclosure includes the following steps. A metal substrate is provided. The metal substrate is etched to form a first through hole, and the first through hole has a first width. A resin layer is formed in the first through hole. An insulating layer is formed on the resin layer. A conductive layer is formed on the insulating layer. The resin layer, the insulating layer, and the conductive layer are patterned to form a second through hole in the resin layer. The second through hole has a second width. A first conductive structure is formed on the conductive layer and in the second through hole, and the first conductive structure penetrates through the metal substrate. The first width is greater than the second width.
Based on the above, in the circuit board and the manufacturing method thereof according to an embodiment of the disclosure, since the metal substrate may be etched, the first through hole may be formed in the metal substrate without needs of using a designated metal drilling machine. Followingly, a general drilling process may be performed on the resin layer, the insulating layer, and the conductive layer. According to the above disposition manner, the disposition of the conductive structure in the manufacturing process of the circuit board of the embodiment may be completed through forming through holes in two steps, without using an expensive metal drilling machine for the relatively thick metal substrate to complete the disposition of the through holes. Therefore, the manufacturing process may be simplified, manufacturing time may be saved, and manufacturing cost may be reduced. In addition, the resin layer has favorable bonding with the metal substrate, so that the circuit board has good manufacturing yield. Moreover, the metal substrate has favorable heat dissipation characteristic, so the metal heat dissipation carrier and the circuit board have favorable heat dissipation property. When the circuit board is applied to the package of the light emitting diode, the circuit board can effectively provide the heat dissipation effect to the light emitting diode for attaining good stability.
The disclosure is more fully described with reference to the drawings of the embodiment. However, the disclosure may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, and the repeated descriptions are not repeated in the following paragraphs.
Hereinafter, an embodiment of the manufacturing method of the circuit board 10 is briefly described.
Referring to
In some embodiments, the metal substrate 110 may also be replaced by a glass substrate, a glass fiber substrate (FR-4), a printed circuit board (PCB), or a semiconductor silicon substrate, but the disclosure is not limited thereto. For example, the glass fiber substrate may include the material of glass fiber mixed with epoxy resin, but the disclosure is not limited thereto.
Followingly, the metal substrate 110 is etched to form the first through hole O1. The first through hole O1 has sidewalls 113, which connect the upper surface 111 and the lower surface 112. The first through hole O1 has a first width L1 (as shown in
In other embodiments, laser drilling or die punching may also be performed on the metal substrate 110 to form the first through hole O1.
It should be noted here that the number of the first through holes O1 in the embodiment of the disclosure is not limited to the number of the first through holes O1 shown in
Then, the resin layer 200′ is formed in the first through hole O1. For example, a resin material layer 200 is firstly disposed on the metal substrate 110 and in the first through hole O1. A portion of the resin material layer 200 may be disposed on at least one surface of the metal substrate 110, for example, on the upper surface 111 or the lower surface 112.
In some embodiments, the material of the resin material layer 200 includes an organic material or an organic polymer material, for example including polyimide (PI), polyamide, polybenzoxazole (PBO), benzocyclobutene (BCB), acrylic, siloxane, silicone, epoxy, a cyclo olefin polymer, other suitable materials, or a combination of the above materials, but is not limited thereto.
Referring to
After the grinding process, a portion of the resin material layer 200 may be removed to form the resin layer 200′ in the first through hole O1. In addition, a portion of the resin layer 200′ may be disposed on at least one surface of the metal substrate 110. Specifically, the resin layer 200′ has a contact portion 201. The contact portion 201 is disposed on at least one surface of the metal substrate 110. For example, the contact portion 201 is disposed on the upper surface 111, the lower surface 112, or on both surfaces 111 and 112. Based the above disposition manner, the resin layer 200′ may increase the contact area with the metal substrate 110 through the contact portion 201. In such fashion, the resin layer 200′ may be better bonded to the metal substrate 110, thereby reducing the risk of the resin layer 200′ being falling off from a first opening O1.
In some embodiments, the surface of the resin layer 200′ may be a curved surface, and the surface of the resin layer 200′ is located on the upper surface 111 or the lower surface 112. That is, a portion of the resin layer 200′ may be overlapped with the metal substrate 110. In addition, in a normal direction perpendicular to the metal substrate 110, the contour of the first through hole O1 is located in the contour of the resin layer 200′, but the present embodiment is not limited thereto.
Moreover, the insulating layers 121 and 122 are formed on the upper surface 111 and the resin layer 200′, and formed on the lower surface 112 and the resin layer 200′. In detail, the insulating layer 121 is disposed above the upper surface 112 and the resin layer 200′. The insulating layer 122 is disposed below the lower surface 111 and the resin layer 200′. The insulating layer 121 and the insulating layer 122 are, for example, formed on the upper surface 111 or the lower surface 112 of the metal substrate 110 on the entire surface, but the present embodiment is not limited thereto. In some embodiments, the insulating layer 121 and the insulating layer 122 have flat surfaces, for example, so that the insulating layer 121 and the insulating layer 122 may be applied as flat layers to improve the flatness and reliability of the overall structure.
In some embodiments, the materials of the insulating layer 121 and the insulating layer 122 include insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials or mixtures thereof but are not limited thereto. In other embodiments, the material of the resin layer 200′ may be the same as or different from the material of the insulating layer 121 and the insulating layer 122 but is not limited thereto.
In addition, the insulating layer 121 and the insulating layer 122 may be a single layer or a multi-layer stack, which is not limited to the exemplary embodiment shown in
In addition, conductive layers 131 and 132 are formed on the insulating layers 121 and 122, respectively. In detail, the conductive layer 131 is disposed above the insulating layer 121. The conductive layer 132 is disposed under the insulating layer 122. The materials of the conductive layer 131 and the conductive layer 132 include conductive materials such as metal or metal alloy (e.g., copper, or copper-aluminum alloy). In other embodiments, the materials of the conductive layer 131 and the conductive layer 132 further include transparent conductive materials, such as indium tin oxide (ITO), zinc oxide (ZnO), aluminum zinc oxide (AlZnO), or gallium zinc oxide (GaZnO) or other suitable transparent conductive materials but are not limited thereto. In some embodiments, the conductive layers 131 and 132 may be a stack of single-layer or multi-layer conductive materials, which is not limited to the exemplary embodiment shown in
In some embodiments, the conductive layer 131 and the conductive layer 132 may be copper foils. As shown in
In an unillustrated embodiment, an insulating layer and a conductive layer may also be disposed on either the upper surface or the lower surface of the metal substrate. Based on the above disposition manner, the insulating layer and the conductive layer are sequentially disposed on the upper surface and cover the resin layer. The resin layer is exposed on the lower surface. In such fashion, the metal substrate, the resin layer, the insulating layer, and the conductive layer may be applied as a metal heat dissipation carrier with a single-sided copper foil.
Referring to
In detail, the above patterning method includes a drilling process or a cutting process. The drilling process includes, for example, laser drilling process or tool drilling process. For example, the resin layer 200′, the insulating layers 121 and 122 and the conductive layers 131 and 132 may be drilled by the laser beams at the positions corresponding to the first through hole O1, so as to drill holes in the resin layer 200′, the insulating layers 121 and 122, and the conductive layers 131 and 132 to form openings. In some embodiments, a sidewall 103 of the resin layer 200′, the insulating layers 121 and 122, and the conductive layers 131 and 132 may be cut to form a continuous via, which penetrates through the resin layer 200′, the insulating layers 121 and 122, and the conductive layers 131 and 132. In other words, the second through hole O2 of the resin layer 200′ may further be a via penetrating through the resin layer 200′, the insulating layers 121 and 122, and the conductive layers 131 and 132. In some embodiments, the second through hole O2 may further penetrate through the metal substrate 110.
In some embodiments, since the resin layer 200′ is located in the first through hole O1, the second through hole O2 located in the resin layer 200′ may be located in the first through hole 01. That is, in the direction perpendicular to the normal line of the metal substrate 110, the contour of the second through hole O2 is located within the contour of the first through hole O1. The sidewalls 103 of the second through hole O2 are located between the sidewalls 113 of the first through hole O1.
In some embodiments, the first width L1 is greater than the second width L2. The first width L1 may be defined as the maximum distance between the opposite sidewalls 113 of the first through hole O1. The second width L2 may be defined as the maximum distance between the opposite sidewalls 103 of the second through hole O2. Based on the above-mentioned width ratio, the first opening O1 is not affected when a second opening O2 is formed, so as to provide favorable structural strength and quality.
Referring to
Specifically, the first conductive structure 140 has a first wiring layer 141, a third wiring layer 142, and a conductive through hole 143 connected to the first wiring layer 141 and the third wiring layer 142. The first wiring layer 141 is disposed above an upper surface 131T of the conductive layer 131. The third wiring layer 142 is disposed below a lower surface 132B of the conductive layer 132. From another perspective, a portion of the first conductive structure 140 is disposed on the conductive layer 131, and the conductive layer 131 is located between the insulating layer 121 and the portion of the first conductive structure 140. The conductive through hole 143 is disposed on the sidewall 103 of the second through hole O2 and electrically connected to the first wiring layer 141 and the third wiring layer 142. The conductive through hole 143 may penetrate through the metal substrate 110, the resin layer 200′, the insulating layers 121 and 122, and the conductive layers 131 and 132. In such fashion, the first conductive structure 140 may electrically connect the lines or circuit elements on the upper surface 111 of the metal substrate 110 to the lines or circuit elements on the lower surface 112 but is not limited thereto.
In some embodiments, the first wiring layer 141 or the third wiring layer 142 may include circuit patterns, conductive pads, and conductive structures penetrating through a dielectric layer but is not limited thereto. In some embodiments, the first wiring layer 141 and the third wiring layer 142 may be a stack of single-layer or multi-layer wiring layers, which is not limited to exemplary embodiment shown in
To this step, the fabrication of the circuit board 10 has been substantially completed. In the embodiment, the circuit board 10 may be an encapsulation carrier in which metal foils or wiring layers are provided on the upper and lower surfaces of the metal heat dissipation carrier 100. In other embodiments, an interconnect structure, a redistribution layer or other circuit elements may further be disposed on the upper surface or the lower surface of the circuit board 10 but is not limited thereto.
In an unillustrated embodiment, an insulating layer and a conductive layer may also be disposed on the upper surface of the metal substrate first. Moreover, the metal substrate is etched on the lower surface to form a first opening. Then, a resin material is formed in the lower surface and the first opening. Next, a grinding process is performed on the lower surface and the resin material to form a resin layer. Followingly, an insulating layer and a conductive layer are formed on the lower surface to complete manufacturing process of the metal heat dissipation carrier. The resin layer, the insulating layer, and the conductive layer are then patterned to form a second through hole penetrating through the metal substrate, the resin layer, the insulating layer, and the conductive layer. Moreover, the first conductive structure is disposed on the metal heat dissipation carrier, and the manufacturing process of the circuit board is completed.
In an embodiment of the disclosure, since the metal substrate 110 may be subjected to an etching process first, the first through hole O1 may be formed in the metal substrate 110 without using a designated metal drilling machine. Followingly, a common drilling process may be performed on the resin layer 220′, the insulating layers 121 and 122, and the conductive layers 131 and 132. Based the above disposition manner, the circuit board 10 of the embodiment may be fabricated through two steps of forming through holes without using an expensive metal drilling machine for the relative thick metal substrate 110 to accomplish the disposition of the through holes. Therefore, the manufacturing process may be simplified, the manufacturing time may be saved, and the manufacturing cost may be reduced. In addition, the contact portion 201 of the resin layer 220′ may be disposed on the upper surface 111 or the lower surface 112 of the metal substrate 110, so that the resin layer 200′ may be better bonded to the metal substrate 110, and better manufacturing yield can be achieved through the circuit board 10. Moreover, the metal substrate 110 has favorable heat dissipation, so that the metal heat dissipation carrier 100 and the circuit board 10 have favorable heat dissipation. When the circuit board 10 is applied to the package of the light emitting diode, the circuit board 10 can effectively provide the heat dissipation effect with good stability to the light emitting diode.
It must be noted here that the following embodiments continue to use the element numbers and part of the contents of the previous embodiments. Therefore, the same reference numerals are used to represent the same or similar elements, and reference may be made to the foregoing embodiments for some descriptions that omit the same technical content, which will not be repeated in the following embodiments.
In detail, the interconnect layer 170 is formed on the first conductive structure 140. The step of forming the interconnect layer 170 includes the following steps. A dielectric layer 150 is formed on the first wiring layer 141 of the first conductive structure 140. Next, the dielectric layer 150 is patterned to form a third through hole O3. The above patterning method includes a drilling process or a cutting process. The drilling process includes, for example, laser drilling process or tool drilling process. The third through hole O3 has sidewalls 153. In some embodiments, the second through hole O2 is overlapped with the third through hole O3 in a direction perpendicular to the normal line of the metal substrate 110. The contour of the third through hole O3 may be aligned with the second through hole O2 but is not limited thereto. In some embodiments, the contour of the third through hole O3 may be located inside or outside the contour of the second through hole O2.
In some embodiments, the material of the dielectric layer 150 is similar to the material of the insulating layer 121, and details are not repeatedly described herein.
Next, a second conductive structure 160 is formed above the dielectric layer 150 and in the third through hole O3. The formation method and material of the second conductive structure 160 are similar to those of the first conductive structure 140. Specifically, the second conductive structure 160 has a second wiring layer 161 and a second conductive through hole 163 connected to the second wiring layer 161. The second wiring layer 161 is disposed on the surface of the dielectric layer 151. The second conductive through hole 163 is disposed in the third through hole O3. The second conductive through hole 163 is disposed on the sidewall 153 of the third through hole O3. The second wiring layer 161 is electrically connected to the first conductive structure 140 through the second conductive through hole 163.
In an unillustrated embodiment, more dielectric layers and conductive structures may be disposed on the second conductive structure 160 to form interconnect layers in which multiple circuit layers and dielectric layers are stacked. The above-mentioned circuit layer may further include a conductive structure penetrating through the dielectric layer but is not limited thereto.
To this step, the fabrication of the circuit board 10′ has been substantially completed.
In such fashion, the circuit board 10′ may obtain the same effect as the above-mentioned embodiment.
Please refer to
Referring to
Then, the steps of forming the insulating layers 121 and 122, the conductive layers 131 and 131, and the first conductive structure 140 are sequentially performed to complete the disposition of the circuit board 10A. The above steps have been described in the preceding paragraphs, so that the descriptions are not repeated here.
Specifically, the interconnect layer 170 is disposed on the first conductive structure 140.
The interconnect layer 170 includes the dielectric layer 150 and the second conductive structure 160. The dielectric layer 150 is disposed on the first conductive structure 140. The dielectric layer 150 has the third through hole O3. The third through hole O3 overlaps the second through hole O2.
The second conductive structure 160 is disposed above the dielectric layer 150 and in the third through hole O3. The formation method and material of the second conductive structure 160 are similar to those of the first conductive structure 140. Therefore, the description is not repeated here. The second conductive structure 160 has a second wiring layer 161 and a second conductive through hole 163 connected to the second wiring layer 161. The second wiring layer 161 is disposed on the surface of the dielectric layer 151. The second conductive through hole 163 is disposed in the third through hole O3. The second conductive through hole 163 is disposed on the sidewall 153 of the third through hole O3. The second wiring layer 161 is electrically connected to the first conductive structure 140 through the second conductive through hole 163. The circuit board 10A′ may obtain the same effect as the above-mentioned embodiment.
In detail, in the grinding process in the step of forming the resin layer 20013′, the resin material layer may be ground to remove the resin material layer disposed on the upper surface 111 or the lower surface 112 of the metal substrate 110. In this way, the upper surface 211 of the resin layer 200B′ formed after grinding is flush with the upper surface 111 of the metal substrate 110. The lower surface 212 of the resin layer 200B′ is flush with the lower surface 112 of the metal substrate 110. Based on the above disposition manner, the metal heat dissipation carrier 100 or the circuit board 10B may be further thinned and thus has good heat dissipation and stability. In addition, the circuit board 10B may have excellent quality of being light and thin.
In summary, in the circuit board and the manufacturing method thereof according to an embodiment of the disclosure, since the metal substrate may be etched, the first through hole may be formed in the metal substrate without using a designated metal drilling machine. Next, a general drilling process may be performed on the resin layer, the insulating layer, and the conductive layer. According to the above disposition manner, the disposition of the conductive structure in the circuit board of the embodiment may be completed through two steps of forming through holes, without using an expensive metal drilling machine for the relative thick metal substrate to complete the disposition of the through holes. Therefore, the manufacturing process may be simplified, the manufacturing time may be saved, and manufacturing cost may be reduced. In addition, the resin layer has favorable bonding with the metal substrate, so that good manufacturing yield can be obtained through the circuit board. Moreover, the metal substrate has good heat dissipation, so the metal heat dissipation carrier and the circuit board have good heat dissipation. When the circuit board is applied to the package of the light emitting diode, the circuit board can effectively provide the heat dissipation effect with good stability to the light emitting diode.
| Number | Date | Country | Kind |
|---|---|---|---|
| 110122308 | Jun 2021 | TW | national |
