Patent Application
20240292539
Embodiments described herein generally relate to electrical interconnections and interconnect structures. Specific examples include electrical interconnections between circuit boards or other electrical distribution structures in devices that include semiconductor dies.
Board-to-board connections consume printed circuit board (PCB) area in computer systems where two or more boards need to connect to each other. The space consumed by current interconnect solutions between boards requires either enlarging system board dimensions or leaving less space for the system components. Each connector is also a cost adder for an electronic system.
In selected configurations, a height difference between components creates a situation where boards need to be on a different Z-axis level. This makes a system either difficult to assemble and service, or more expensive due to added cost of existing connector solutions, or both.
It is desired to have electrical connectors and methods that address these concerns, and other technical challenges.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
Electrical pathways are provided where conduction passes from a trace conductor on the first circuit board 118, through the standoff interposer 130 and through a trace conductor on the second circuit board 128. Although one or more semiconductor dies are shown on the circuit boards 118, 128, the invention is not so limited. Other examples of circuit board to circuit board conduction that do not involve dies are within the scope of the invention. Examples of conduction through traces and standoff interposers include, but are not limited to, data signals, power, ground, etc.
Although a central passage through the standoff interposer 130 is described, the invention is not so limited. A passage need not be central to the standoff interposer 130. In one example, the fastener 102 provides a compressive force on the standoff interposer 130 and enhances an electrical connection of one or more conductive pathways within the standoff interposer 130. Examples of an enhanced electrical connection includes, but is not limited to, compression of a spring interconnect.
In one example, the chassis 104 includes a device housing, such as an outer shell for a mobile phone, watch, GPS device etc. In one example, the chassis 104 includes an internal mounting frame in a computing device such as a desktop computer, a laptop computer, or server device, etc. In one example, connection to the chassis 104 is a direct connection. In one example, connection to the chassis 104 includes direct connection to a chassis that is integrally formed with an outer case. In one example, connection to the chassis 104 is indirect, and utilizes intermediate components to complete the physical connection.
In the example of
In one example of manufacture, a solderable pad end 240 of the standoff interposer 230 is soldered to the first circuit board 218 at a first circuit board connection surface 234 to make an electrical connection, and to hold the standoff interposer 230 in place. Then a fastener 202, such as a screw as illustrated in
In one example, an inner and an outer ground ring are included adjacent to mating pads 350, as shown in
In one example, a number of conductive pathways includes between 4 and 20 conductive pathways in a standoff interposer 330. In one example, a number of conductive pathways includes between 10 and 16 conductive pathways. Although multiple conductive pathways 336 are shown, and are arranged radially about a central axis, the invention is not so limited. A single conductive pathway is also within the scope of the invention, and arrangements for multiple conductive pathways other than radial are also within the scope of the invention. In one example, the conductive pathways include copper, although the invention is not so limited. Other conductor materials include other metals such as aluminum, steel, gold, silver, etc.
In one embodiment, processor 710 has one or more processor cores 712 and 712N, where 712N represents the Nth processor core inside processor 710 where N is a positive integer. In one embodiment, system 700 includes multiple processors including 710 and 705, where processor 705 has logic similar or identical to the logic of processor 710. In some embodiments, processing core 712 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 710 has a cache memory 716 to cache instructions and/or data for system 700. Cache memory 716 may be organized into a hierarchal structure including one or more levels of cache memory.
In some embodiments, processor 710 includes a memory controller 714, which is operable to perform functions that enable the processor 710 to access and communicate with memory 730 that includes a volatile memory 732 and/or a non-volatile memory 734. In some embodiments, processor 710 is coupled with memory 730 and chipset 720. Processor 710 may also be coupled to a wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna 778 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In some embodiments, volatile memory 732 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 734 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
Memory 730 stores information and instructions to be executed by processor 710. In one embodiment, memory 730 may also store temporary variables or other intermediate information while processor 710 is executing instructions. In the illustrated embodiment, chipset 720 connects with processor 710 via Point-to-Point (PtP or P-P) interfaces 717 and 722. Chipset 720 enables processor 710 to connect to other elements in system 700. In some embodiments of the example system, interfaces 717 and 722 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In some embodiments, chipset 720 is operable to communicate with processor 710, 705N, display device 740, and other devices, including a bus bridge 772, a smart TV 776, I/O devices 774, nonvolatile memory 760, a storage medium (such as one or more mass storage devices) 762, a keyboard/mouse 764, a network interface 766, and various forms of consumer electronics 777 (such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset 720 couples with these devices through an interface 724. Chipset 720 may also be coupled to a wireless antenna 778 to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.
Chipset 720 connects to display device 740 via interface 726. Display 740 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 710 and chipset 720 are merged into a single SOC. In addition, chipset 720 connects to one or more buses 750 and 755 that interconnect various system elements, such as I/O devices 774, nonvolatile memory 760, storage medium 762, a keyboard/mouse 764, and network interface 766. Buses 750 and 755 may be interconnected together via a bus bridge 772.
In one embodiment, mass storage device 762 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 766 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
While the modules shown in
To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:
Example 1 includes an electronic device. The electronic device includes a semiconductor die coupled to a first circuit board, and a second circuit board laterally overlapping a portion of the first circuit board. The electronic device includes a standoff interposer having a central passage, the standoff interposer located between the first circuit board and the second circuit board at the overlapping portion, the standoff interposer including one or more conductive pathways coupled between the first circuit board and the second circuit board, and a fastener passing through the central passage.
Example 2 includes the electronic device of example 1, further including a semiconductor die coupled to the first circuit board.
Example 3 includes the electronic device of any one of examples 1-2, wherein the standoff interposer is cylindrical.
Example 4 includes the electronic device of any one of examples 1-3, wherein the conductive pathways are arranged radially about the central passage.
Example 5 includes the electronic device of any one of examples 1-4, further including a ground ring on at least one side of the conductive pathways.
Example 6 includes the electronic device of any one of examples 1-5, further including an inner and outer ground ring adjacent to the conductive pathways.
Example 7 includes the electronic device of any one of examples 1-6, wherein at least one of the conductive pathways includes a spring at an end of the conductive pathway.
Example 8 includes the electronic device of any one of examples 1-7, wherein at least one of the conductive pathways includes solder at an end of the conductive pathway.
Example 9 includes the electronic device of any one of examples 1-8, wherein the fastener includes a screw.
Example 10 includes the electronic device of any one of examples 1-9, wherein the standoff interposer includes a polymer body and wherein the conductive pathways include copper.
Example 11 includes an electronic device. The electronic device includes a semiconductor die coupled to a first circuit board, and a second circuit board laterally overlapping a portion of the first circuit board. The electronic device also includes a standoff interposer having a central passage, the standoff interposer located between the first circuit board and the second circuit board at the overlapping portion, the standoff interposer including one or more conductive pathways coupled between the first circuit board and the second circuit board, and a fastener passing through the central passage, the fastener coupled to a chassis of the electronic device.
Example 12 includes the electronic example 11, wherein the chassis is integral with an outer case of the electronic device.
Example 13 includes the electronic device of any one of examples 11-12, further including an antenna in communication with the semiconductor die.
Example 14 includes the electronic device of any one of examples 11-13, further including a second die on the second circuit board.
Example 15 includes the electronic device of any one of examples 11-14, wherein the first circuit board includes a system on chip and wherein the second circuit board includes a graphics integrated circuit.
Example 16 include a method of forming an electronic device. The method includes placing a standoff interposer between an overlapping portion of a first circuit board and a second circuit board, aligning one or more conductive pathways within the standoff interposer with electrical pads on the first circuit board and the second circuit board, and securing a fastener through a central passage in the standoff interposer to hold the first circuit board, the second circuit board, and the standoff interposer together.
Example 17 includes the method of example 16, wherein securing the fastener includes compressing a spring on an end of at least one of the conductive pathways.
Example 18 includes the method of any one of examples 16-17, further including soldering at an interface of at least one of the conductive pathways.
Example 19 includes the method of any one of examples 16-18, wherein securing the fastener includes threading a screw.
Example 20 includes the method of any one of examples 16-19, further including injection molding a body around the one or more conductive pathways to form the standoff interposer.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single disclosure or inventive concept if more than one is, in fact, disclosed.
The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
As used herein, the term “or” may be construed in either an inclusive or exclusive sense. Moreover, plural instances may be provided for resources, operations, or structures described herein as a single instance. Additionally, boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in a context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within a scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within a scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various example embodiments with various modifications as are suited to the particular use contemplated.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the present example embodiments. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used in the description of the example embodiments herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.
