Circuit pattern exposure method and mask

Abstract

A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed in the mask to a semiconductor substrate, wherein the mask includes a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask patterns that are arranged outside the outermost main mask pattern and that are not to be transferred (offset) to the semiconductor substrate; the auxiliary mask patterns are provided with a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row; and the first auxiliary mask row and the second auxiliary mask row are arranged at a pitch that is narrower than the pitch of arrangement of the main mask patterns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing an example of DRAM that has been fabricated using the circuit pattern exposure method of the present invention;

FIG. 2 is a schematic view showing an example of the mask used in the circuit pattern exposure method of the present invention;

FIG. 3 shows an example of the distribution of the intensity of exposure light;

FIG. 4 is a schematic view showing another example of a mask used in the circuit pattern exposure method of the present invention;

FIG. 5 shows the distribution of the intensity of exposure light;

FIG. 6 shows another example of the distribution of the intensity of exposure light;

FIG. 7 shows another example of the distribution of the intensity of exposure light;

FIG. 8 is a schematic view showing another example of a mask used in the circuit pattern exposure method of the present invention;

FIG. 9 shows another example of the distribution of the intensity of exposure light;

FIG. 10 shows another example of the distribution of the intensity of exposure light;

FIG. 11 shows an example of mask in which the pitch of the auxiliary mask rows is wide; and

FIG. 12 shows the distribution of the intensity of exposure light when using the mask shown in FIG. 11.

Claims

1. A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed in the mask onto a semiconductor substrate, wherein: said mask comprises a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask pattern that is arranged outside the outermost main mask pattern and that is not transferred onto said semiconductor substrate; andsaid auxiliary mask pattern is composed of a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row, and said first auxiliary mask row and said second auxiliary mask row are arranged at a narrower pitch than the pitch of the arrangement of said main mask patterns.

2. A circuit pattern exposure method for irradiating illumination light onto a mask to transfer (offset) mask patterns that are formed in the mask onto a semiconductor substrate, wherein: said mask comprises a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask pattern that is arranged outside the outermost main mask pattern and that are not transferred onto said semiconductor substrate;said auxiliary mask pattern is composed of a first auxiliary mask row that is arranged adjacent to the outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to the first auxiliary mask row; andsaid first auxiliary mask row and said second auxiliary mask row are formed by a plurality of micro-masks arranged along said main mask patterns, and are arranged at a narrower pitch than the pitch of the arrangement of said main mask patterns.

3. The circuit pattern exposure method according to claim 2, wherein the micro-masks that form said second auxiliary mask row are larger than the micro-masks that form said first auxiliary mask row.

4. The circuit pattern exposure method according to claim 2, wherein the spacing of the arrangement of the plurality of micro-masks that form said second auxiliary mask row is narrower than the spacing of the arrangement of the plurality of micro-masks that form said first auxiliary mask row.

5. The circuit pattern exposure method according to claim 1, wherein the width of the outermost main mask pattern is greater than the width of other main mask patterns.

6. The mask in which mask patterns are formed that are to be transferred (offset) onto a semiconductor substrate; said mask comprising: a plurality of main mask patterns that are arranged at a prescribed pitch and auxiliary mask pattern that is arranged outside the outermost main mask pattern and that is not transferred (offset) to said semiconductor substrate;wherein said auxiliary mask pattern is composed from a first auxiliary mask row that is arranged adjacent to said outermost main mask pattern and a second auxiliary mask row that is arranged adjacent to said first auxiliary mask row, and said first auxiliary mask row and said second auxiliary mask row are arranged at a pitch narrower than the pitch of arrangement of said main mask patterns.

7. A mask in which mask patterns are formed that are to be transferred (offset) to a semiconductor substrate; said mask comprising: a plurality of main mask patterns arranged at a prescribed pitch, and auxiliary mask pattern that is arranged outside the outermost main mask pattern and that is not to be transferred (offset) to said semiconductor substrate;wherein said auxiliary mask pattern is composed of a first auxiliary mask row that is arranged adjacent to said outermost main mask pattern and a second auxiliary mask row arranged adjacent to said first auxiliary mask row; andsaid first auxiliary mask row and said second auxiliary mask row are formed by a plurality of micro-masks arranged along said main mask patterns, and are arranged at a pitch narrower than the pitch of the arrangement of said main mask patterns.

8. The mask according to claim 7, wherein micro-masks that form said second auxiliary mask row are larger than micro-masks that form said first auxiliary mask row.

9. The mask according to claim 7, wherein the spacing of the arrangement of the plurality of micro-masks that form said second auxiliary mask row is narrower than the spacing of the arrangement of the plurality of micro-masks that form said first auxiliary mask row.

10. The mask according to claim 6, wherein the width of the outermost main mask pattern is greater than the width of the other main mask patterns.