Patent Application
20140101500
In design for testability (DFT) applications, integrated circuits are often designed with scan test circuitry that is used during chip manufacturing to test for various internal fault conditions of an integrated circuit. Scan test circuitry typically comprises scan chains comprising multiple scan cells (registers), which are used to gain access to internal nodes of the integrated circuit. The scan cells may be implemented using a series of flip-flops or latches. The scan cells of a given scan chain are configurable to form a serial shift register for shifting in test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture outputs from other combinational logic of the integrated circuit. In this regard, scan testing of an integrated circuit may be viewed as being performed in two repeating phases, namely, a scan shift phase in which the scan cells of a scan chain are configured as a serial shift register for shifting in and shifting out of respective input and output scan data, and a scan capture phase in which the scan cells of the scan chain capture scan data from combinational logic. The captured data is subsequently shifted out to compare to expected patterns. These repeating scan test phases are often collectively referred to as a scan test mode of operation of the integrated circuit.
With regard to SoC (System-on-Chip) designs, when an SoC design development is complete, SoC bring up and debug processes are critical for successful operation in the field. In general, a debug process is time consuming and arduous, and internal SoC failures are hard to debug due to the limited ability to observe the state of internal registers inside an SoC. In order to debug failures in an SoC, however, chip designers need access to the state of the internal registers of the SoC. A debug test protocol for obtaining the internal register data state from an SoC should be simple. Moreover, this process should not add overhead to the SoC design in terms of area, routing congestion, and timing, for example.
Embodiments of the invention generally include circuits and methods for functional testing and debugging of an integrated circuit such as a system-on-chip. For example, in one embodiment, an integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The scan test circuitry includes one or more scan chains, where each scan chain includes a plurality of scan cells interspersed throughout regions of the core circuitry. The scan control circuitry is configured to utilize the scan test circuitry to scan test the core circuitry. The debug control circuitry is configured to utilize the scan test circuitry and control the scan control circuitry to implement a debug mode of operation to debug failure conditions of the core circuitry during normal use of the integrated circuit. A debug control scheme can be implemented using a Joint Test Action Group (JTAG) protocol, for example.
In another embodiment of the invention, a method is provided for debugging the integrated circuit to debug failure conditions of the core circuitry during normal use of the integrated circuit. The debug process includes utilizing the scan control circuitry to selectively apply a debug clock signal to a clock port of each scan cell of a given scan chain during the debug process to store data values that are generated by the core circuitry into the scan cells during the debug process, and controlling the scan control circuitry to perform a scan shift operation using the scan test circuitry to scan shift out the stored data values generated by the core circuitry during the debug process. A debug process allows failure conditions to be re-created and logic changes to be made core circuitry of the integrated circuit so that internal signals of the integrated circuit can be readily observed for verification.
Embodiments of the invention will be described or become apparent from the following detailed description of embodiments, which is to be read in connection with the accompanying drawings.
Embodiments of the invention will now be discussed in further detail below with regard to circuits and methods for functional testing and debugging of integrated circuits.
As further shown in
Furthermore, in an embodiment of the invention, debugging of failure conditions and errors of the integrated circuit 140 can be implemented using the internal registers 180, the debug controller 190, and the debug controller interface 192, in conjunction with the scan test circuitry 160 and the scan control circuitry 170 to verify operability of the integrated circuit 140 during actual use. In accordance with embodiments of the invention as discussed in further detail below with reference to
In an embodiment, a debug process (which is implemented via the debug protocol 124) provides various debug test signals such as debug test clocks and control signals, as well as debug test data to the integrated circuit 140. The debug test signals and test data are input to the debug controller 190 via the debug controller interface 192. The debug controller 190 uses these signals in conjunction with the scan control circuitry 170 to operate the scan test circuitry 160 and perform a debug process on the core circuitry 150, and store the results of the debug process in the internal registers 180. The internal state of the registers 180 is accessed by the debug controller 190 and output (via an output port of the interface 192) to the tester 110 over the interface 115, wherein the debug test output data can be stored as the internal register state data 134 in the memory 130 of the tester 110. In an embodiment, the debug protocol 124 and debug controller 190 are implemented using a JTAG scheme, although in alternate embodiments of the invention, other standard or non-standard debugging protocols may be used to implement debugging techniques based on techniques as described herein.
It is to be noted that the tester 110 in the testing system 100 of
In an embodiment, the integrated circuit 140 is configured for installation on a circuit board or other mounting structure in a computer, server, mobile telephone or other type of communication device. Such communication devices may also be viewed as examples of what are more generally referred to herein as “processing devices.” The term “processing devices” is also intended to encompass storage devices, as well as other types of devices comprising data processing circuitry.
Each of the scan chains 202 comprises a plurality of scan cells 204 that are interspersed with various circuit blocks of a core circuit that is under test. For instance,
In the embodiment of
In the embodiment of
In the embodiment of
The scan output multiplexer 210 has N inputs, wherein each of the N inputs is connected to the Q output port of a last scan cell 204 in a corresponding one of the plurality of scan chains 202. The scan output multiplexer 210 is controlled by a control signal applied on control line 226 from the JTAG TAP controller 220. The output of the scan output multiplexer 210 is connected to the JTAG user defined registers 224. The control signal applied on the control line 226 from the JTAG TAP controller 220 selects one of the scan chains 202 for outputting data of the selected scan chain 202 for storage in the JTAG user defined registers 224.
The control logic block 230 receives control signals from the JTAG TAP controller 220 via a control line 228. The control logic block 230 receives “debug mode” triggering events, such as error events and interrupt events (internal or external interrupts). The control signals applied on control line 228 serve to program the control logic block 230 for various functions. For example, a control signal may be applied on control line 228 to select which interrupt to be used for triggering a debug process. A control signal may be applied on control line 228 to program user-defined “wait” states that specify a time for waiting to trigger a debug process after receiving an error. A control signal may be applied on the control line 228 to program the control logic block 230 to recognize a sequence of events (errors) that causes the triggering of a debug process. In other embodiments, control signals may be applied on the control line 228 to specify a number of clock pulses to be generated through the OCC (on chip clock) logic for a debug process, and to enable access to programmable registers of the control logic block 230.
In accordance with embodiments of the invention, the scan test and control circuitry in
As shown in
An output of the clock signal select multiplexer M1 in connected to one input of the clock signal select multiplexer M2, and an output of the clock gating block 270 is connected to another input of the clock signal select multiplexer M2. The clock gating block 270 selectively outputs a gated JTAG test clock signal (gated TCK) to an input of the clock signal select multiplexer M2 in response the control signal applied on the control line 238. More specifically, in a debug mode of operation, when a SCAN mode is not present, a gated TCK clock signal (which applied to an input of the clock signal select multiplexer M2) will be selected for output from the clock signal select multiplexer M2 in response to the assertion of a control signal applied to the select control port of the multiplexer M2 via the control line 236. The number of TCK clock pulses that are output from the clock gating block 270 to the input of the clock signal select multiplexer M2 is controlled by a control signal applied on the control line 238. In this regard, when the JTAG clock TCK is selected for shifting data out through a JTAG port of the interface 222 during a debug mode of operation, the control logic block 230 will generate a control signal on line 238 that specifies a number of TCK clock pulses to be applied to the scan logic so that the status of only the required registers will be shifted out from the JTAG interface 222.
An output of the clock signal select multiplexer M2 is connected to one input of the clock signal select multiplexer M3. A functional mode clock signal is applied to another input of the clock signal select multiplexer M3. A select control port of the clock signal select multiplexer M3 is connected to an output of the OR gate 250. The OR gate 250 receives a scan mode control signal, an MBIST mode control signal, and a debug mode control signal applied on the control line 234 from the control logic block 230. The OR gate 250 generates a control signal that is applied to the select control port of the clock signal select multiplexer M3 to selectively output a clock signal (OCC clock signal) on a clock signal line 264. The OCC clock signal is applied to the CLK port of each scan cell 204 via a clock signal line 264. The OCC clock signal at the output of the clock signal select multiplexer M3 will vary depending on the selected mode of operation, test mode or functional mode. In functional mode, the functional mode clock is output from the clock signal select multiplexer M3 as the OCC clock signal that is applied to the CLK port of each scan cell 204 via a clock signal line 264. In test mode, either the ATE slow clock (for scan testing) or the gated fast clock (for at speed testing) or gated JTAG clock TCK (for debug mode) will be output as the OCC clock signal that is applied to the CLK port of each scan cell 204 via a clock signal line 264. The functional debug mode, which is separate from the SCAN mode or MBIST mode, is initiated using a separate control signal that is applied on control line 234 from the control logic block 230 to select the gate JTAG clock TCK to drive to logic.
Moreover, in the scan control circuitry of
In functional debug mode, the standard SCAN mode will be off. However, to provide control of the SE ports of the scan cells 204 in a debug mode, when a trigger is asserted, the control logic block 230 generates a control signal on line 232 to operate the scan circuitry in a scan mode of operation by controlling the SE ports of the scan cells 204. A single SE signal is used to control all of the scan chains 204, or only a subset of the scan chains, with the remaining scan chains being controlled using one or more other SE signals. The SE signal in an embodiment controls configuration of scan cells of a scan chain to form a serial shift register for shifting in and shifting out of test patterns. The SE signal may therefore be considered a type of scan shift enable signal, or more generally, a type of scan shift control signal. Other types of scan shift control signals may be used in other embodiments.
In a scan mode, the clock signal select multiplexers M1, M2 and M3 are selectively controlled (via respective select control signals output from the OR gate 240, control logic block 230 and OR gate 250) to output the gated fast clock signal or the ATE slow clock signal to the clock signal line 264 at the output of the multiplexer M3. In a functional mode of operation, the clock signal select multiplexer M3 is selectively controlled via a select control signal output from the OR gate 250 to output the functional mode clock signal to the clock signal line 264 at the output of the multiplexer M3. Thus, in the exemplary framework of
Furthermore, in the exemplary framework of
Thereafter, by switching the logic to a scan shift mode, the current latched values of the registers 224 are driven out on the chip port through the JTAG interface 222. In particular, since the scan chains 202 are multiplexed for JTAG output, the status of the registers (from a failing scan chain) can be shifted out to the JTAG user defined registers 224. Once the data is stored in the JTAG user defined registers 224, the data can be read suing the JTAG interface 222. As the location of the scan cells 204 in the given scan chain 202 are known from the DFT tool, the output data can be mapped to internal registers which will give designer the condition at which the failure occurred.
During the debug mode, the scan cells 204 continuously capture functional signal values from respective circuit blocks 205, 206, 207. At a particular point in time, a debug mode signal, which is normally at a logic “1” level, transitions to a logic “0” level, the scan chain 202 is placed into its scan shift mode in order to shift out the latest captured signal values for observation. The scan cells 204 can be configured such that when the switch is made from the functional (debug) mode to the scan shift mode, the current contents of the scan cells 204 are preserved. This can be accomplished, for example, by configuring the scan cells to comprise respective non-resettable flip-flops and turning off their clocks in conjunction with the switch from functional mode to scan shift mode. The clock signal input to the CLK port of the scan cells 204 are then turned back on once the scan cells 204 are in scan shift mode in order to allow the captured contents to be shifted out for observation.
When the debug mode is initiated (affirmative determination in step 302), the control logic block 230 will wait for a triggering event (step 304). As noted above, a triggering event may be an error condition or an interrupt condition that is input to the control logic block 230. When a triggering event is received (affirmative result in step 304), the control logic block 230 will generate the appropriate control signals to selectively apply a debug clock signal to drive the scan circuitry (step 306). In one embodiment as shown in
Next, the operating mode is changed to a scan shift mode and the Scan Enable signal is asserted (step 310). In the embodiment of
After the mode is changed to scan shift mode, one of the scan chains 202 is selected whose captured values are to be scanned out and stored in the JTAG user defined registers 234 (step 312). In the embodiment of
Once a target scan chain is selected, the clock gating applied to the JTAG clock TCK signal (via clock gating block 270) is turned off so that the debug clock signal is applied to the CLK ports of the scan cells 204 to cause the captured contents to be shifted out from the scan cells 204 (of the selected scan chain 202) into the JTAG user defined registers 224 (step 314). In this step, a control signal is asserted on control line 238, which is a clock gating control signal for the JTAG clock TCK. This signal is asserted by default so that JTAG clock will be gated, once all the can cells 204 are in Scan mode, depending on a user programmable control register or length of the scan chain or number of the scan cells for which the status must be checked by passing the values to the registers. Once the required number of clock pulses reach the registers, the clock gating will be enabled again. Thereafter, the stored data values in the JTAG user defined registers 224 can be accessed for observation through the JTAG interface 222 via operation of the JTAG TAP controller 220 (step 316).
In the embodiments described herein, a debug process implements control logic that operates on a system clock so that there is less delay for latching status values in the registers. Therefore, with this process, more accurate debug data can be received. Moreover, since most of the scan cells 204 are included in the scan chains 202, a significantly large number of observable internal signals can be accessed. Furthermore, debug control schemes according to embodiments described herein do not require the use of large multiplexer logic circuits to access the internal register data, which would add to more area overhead and routing congestion to the integrated circuit.
The network interface 420 is coupled to the processor system 410 to provide an interface that allows the processor system 410 to communicate with other systems and devices over one or more networks. The network interface 420 may comprise one or more transceivers. The I/O interface(s) 430 is/are coupled to the processor system 410 to provide an interface that allows the processor system 410 to communicate with one or more external devices such as a keyboard, a pointing device, a display, etc. The processor system 410 is coupled to the memory 440 to execute program instructions (e.g., IC design software 442) and access associated data (e.g., component designs 444 and 446) for designing an integrated circuit.
For instance, the IC design software 442 includes one or more software programs for implementing an RTL design phase to convert a user specification of integrated circuit function into an RTL description, and to implement various phases of a physical design including, but not limited to, logic synthesis, placement, signal distribution network synthesis, routing and timing analysis, using known techniques, to generate circuit components 444 and 446 that are stored in memory 440. The processor 410 implements a scan module 412 for supplementing the core circuit designs 444 with scan test and control circuitry 446 configured for testing the core circuit designs 444 in conjunction with utilizing of the design software 442. The memory 440 is an example of what is more generally referred to herein as a computer readable storage medium or other type of computer program product having computer program code tangibly embodied thereon. The memory 440 may comprise, for example, electronic memory such as random access memory (RAM) or read only memory (ROM), magnetic memory, optical memory, or other types of storage devices in any combination. The processor system 410 may comprise a microprocessor, CPU, ASIC, FPGA, or other type of processing device, as well as portions or combinations of such devices.
Furthermore, as indicated above, embodiments of the invention are implemented in the form of integrated circuits such as shown in
Although embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to the described embodiments, and that various changes and modifications may be made by one skilled in the art resulting in other embodiments of the invention within the scope of the following claims.
