Patent Application
20220045054
The disclosure relates to the field of display technology. More specifically, it relates to a CMOS structure and a method for manufacturing a CMOS structure.
With the combination and upgrade of display technology and sensing technology, new devices have increasingly higher requirements for TFTs (Thin Film Transistors). TFTs are required to not only have the function of simple switching, but also have logic calculation and processing functions. This requires the TFT to form a CMOS (Complementary Metal Oxide Semiconductor) structure. However, currently, LTPS (Low Temperature Poly-silicon) can be used to manufacture the CMOS structure with TFT, but the process is complicated and the cost is high.
Embodiments of the present disclosure provide a CMOS structure and a method for manufacturing a CMOS structure.
Embodiments of the present disclosure provide a CMOS structure. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer. The first active layer includes a first semiconductor layer, a N-type second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. Wherein, an N-type doping concentration of the second semiconductor layer is smaller than an N-type doping concentration of the third semiconductor layer. The P-type TFT includes a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer, wherein the second active layer includes a fourth semiconductor layer, and a fifth semiconductor layer of the P-type and a sixth semiconductor layer of the P-type which are at the opposite ends of the fourth semiconductor layer and sequentially stacked in a direction away from the second gate dielectric layer. Wherein, a P-type doping concentration of the fifth semiconductor layer is smaller than a P-type doping concentration of the sixth semiconductor layer.
In some embodiments, at least a portion of the first semiconductor layer serving as a channel region and a portion of the fourth semiconductor layer serving as a channel region include a polycrystalline semiconductor material.
In some embodiments, the source/drain regions of the first semiconductor layer and the source/drain regions of the fourth semiconductor layer include an amorphous semiconductor material.
In some embodiments, the second semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer include the polycrystalline semiconductor material.
In some embodiments, the polycrystalline semiconductor material includes polysilicon, and the amorphous semiconductor material includes amorphous silicon.
In some embodiments, the N-type TFT further includes a first etch stop layer on a side, away from the first gate dielectric layer, of a portion of the first semiconductor layer serving as a channel region portion. An end portion of the first etch stop layer is located between the first semiconductor layer and the second semiconductor layer. The P-type TFT further includes a second etch stop layer on a side, away from the second gate dielectric layer, of a portion of the fourth semiconductor layer serving as a channel region. An end of the second etch stop layer is located between the fourth semiconductor layer and the fifth semiconductor layer.
In some embodiments, the first gate electrode, the first gate dielectric layer, and the first semiconductor layer are sequentially stacked in a direction away from the substrate, and wherein the second gate electrode, the second gate dielectric layer and the second semiconductor layer are sequentially stacked in a direction away from the substrate.
In some embodiments, the first active layer has a first source/drain region adjacent to the P-type TFT and a second source/drain region away from the P-type TFT, the second active layer has a third source/drain region adjacent to the N-type TFT and a fourth source/drain region away from the P-type TFT. The CMOS structure further includes a first source/drain electrode disposed on the first source/drain region, the second source/drain electrode disposed on the second source/drain region, a third source/drain electrode disposed on the third source/drain region, a fourth source/drain electrode disposed on the fourth source/drain region, wherein the first source/drain electrode is connected to the third source/drain electrode.
Embodiments of the present disclosure further provide a method for manufacturing a CMOS structure.
The method for manufacturing a CMOS structure includes forming an N-type TFT and a P-type TFT on a substrate. Wherein, forming the N-type TFT includes forming a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer. The first active layer includes a first semiconductor layer, an N-type second semiconductor layer and an N-type third semiconductor layer which are at the opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. Wherein, an N-type doping concentration of the second semiconductor layer is smaller than an N-type doping concentration of the third semiconductor layer. Forming the P-type TFT includes forming a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer, wherein the second active layer includes a fourth semiconductor layer, a fifth semiconductor layer of the P-type and a sixth semiconductor layer of the P-type which are at the opposite ends of the fourth semiconductor layer and sequentially stacked in a direction away from the second gate dielectric layer. Wherein, a P-type doping concentration of the fifth semiconductor layer is smaller than a P-type doping concentration of the sixth semiconductor layer.
In some embodiments, at least a channel region of the first semiconductor layer and a channel region of the fourth semiconductor layer include a polycrystalline semiconductor material, a source/drain region of the first semiconductor layer, and a source/drain region of the fourth semiconductor layer include an amorphous semiconductor material.
In some embodiments, forming the first gate dielectric layer and the second gate dielectric layer includes forming a gate dielectric material layer on the first gate electrode and the second gate electrode, wherein a portion of the gate material dielectric layer on the first gate electrode constitutes the first gate dielectric layer, and wherein a portion of the gate material dielectric layer on the second gate electrode constitutes the second gate dielectric layer.
In some embodiments, forming the first semiconductor layer and the second semiconductor layer includes forming a first amorphous semiconductor material on the gate dielectric material layer, converting portions of the first amorphous semiconductor material layer on the first gate electrode and the second gate electrode into a polycrystalline semiconductor material to form a channel region of the first active layer and a channel region of the second active layer.
In some embodiments, the converting includes performing a laser annealing on the amorphous semiconductor material.
In some embodiments, performing the laser annealing includes using a microlens array mask.
In some embodiments, the method for manufacturing a CMOS structure further includes forming a first etch stop layer on a portion of the first semiconductor layer serving as a channel region, and forming a second etch stop layer on a portion of the fourth semiconductor layer serving as a channel region.
In some embodiments, forming the second semiconductor layer and the third semiconductor layer includes forming a second amorphous semiconductor material layer on the first semiconductor layer, forming a third amorphous semiconductor material layer on the second amorphous semiconductor material layer, and etching the second amorphous semiconductor material layer and the third amorphous semiconductor material layer located on the first etch stop layer to form a first gap extending to the first etch stop layer.
In some embodiments, forming the fifth semiconductor layer and the sixth semiconductor layer includes forming a fifth amorphous semiconductor material layer on the fourth semiconductor layer, forming a sixth amorphous semiconductor material layer on the fifth amorphous semiconductor material layer, and etching the fifth amorphous semiconductor material layer and the sixth amorphous semiconductor material layer located on the second etch stop layer to form a second gap extending to the second etch stop layer.
In some embodiments, forming the second amorphous semiconductor material layer, the third amorphous semiconductor material layer, the fifth amorphous semiconductor material layer, and the sixth amorphous semiconductor material layer includes using CVD.
In some embodiments, the first active layer has a first source/drain region adjacent to the P-type TFT and a second source/drain region away from the P-type TFT, and the second active layer has a third source/drain region adjacent to the N-type TFT and a fourth source/drain region away from the N-type TFT, the method further includes forming a conductive layer on the third semiconductor layer, the sixth semiconductor layer, the first gate dielectric layer, and the second gate dielectric layer, etching the conductive layer to form a first portion, a second portion, and a third portion spaced from one another, wherein the first portion covers the first source/drain region and the third source/drain region, the second portion covers the second source/drain region, and wherein the third portion covers the fourth source/drain region.
In some embodiments, the polycrystalline semiconductor material includes polysilicon, and the amorphous semiconductor material includes amorphous silicon.
To describe the technical solutions in embodiments of the present disclosure more clearly, the accompanying drawings of embodiments are briefly described below. It should be understood that the drawings described below refer only to some embodiments of the present disclosure, and not to restrict the present disclosure, wherein:
In order to make the technical solutions and advantages of embodiments of the present disclosure more comprehensible, the technical solutions of embodiments of the present disclosure are clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part but not all of embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall also fall within the protection scope of the present disclosure.
As used herein and in the appended claims, the singular form of a word includes the plural, and vice versa, unless the context clearly dictates otherwise. Thus, the references “a”, “an”, and “the” are generally inclusive of the plurals of the respective terms. Similarly, the words “comprise”, “comprises”, and “comprising” are to be interpreted inclusively rather than exclusively.
For purposes of the description, hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosure, as it is oriented in the drawing figures. The terms “overlying”, “atop”, “positioned on” or “positioned atop” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. The term “contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected with or without any intermediary elements at the interface of the two elements.
The P-type TFT includes a second gate electrode 21, a second active layer 22, and a second gate dielectric layer 23 located between the second gate electrode 21 and the second active layer 22. The second active layer 22 includes a fourth semiconductor layer 221, and a fifth semiconductor layer 222 of the P-type, and a sixth semiconductor layer 223 of the P-type which are at the opposite ends (E3, E4) of the fourth semiconductor layer 221 and sequentially stacked in a direction away from the second gate dielectric layer 23. The P-type doping concentration of the fifth semiconductor layer 222 is less than the P-type doping concentration of the sixth semiconductor layer 223.
As shown in
In some embodiments, at least a portion P11 of the first semiconductor layer 121 as a channel region and a portion P21 of the fourth semiconductor layer 221 as a channel region may include a polycrystalline semiconductor material. In some embodiments, the source/drain regions P12 of the first semiconductor layer 121 and the source/drain regions P22 of the fourth semiconductor layer 221 may include an amorphous semiconductor material. In some embodiments, the second semiconductor layer 122, the third semiconductor layer 123, the fifth semiconductor layer 222, and the sixth semiconductor layer 223 may include a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material may include polysilicon, and the amorphous semiconductor material may include amorphous silicon.
According to some embodiments of the present disclosure, the thin film transistor may have a bottom gate structure, as shown in
The second semiconductor layer 122 may be an N-type lightly doped semiconductor layer. For example, the N-type doping concentration of the second semiconductor layer 122 may be between 1017 ions/cm3 and 1019 ions/cm3. The third semiconductor layer 123 may be an N-type heavily doped semiconductor layer. For example, the N-type doping concentration of the third semiconductor layer 123 may be between 1019 ions/cm3 and 1021 ions/cm3.
The fifth semiconductor layer 222 may be a P-type lightly doped semiconductor layer. For example, the doping concentration of the fifth semiconductor layer 222 may be between 1017 ions/cm3 and 1019 ions/cm3. The sixth semiconductor layer 223 may be a P-type heavily doped semiconductor layer. For example, the P-type doping concentration of the sixth semiconductor layer 223 may be between 1019 ions/cm3 and 1021 ions/cm3.
The N-type TFT (TFT1) and the P-type TFT (TFT2) are connected through the first source/drain electrode 51 and the third source/drain electrode 53 to avoid the undesired potential barrier brought by the direct contact between the third semiconductor layer 123 and the sixth semiconductor layer 223 to achieve the connection, conducive to improving the performance of the CMOS structure.
Some embodiments of the present disclosure also provide a method for manufacturing a CMOS structure. A method for manufacturing a CMOS structure according to some embodiments of the present disclosure includes forming an N-type TFT and a P-type TFT on a substrate.
In some embodiments of the present disclosure, forming the N-type TFT includes forming a first gate electrode 11, a first active layer 12, and a first gate dielectric layer 13 between the first gate electrode 11 and the first active layer 12. The first active layer 12 includes a first semiconductor layer 121, a second semiconductor layer 122 of the N-type, and a third semiconductor layer 123 of the N-type which are at the opposite ends (E1, E2) of the first semiconductor layer 121 and sequentially stacked in a direction away from the first gate dielectric layer 13. The N-type doping concentration of the second semiconductor layer 122 is smaller than the N-type doping concentration of the third semiconductor layer 123.
In some embodiments of the present disclosure, forming a P-type TFT includes forming a second gate electrode 21, a second active layer 22, and a second gate dielectric layer 23 between the second gate electrode 21 and the second active layer 22. Wherein, the second active layer 22 includes a fourth semiconductor layer 221, a fifth semiconductor layer 222 of the P-type, and a sixth semiconductor layer 223 of the P-type which are at the opposite ends (E3, E4) of the fourth semiconductor layer 221 and sequentially stacked in a direction away from the second gate dielectric layer 23. The P-type doping concentration of the fifth semiconductor layer 222 is smaller than the P-type doping concentration of the sixth semiconductor layer 223.
In an embodiment of the present disclosure, the channel region P11 of the first semiconductor layer and the channel region P12 of the fourth semiconductor layer may include a polycrystalline semiconductor material, and a source/drain region P12 of the first semiconductor layer, and a source/drain region P22 of the fourth semiconductor layer may include an amorphous semiconductor material. The polycrystalline semiconductor material may include polysilicon, and the amorphous semiconductor material may include amorphous silicon.
In some embodiments of the present disclosure, forming the first semiconductor layer and the second semiconductor layer includes forming a first amorphous semiconductor material layer 02 on the gate dielectric material layer 03, converting portions of the first amorphous semiconductor material layer 02 on the first gate electrode 11 and the second gate electrode 21 into a polycrystalline semiconductor material to form a channel region P11 of the first active layer 12 and a channel region P21 of the second active layer 22.
The thickness of the first amorphous semiconductor material layer 02 may be 500 angstroms. Laser annealing can be used to convert the amorphous semiconductor material into a polycrystalline semiconductor material (i.e., perform a polycrystallization process). For example, a Micro Lens Array (MLA) mask can be used for laser annealing. MLA annealing has the advantage of high position accuracy.
In some embodiments of the present disclosure, the method for manufacturing a CMOS structure may further include forming a first etch stop layer 14 on a portion P11 of the first semiconductor layer that serves as a channel region, and forming a second etch stop layer 24 on a portion of the fourth semiconductor layer that serves as a channel region P21.
In some embodiments, an etch stop material layer may be deposited on the first amorphous semiconductor material layer 02 that has undergone the polycrystallization process. Then, the etch stop material layer is etched to form a first etch stop layer 14 and a second etch stop layer 24.
S51. Forming a second amorphous semiconductor material layer 04 on the first semiconductor layer 121. For example, a lightly doped N-type amorphous silicon with a thickness of 500 angstroms can be deposited on the first semiconductor layer. The N-type semiconductor layer may be doped with a pentavalent impurity element of phosphorus.
S52. Forming a third amorphous semiconductor material layer 05 on the second amorphous semiconductor material layer 122. For example, a heavily doped N-type amorphous silicon semiconductor layer with a thickness of 500 angstroms may be deposited on the second amorphous semiconductor material layer.
S53. Etching the second amorphous semiconductor material layer 04 and the third amorphous semiconductor material layer 05 located on the first etch stop layer 14 to form a first gap G1 extending to the first etch stop layer 14.
S61. Forming a fifth amorphous semiconductor material layer 06 on the fourth semiconductor layer 221. For example, a lightly doped P-type amorphous silicon with a thickness of 500 angstroms may be deposited on the fourth semiconductor layer. The P-type semiconductor layer may be doped with a trivalent impurity element such as boron.
S62. Forming a sixth amorphous semiconductor material layer 07 on the fifth amorphous semiconductor material layer 06. For example, a heavily doped P-type amorphous silicon with a thickness of 500 angstroms may be deposited on the fifth amorphous semiconductor material layer 06.
S63. Etching the fifth amorphous semiconductor material layer 06 and the sixth amorphous semiconductor material layer 07 located on the second etch stop layer 24 to form a second gap G2 extending to the second etch stop layer 24.
In some embodiments of the present disclosure, forming the second amorphous semiconductor material layer, the third amorphous semiconductor material layer, the fifth amorphous semiconductor material layer, and the sixth amorphous semiconductor material layer includes using chemical vapor deposition (CVD).
S71. Forming a conductive layer 08 on the third semiconductor layer 123, the sixth semiconductor layer 223, the first gate dielectric layer 13, and the second gate dielectric layer 23.
S73. Etching the conductive layer to form a first portion 08a (51, 53), a second portion 08b (52), and a third portion 08c (54) spaced from one another. As shown in
The specific embodiments have been described, and are not intended to limit the scope of the disclosure. In fact, the novel embodiments described herein can be implemented in a variety of other forms. In addition, various omissions, substitutions, and changes in the form of embodiments described herein may be made without departing from the spirit of the disclosure. The following claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the disclosure.
This patent application is a National Stage Entry of PCT/CN2019/076871 filed on Mar. 4, 2019, the disclosure of which is incorporated by reference herein in its entirety as part of the present application.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2019/076871 | 3/4/2019 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 20210151435 A1 | May 2021 | US |
