Combinatorial RF Biasing for Selectable Spot-Site Isolation

BACKGROUND

Combinatorial processing enables rapid evaluation of semiconductor processes. The systems supporting the combinatorial processing are flexible to accommodate the demands for running the different processes either in parallel, serial or some combination of the two.

Spot combinatorial processing while performing Radio Frequency (“RF”) biasing and ionized sputtering can be problematic. For example, conventionally applying RF bias to a substrate support such as a chuck that supports a substrate to drive the sputtered material applies the RF field to the entire substrate. While this may be desirable for full wafer processing, it is not well suited for site isolated combinatorial spot deposition and the flexible nature of combinatorial processing to vary materials, unit processes, and process parameters.

It is within this context that the embodiments arise.

SUMMARY

According to various embodiments of the invention, an apparatus for combinatorial Radio Frequency (RF) biasing for selectable site isolation on a substrate includes at least one motor and a movable arm operatively driven by the motor. An RF biasing element may be mounted on the movable arm. The motor is capable of driving the arm such that the RF biasing element can be positioned at any one of a plurality of sites beneath the substrate, where the RF biasing element can generate an RF hot spot.

According to various embodiments of the invention, an apparatus for combinatorial RF biasing for selectable site isolation on a substrate may include at least one RF biasing element configured to generate an RF hot spot at a particular site on the substrate. A controller is coupled to the RF biasing element and is configured to receive an indication of a selected site on the substrate at which to generate the RF hot spot. The controller may determine a position that corresponds to the selected site and generate a control signal based on the determined position. The control signal causes the RF biasing element to generate the RF hot spot at the selected site.

Various other objects, features, and advantages of the invention will be apparent through the detailed description of the preferred embodiments and the drawings attached hereto. It is also to be understood that both the foregoing general description and the following detailed description are exemplary and not restrictive of the scope of the invention.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.

FIG. 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration.

FIG. 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HPC) system in accordance with some embodiments of the invention

FIG. 5A is a schematic side elevational view of a substrate support illustrating a plane A-A for illustrative purposes, in accordance with some embodiments of the invention.

FIG. 5B is a schematic top view of a substrate support illustrating a plane B-B for illustrative purposes, in accordance with some embodiments of the invention.

FIGS. 6A and 6B are schematic diagrams illustrating cross-sectional views along plane A-A (FIG. 6A) and plane B-B (FIG. 6B) of a substrate support having a movable arm coupled to an RF biasing element, in accordance with some embodiments of the invention.

FIGS. 7A and 7B are a schematic diagrams illustrating cross-sectional views along plane A-A (FIG. 7A) and plane B-B (FIG. 7B) of a substrate support having a movable arm coupled to an RF biasing element, in accordance with some embodiments of the invention.

FIGS. 8A and 8B are schematic diagrams illustrating a cross-sectional view along plane A-A (FIG. 8A) and plane B-B (FIG. 8B) of a substrate support having an array of RF biasing elements, in accordance with some embodiments of the invention.

DETAILED DESCRIPTION

The embodiments described herein provide a method and apparatus related to sputter deposition processing. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

The embodiments provide for radio frequency (RF) biasing a region of a substrate with a RF element or puck that is capable of being moved under the surface of the substrate. The movement is provided by a motor mechanism that can cover the surface of the substrate. The motor moves the puck linearly and is capable of rotating around an axis in order to assist with the site isolated combinatorial deposition. In some embodiments, the RF puck is similar in size to a region of the substrate being processed. In an alternate embodiment, a grid array of fixed RF “hot spots” is provided so that multiple RF “hot spots” are distributed under the substrate. The grid array is capable of independently controlling whether certain hot spots are turned on or off. It should be appreciated that the embodiments can be integrated into a high ionization process in order to prevent re-deposition from occurring.

Semiconductor manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, patterning, etching, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as efficiency, power production, and reliability.

As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.

Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005 which are all herein incorporated by reference.

HPC processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD).

FIG. 1 illustrates a schematic diagram, 100, for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening. The schematic diagram, 100, illustrates that the relative number of combinatorial processes run with a group of substrates decreases as certain materials and/or processes are selected. Generally, combinatorial processing includes performing a large number of processes during a primary screen, selecting promising candidates from those processes, performing the selected processing during a secondary screen, selecting promising candidates from the secondary screen for a tertiary screen, and so on. In addition, feedback from later stages to earlier stages can be used to refine the success criteria and provide better screening results.

For example, thousands of materials are evaluated during a materials discovery stage, 102. Materials discovery stage, 102, is also known as a primary screening stage performed using primary screening techniques. Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage, 104. Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes).

The materials and process development stage, 104, may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage, 106, where tens of materials and/or processes and combinations are evaluated. The tertiary screen or process integration stage, 106, may focus on integrating the selected processes and materials with other processes and materials.

The most promising materials and processes from the tertiary screen are advanced to device qualification, 108. In device qualification, the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing, 110.

The schematic diagram, 100, is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes. The descriptions of primary, secondary, etc. screening and the various stages, 102-110, are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways.

This application benefits from High Productivity Combinatorial (HPC) techniques described in U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007 which is hereby incorporated for reference in its entirety. Portions of the '137 application have been reproduced below to enhance the understanding of the present invention. The embodiments described herein enable the application of combinatorial techniques to process sequence integration in order to arrive at a globally optimal sequence of semiconductor manufacturing operations by considering interaction effects between the unit manufacturing operations, the process conditions used to effect such unit manufacturing operations, hardware details used during the processing, as well as materials characteristics of components utilized within the unit manufacturing operations. Rather than only considering a series of local optimums, i.e., where the best conditions and materials for each manufacturing unit operation is considered in isolation, the embodiments described below consider interactions effects introduced due to the multitude of processing operations that are performed and the order in which such multitude of processing operations are performed when fabricating a device. A global optimum sequence order is therefore derived and as part of this derivation, the unit processes, unit process parameters and materials used in the unit process operations of the optimum sequence order are also considered.

The embodiments described further analyze a portion or sub-set of the overall process sequence used to manufacture a semiconductor device. Once the subset of the process sequence is identified for analysis, combinatorial process sequence integration testing is performed to optimize the materials, unit processes, hardware details, and process sequence used to build that portion of the device or structure. During the processing of some embodiments described herein, structures are formed on the processed substrate that are equivalent to the structures formed during actual production of the semiconductor device. For example, such structures may include, but would not be limited to, contact layers, buffer layers, absorber layers, or any other series of layers or unit processes that create an intermediate structure found on semiconductor devices. While the combinatorial processing varies certain materials, unit processes, hardware details, or process sequences, the composition or thickness of the layers or structures or the action of the unit process, such as cleaning, surface preparation, deposition, surface treatment, etc. is substantially uniform through each discrete region. Furthermore, while different materials or unit processes may be used for corresponding layers or steps in the formation of a structure in different regions of the substrate during the combinatorial processing, the application of each layer or use of a given unit process is substantially consistent or uniform throughout the different regions in which it is intentionally applied. Thus, the processing is uniform within a region (inter-region uniformity) and between regions (intra-region uniformity), as desired. It should be noted that the process can be varied between regions, for example, where a thickness of a layer is varied or a material may be varied between the regions, etc., as desired by the design of the experiment.

The result is a series of regions on the substrate that contain structures or unit process sequences that have been uniformly applied within that region and, as applicable, across different regions. This process uniformity allows comparison of the properties within and across the different regions such that the variations in test results are due to the varied parameter (e.g., materials, unit processes, unit process parameters, hardware details, or process sequences) and not the lack of process uniformity. In the embodiments described herein, the positions of the discrete regions on the substrate can be defined as needed, but are preferably systematized for ease of tooling and design of experimentation. In addition, the number, variants and location of structures within each region are designed to enable valid statistical analysis of the test results within each region and across regions to be performed.

FIG. 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing in accordance with one embodiment of the invention. In one embodiment, the substrate is initially processed using conventional process N. In one exemplary embodiment, the substrate is then processed using site isolated process N+1. During site isolated processing, an HPC module may be used, such as the HPC module described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006. The substrate can then be processed using site isolated process N+2, and thereafter processed using conventional process N+3. Testing is performed and the results are evaluated. The testing can include physical, chemical, acoustic, magnetic, electrical, optical, etc. tests. From this evaluation, a particular process from the various site isolated processes (e.g. from steps N+1 and N+2) may be selected and fixed so that additional combinatorial process sequence integration may be performed using site isolated processing for either process N or N+3. For example, a next process sequence can include processing the substrate using site isolated process N, conventional processing for processes N+1, N+2, and N+3, with testing performed thereafter.

It should be appreciated that various other combinations of conventional and combinatorial processes can be included in the processing sequence with regard to FIG. 2. That is, the combinatorial process sequence integration can be applied to any desired segments and/or portions of an overall process flow. Characterization, including physical, chemical, acoustic, magnetic, electrical, optical, etc. testing, can be performed after each process operation, and/or series of process operations within the process flow as desired. The feedback provided by the testing is used to select certain materials, processes, process conditions, and process sequences and eliminate others. Furthermore, the above flows can be applied to entire monolithic substrates, or portions of monolithic substrates such as coupons.

Under combinatorial processing operations the processing conditions at different regions can be controlled independently. Consequently, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, deposition order of process materials, process sequence steps, hardware details, etc., can be varied from region to region on the substrate. Thus, for example, when exploring materials, a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters. Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, an order in which materials are deposited, hardware details of the gas distribution assembly, etc. It should be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used in semiconductor manufacturing may be varied.

As mentioned above, within a region, the process conditions are substantially uniform, in contrast to gradient processing techniques which rely on the inherent non-uniformity of the material deposition. That is, the embodiments, described herein locally perform the processing in a conventional manner, e.g., substantially consistent and substantially uniform, while globally over the substrate, the materials, processes, and process sequences may vary. Thus, the testing will find optimums without interference from process variation differences between processes that are meant to be the same. It should be appreciated that a region may be adjacent to another region in one embodiment or the regions may be isolated and, therefore, non-overlapping. When the regions are adjacent, there may be a slight overlap wherein the materials or precise process interactions are not known, however, a portion of the regions, normally at least 50% or more of the area, is uniform and all testing occurs within that region. Further, the potential overlap is only allowed with material of processes that will not adversely affect the result of the tests. Both types of regions are referred to herein as regions or discrete regions.

FIG. 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HPC) system in accordance with some embodiments of the invention. HPC system includes a frame 300 supporting a plurality of processing modules. It should be appreciated that frame 300 may be a unitary frame in accordance with some embodiments. In some embodiments, the environment within frame 300 is controlled. Load lock/factory interface 302 provides access into the plurality of modules of the HPC system. Robot 314 provides for the movement of substrates (and masks) between the modules and for the movement into and out of the load lock 302. Modules 304-312 may be any set of modules and preferably include one or more combinatorial modules. For example, module 304 may be an orientation/degassing module, module 306 may be a clean module, either plasma or non-plasma based, modules 308 and/or 310 may be combinatorial/conventional dual purpose modules. Module 312 may provide conventional clean or degas as necessary for the experiment design.

Any type of chamber or combination of chambers may be implemented and the description herein is merely illustrative of one possible combination and not meant to limit the potential chamber or processes that can be supported to combine combinatorial processing or combinatorial plus conventional processing of a substrate or wafer. In some embodiments, a centralized controller, i.e., computing device 316, may control the processes of the HPC system, including the power supplies and synchronization of the duty cycles described in more detail below. Further details of one possible HPC system are described in U.S. application Ser. Nos. 11/672,478 and 11/672,473. With HPC system, a plurality of methods may be employed to deposit material upon a substrate employing combinatorial processes.

FIG. 4 is a simplified schematic diagram illustrating a sputter chamber configured to perform combinatorial processing and full substrate processing in accordance with some embodiments of the invention. Processing chamber 400 includes a bottom chamber portion 402 disposed under top chamber portion 418. Within bottom portion 402, substrate support 404 is configured to hold a substrate 406 disposed thereon and can be any known substrate support, including but not limited to a vacuum chuck, electrostatic chuck or other known mechanisms. Substrate support 404 is capable of both rotating around its own central axis 408 (referred to as “rotation” axis), and rotating around an exterior axis 410 (referred to as “revolution” axis). Such dual rotary substrate support is central to combinatorial processing using site-isolated mechanisms. Other substrate supports, such as an XY table, can also be used for site-isolated deposition. In addition, substrate support 404 may move in a vertical direction. It should be appreciated that the rotation and movement in the vertical direction may be achieved through known drive mechanisms which include magnetic drives, linear drives, worm screws, lead screws, a differentially pumped rotary feed through drive, etc. Power source 426 provides a bias power to substrate support 404 and substrate 406, and produces a negative bias voltage on substrate 406. In some embodiments power source 426 provides a radio frequency (RF) power sufficient to take advantage of the high metal ionization to improve step coverage of vias and trenches of patterned wafers. In another embodiment, the RF power supplied by power source 426 is pulsed and synchronized with the pulsed power from power source 424. Further details of the power sources and their operation may be found in U.S. patent application Ser. No. 13/281,316 entitled “High Metal Ionization Sputter Gun” filed on Oct. 25, 2011 and is herein incorporated by reference.

Substrate 406 may be a conventional round 200 mm, 300 mm, or any other larger or smaller substrate/wafer size. In other embodiments, substrate 406 may be a square, rectangular, or other shaped substrate. One skilled in the art will appreciate that substrate 406 may be a blanket substrate, a coupon (e.g., partial wafer), or even a patterned substrate having predefined regions. In another embodiment, substrate 406 may have regions defined through the processing described herein. The term region is used herein to refer to a localized area on a substrate which is, was, or is intended to be used for processing or formation of a selected material. The region can include one region and/or a series of regular or periodic regions predefined on the substrate. The region may have any convenient shape, e.g., circular, rectangular, elliptical, wedge-shaped, etc. In the semiconductor field a region may be, for example, a test structure, single die, multiple dies, portion of a die, other defined portion of substrate, or an undefined area of a substrate, e.g., blanket substrate which is defined through the processing.

Top chamber portion 418 of chamber 400 in FIG. 4 includes process kit shield 412, which defines a confinement region over a radial portion of substrate 406. Process kit shield 412 is a sleeve having a base (optionally integrated with the shield) and an optional top within chamber 400 that may be used to confine a plasma generated therein. The generated plasma will dislodge atoms from a target and the sputtered atoms will deposit on an exposed surface of substrate 406 to combinatorial process regions of the substrate in some embodiments. In another embodiment, full wafer processing can be achieved by optimizing gun tilt angle and target-to-substrate spacing, and by using multiple process guns 416. Process kit shield 412 is capable of being moved in and out of chamber 400, i.e., the process kit shield is a replaceable insert. In another embodiment, process kit shield 412 remains in the chamber for both the full substrate and combinatorial processing. Process kit shield 412 includes an optional top portion, sidewalls and a base. In some embodiments, process kit shield 412 is configured in a cylindrical shape, however, the process kit shield may be any suitable shape and is not limited to a cylindrical shape.

The base of process kit shield 412 includes an aperture 414 through which a surface of substrate 406 is exposed for deposition or some other suitable semiconductor processing operations. Aperture shutter 420 which is moveably disposed over the base of process kit shield 412. Aperture shutter 420 may slide across a bottom surface of the base of process kit shield 412 in order to cover or expose aperture 414 in some embodiments. In another embodiment, aperture shutter 420 is controlled through an arm extension which moves the aperture shutter to expose or cover aperture 414. It should be noted that although a single aperture is illustrated, multiple apertures may be included. Each aperture may be associated with a dedicated aperture shutter or an aperture shutter can be configured to cover more than one aperture simultaneously or separately. Alternatively, aperture 414 may be a larger opening and plate 420 may extend with that opening to either completely cover the aperture or place one or more fixed apertures within that opening for processing the defined regions. The dual rotary substrate support 404 is central to the site-isolated mechanism, and allows any location of the substrate or wafer to be placed under the aperture 414. Hence, the site-isolated deposition is possible at any location on the wafer/substrate.

A gun shutter, 422 may be included. Gun shutter 422 functions to seal off a deposition gun when the deposition gun may not be used for the processing in some embodiments. For example, two process guns 416 are illustrated in FIG. 4. Process guns 416 are moveable in a vertical direction so that one or both of the guns may be lifted from the slots of the shield. While two process guns are illustrated, any number of process guns may be included, e.g., one, three, four or more process guns may be included. Where more than one process gun is included, the plurality of process guns may be referred to as a cluster of process guns. Gun shutter 422 can be transitioned to isolate the lifted process guns from the processing area defined within process kit shield 412. In this manner, the process guns are isolated from certain processes when desired. It should be appreciated that slide cover plate 422 may be integrated with the top of the process kit shield 412 to cover the opening as the process gun is lifted or individual cover plate 422 can be used for each target. In some embodiments, process guns 416 are oriented or angled so that a normal reference line extending from a planar surface of the target of the process gun is directed toward an outer periphery of the substrate in order to achieve good uniformity for full substrate deposition film. The target/gun tilt angle depends on the target size, target-to-substrate spacing, target material, process power/pressure, etc.

Top chamber portion 418 of chamber 400 of FIG. 4 includes sidewalls and a top plate which house process kit shield 412. Arm extensions 416a, which are fixed to process guns 416 may be attached to a suitable drive, e.g., lead screw, worm gear, etc., configured to vertically move process guns 416 toward or away from a top plate of top chamber portion 418. Arm extensions 416a may be pivotally affixed to process guns 416 to enable the process guns to tilt relative to a vertical axis. In some embodiments, process guns 416 tilt toward aperture 414 when performing combinatorial processing and tilt toward a periphery of the substrate being processed when performing full substrate processing. It should be appreciated that process guns 416 may tilt away from aperture 414 when performing combinatorial processing in another embodiment. In yet another embodiment, arm extensions 416a are attached to a bellows that allows for the vertical movement and tilting of process guns 416. Arm extensions 416a enable movement with four degrees of freedom in some embodiments. Where process kit shield 412 is utilized, the aperture openings are configured to accommodate the tilting of the process guns. The amount of tilting of the process guns may be dependent on the process being performed in some embodiments.

Power source 424 provides power for sputter guns 416 whereas power source 426 provides RF bias power to an electrostatic chuck to bias the substrate when necessary. It should be appreciated that power source 424 may output a direct current (DC) power supply or a radio frequency (RF) power supply.

Chamber 400 includes auxiliary magnet 428 disposed around an external periphery of the chamber. The auxiliary magnet 428 is located in a region defined between the bottom surface of sputter guns 416 and a top surface of substrate 406. Magnet 428 may be either a permanent magnet or an electromagnet. It should be appreciated that magnet 428 is utilized to provide more uniform bombardment of Argon ions and electrons to the substrate in some embodiments.

FIG. 5A is a schematic side elevational view of a substrate support 204 illustrating a plane A-A for illustrative purposes, in accordance with some embodiments of the invention. A substrate (not illustrated in FIG. 5A) may be placed adjacent to and at least partially supported by a surface 501 of substrate support 204. As illustrated, surface 501 is substantially parallel to the plane A-A.

FIG. 5B is a schematic top view of a substrate support 204 illustrating a plane B-B for illustrative purposes, in accordance with some embodiments of the invention. A substrate (not illustrated in FIG. 5B) may be placed adjacent to and at least partially supported by a surface 501 of substrate support 204. As illustrated, surface 501 is substantially perpendicular to the plane B-B.

FIGS. 6A and 6B are schematic diagrams illustrating cross-sectional views along plane A-A of FIG. 5A and plane B-B of FIG. 5B of a substrate support 204 having a movable arm 604 coupled to an RF biasing element 602, in accordance with some embodiments of the invention. In some embodiments of the invention, RF biasing element 602 is attached, directly or indirectly, to a distal end 615 of movable arm 604. In some embodiments of the invention, motors 606 and 607 may respectively telescope and sweep movable arm 604. As illustrated, in some embodiments, motors 606 and 607 may be disposed within a housing such as an elbow 609, although other housings may be used as would be appreciated. In some embodiments of the invention, motors 606 and 607 may each be attached, directly or indirectly, to a proximal end 617 of movable arm 604. In some embodiments of the invention, RF biasing element 602 is electrically coupled to and receives RF biasing power from an RF source 603, which may include, for example, power source 226 illustrated in FIG. 4. In some embodiments of the invention, RF source 603 may be controlled by controller 601, which may include or be controlled by, for example, computing device 116 illustrated in FIG. 3.

As illustrated in FIG. 6A, substrate support 204 includes different regions (illustrated for clarity as regions 204A-D). The number, shape and configuration of different regions 204A-D will vary according to particular needs. For example, in some embodiments of the invention, at least one region 204A-D may be substantially co-extensive with the shape, size, and/or configuration of RF biasing element 602. In some embodiments of the invention, at least one region 204A-D may have a different shape, size, and/or configuration than RF biasing element 602.

In some embodiments of the invention, movable arm 604 is coupled to a motor 606, which may be attached, directly or indirectly, to substrate support 204. In some embodiments of the invention, as illustrated in FIG. 6B, motor 606 rotates about an axis 610. For example, and without limitation, motor 606 may include an elbow motor, although other conventional motors that can cause rotation about an axis may be used as would be appreciated. In this manner, motor 606 may sweep movable arm 604 within a region 204A-D, or from one region 204A-D to another region 204A-D, in an angular direction about axis 610.

In some embodiments of the invention, movable arm 604 is coupled to a motor 607, which may be attached, directly or indirectly, to substrate support 204. Motor 607 moves movable arm 604 such that RF biasing element 602 is moved linearly toward or away from motor 607, as illustrated by double arrow R. In this manner, motor 607 may move movable arm 604 within a region 204A-D, or from one region 204A-D to another region 204A-D.

In some embodiments of the invention, movable arm 604 is a retractable arm. In these embodiments, motor 607 may include various conventional motors that can telescope (i.e., retract and extend) movable arm 604. In other embodiments of the invention, movable arm 604 is a rigid arm (i.e., non-telescoping) that, when moved toward motor 607, may at least partially protrude from substrate support 204.

In some embodiments of the invention, RF biasing element 602 may be attached, directly or indirectly, to a moving element 608, which helps support RF biasing element 602 against an inner surface 611 (FIG. 6B) of substrate support 204. Moving element 608 may include, without limitation, a ball bearing that rolls along inner surface 611 and/or be formed from materials, compositions, and/or coatings (such as, without limitation, Polytetrafluoroethylene) that can support and/or assist movement of RF biasing element 602 along inner surface 611.

In operation, controller 601 may determine a particular region 204A-D (e.g., region 204B illustrated in FIG. 6A) for which an RF bias is to be applied (i.e., an “RF hotspot” or “RF biasing”). In some embodiments, for example, controller 601 may receive an identification of region 204B at which an RF bias should be applied. In some embodiments, controller 601 may receive an indication that a discrete location or region of a substrate (such as substrate 206 illustrated in FIG. 4) is or will undergo combinatorial processing as described above. In these embodiments, based on the indication, controller 601 may determine a particular region 204A-D (e.g., region 204B illustrated in FIG. 6A) that corresponds to the discrete location. For example, the substrate may be substantially co-extensive with substrate support 204 so that the indicated position on the substrate substantially coincides with a position of regions 204A-D. In other examples, the substrate may be smaller or larger than substrate support 204 such that a mapping between positions of the substrate and regions 204A-D may be performed. Such mapping may be pre-stored in a memory or dynamically generated according to the size, shape, configuration, etc., of the substrate and/or substrate support 204.

Whichever embodiment is used to determine the region to which the RF bias should be applied, controller 601 causes movable arm 604, via motor 606 and/or motor 607, to move such that RF biasing element 602 is moved to region 204B. For example, each region 204A-D may be associated with a positional coordinate such that movable arm 604 may be moved to the relevant coordinate by actuating motor 606, motor 607 or both. In some embodiments, controller 601 may use conventional algorithms to move movable arm 604 and RF biasing element 602 to the positional coordinate. For example, controller 601 may use dead reckoning or other techniques for tracking and moving objects to various locations.

When RF biasing element 602 is positioned at region 204B, controller 601 may cause RF source 603 to provide RF biasing power. In response to the RF biasing power, RF biasing element 602 generates a spot-isolated RF bias to region 204B. In some embodiments of the invention, the RF bias is substantially co-extensive with the size, shape, and/or configuration of RF biasing element 602. In other embodiments, the RF bias (i.e., RF hotspot) has a different size, shape, and/or configuration than the size, shape, and/or configuration of the RF biasing element. In other words, RF biasing element 602 may be configured to generate an RF hotspot substantially the same size, shape, configuration, etc., as the size, shape, configuration, etc. of the element or may generate a smaller or larger RF hotspot.

FIGS. 7A and 7B are a schematic diagrams illustrating cross-sectional views along plane A-A of FIG. 5A and plane B-B of FIG. 5B) of a substrate support 204 having a movable arm 604 coupled to an RF biasing element 602, in accordance with some embodiments of the invention. In this embodiment, while motor 606 may sweep movable arm 604 in an angular direction (as described with respect to FIGS. 6A and 6B), the movable arm does not retract or otherwise move linearly. Instead, RF biasing element 602 is moved linearly along movable arm 604. For example, as illustrated in FIGS. 7A, and 7B, RF biasing element 602 is moved linearly in a direction (indicated by double arrow R in FIG. 7A) along a track 702 formed into or mounted onto movable arm 604.

As illustrated in FIG. 7B, for example, RF biasing element 602 may move along track 702 via a motor 706 that drives a wheel 707. Wheel 707 can be configured as a wheel, a gear, or other component that facilitates movement along track 702, which can be formed with a smooth surface or a surface having grooves that receive gear teeth. In these embodiments, for example, the position of RF biasing element 602 may be tracked at least in part by counting a number of partial or whole rotations of wheel 707 (as well as, for example, an angular rotation by motor 606).

Referring to FIGS. 7A and 7B, in operation, controller 601 operates in a manner similar to that described above with respect to FIGS. 6A and 6B. However, instead of controlling movement of moveable arm 604 in a linear fashion, controller 601 controls movement of RF biasing element 602 along moveable arm 604, a non-limiting example of which is illustrated in FIGS. 7A, and 7B.

The components illustrated in FIG. 7B are non-limiting examples for illustrative purposes. As would be appreciated, alternative components (not illustrated in the Figures) may be used to move RF biasing element 602 along movable arm 604. Such structures can include, without limitation, a pulley system used to push/pull RF biasing element 602, an actuator such as a solenoid used to push/pull RF biasing element 602, and/or other conventional techniques that can move the RF biasing element along the movable arm. Furthermore, although illustrated in FIGS. 6-7 as having a single movable arm 604, more than one movable arm may be used such that each movable arm covers respective regions of the substrate support.

FIGS. 8A and 8B are schematic diagrams illustrating a cross-sectional view along plane A-A of FIG. 5A) and plane B-B of FIG. 5B) of a substrate support 204 having an array 802 of RF biasing elements 602, in accordance with some embodiments of the invention. For clarity, only three RF biasing elements 602 (RF biasing element 602A, 602B, 602N) are labeled in FIGS. 8A and 8B, although the array can include more or less RF biasing elements. In some embodiments, at least one RF biasing element 602 may correspond to a region on substrate support 204. In turn, the region (and corresponding RF biasing element 602) of substrate support 204 may correspond to a discrete region on the substrate so that an RF biasing element 602 in array 802 may correspond to a discrete region of the substrate for combinatorial processing. In some embodiments, a size of the discrete region and a size of RF biasing element are substantially equivalent.

In some embodiments of the invention, RF biasing elements 602 may be electrically coupled to RF source 603, which provides an RF biasing source to one or more of the RF biasing elements 602. In some embodiments, RF source 603 can be controlled by controller 601 as described above with respect to FIGS. 6 and 7. In some embodiments of the invention, controller 601 selectively determines which ones of the RF biasing elements 602 should receive the RF biasing power. In some embodiments, a switching matrix 605 may be used to selectively route the RF biasing power to the appropriate RF biasing element(s) 602, although other techniques for selectively activating electrical components may be used as would be appreciated.

In some embodiments of the invention, array 802 may include a body 804 (FIG. 8B) on which RF biasing elements 602 are disposed. For example, body 804 may include a rigid or flexible sheet, membrane, mesh or other component that can support the RF biasing elements 602 attached thereto. In some embodiments, body 804 may be formed from wires (not illustrated) used to electrically couple RF biasing elements 602 to RF source 603 and/or switching matrix 605.

In some embodiments of the invention, at least two of the RF biasing elements 602 may be RF shielded from one another in order to further isolate RF biasing at a discrete region of the substrate supported by substrate support 204. For example, RF absorbent material (as would be appreciated) may be disposed between (not illustrated in the Figures) the at least two RF biasing elements 106 that are to be isolated from one another.

In operation, controller 601 may determine a particular RF biasing element 602 that should apply an RF bias. In some embodiments, for example, controller 601 may receive an identification of the particular RF biasing element 602. As would be appreciated, each RF biasing element 602 may be associated with an identifier or address that identifies a position of the RF biasing element. In other embodiments, controller 601 may determine the identity of the RF biasing element 602 that should apply the RF biasing. For example, controller 601 may receive an indication that a discrete location or region of a substrate (such as substrate 206 illustrated in FIG. 4) is or will undergo combinatorial processing as described above. In these embodiments, based on the indication, controller 601 may determine an RF biasing element 602 that corresponds to the discrete location. For example, the substrate may be substantially co-extensive with array 802 such that the indicated position on the substrate substantially coincides with a position on array 802. In other examples, the substrate may be smaller or larger than array 802 such that a mapping between positions of the substrate and array 802 may be performed. Such mapping may be pre-stored in a memory or dynamically generated according to the size, shape, configuration, etc., of the substrate and/or array 802.

Upon identification of the RF biasing element 602 that should apply the RF biasing, controller 601 may communicate a control signal to RF source 603 to transmit RF biasing power. The RF biasing power, along with identification of the RF biasing element 602 may be routed via switch matrix 605, which causes the RF biasing power to be transmitted to the identified RF biasing element 602.

In the drawings, like reference numerals appearing in different drawings represent similar or same components and perform similar or same functions, unless specifically noted otherwise in the description. Furthermore, as would be appreciated by those skilled in the art, according to common practice, the various features of the drawings discussed herein are not necessarily drawn to scale, and that dimensions of various features, structures, or characteristics of the drawings may be expanded or reduced to more clearly illustrate various implementations of the invention described herein.

Implementations of the invention may be described as including a particular feature, structure, or characteristic, but every aspect or implementation may not necessarily include the particular feature, structure, or characteristic. Further, when a particular feature, structure, or characteristic is described in connection with an aspect or implementation, it will be understood that such feature, structure, or characteristic may be included in connection with other implementations, whether or not explicitly described. Thus, various changes and modifications may be made to the provided description without departing from the scope or spirit of the invention. As such, the specification and drawings should be regarded as exemplary only, and the scope of the invention to be determined solely by the appended claims.

Combinatorial RF Biasing for Selectable Spot-Site Isolation

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