COMPLEMENTARY MIRROR IMAGE EMBEDDED PLANAR RESISTOR ARCHITECTURE

Abstract

A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows an architecture of a conventional embedded planar resistor and a ground plane.

FIG. 1B shows a simulating architecture of the conventional embedded planar resistor.

FIG. 1C is a frequency response simulating diagram for comparing the simulating architecture with the actually measured resistance according to the conventional embedded planar resistor and the ground plane.

FIG. 2 shows conventional printed circuit board architecture with an embedded planar resistor.

FIG. 3A is a schematic cross-sectional view of the ground architecture of the complementary mirror image embedded planar resistor according to a preferred embodiment of the present invention.

FIG. 3B is a perspective schematic side view of the ground architecture of the complementary mirror image embedded planar resistor according to a preferred embodiment of the present invention.

FIGS. 3C and 3D are a schematic cross-sectional view of the complementary mirror image embedded planar resistor according to other embodiments of the present invention.

FIG. 3E is a perspective schematic side view of the ground architecture of the complementary mirror image embedded planar resistor according to a preferred embodiment of the present invention.

FIG. 4A is a schematic cross-sectional view of the ground architecture of the complementary mirror image embedded planar resistor according to a preferred embodiment of the present invention.

FIG. 4B is a perspective schematic side view.

FIG. 5A is a resistance to frequency relation curve of the embedded planar resistor as for different ground planes.

FIG. 5B is a impedance (db value) to frequency relation curve of the embedded planar resistor as for different ground planes.

FIG. 6 is a schematic cross-sectional view of the complementary mirror image embedded planar resistor architecture according to a preferred embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a complementary mirror image embedded planar resistor architecture according to another preferred embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

The design of an embedded planar resistor usually presents different electrical characteristics due to the effects of the parasitic components generated between the embedded resistor and the conductive layer, such as a metal ground plane, an electrode layer, or a power supply layer. The higher the frequency is, the greater the influence of the parasitic effects is. On the other hands, when other signal transmission lines pass through, if there is no shield at all, serious interference or cross talk phenomenon occurs. In the present invention, the design of the structure between the embedded planar resistor and a ground plane or an electrode layer or a power supply layer is improved, so as to increase the application frequency, thus, the embedded planar resistor is more suitable for a high frequency application circuit.

In order to enhance the aforementioned characteristics, a novel structure must be designed to achieve the high frequency application. As for the design of a conventional embedded planar resistor, all electrodes are embedded in a circuit substrate and electrode contacts are usually connected to transmission lines or via holes. The common transmission line structures are, for example, a micro-strip line structures, so that the parasitic capacitance unavoidably occurs between the micro-strip line and a ground plane or an electrode layer below the micro-strip line.

The present invention provides a complementary mirror image embedded planar resistor architecture. A complementary hollow structure is formed in a ground plane or in an electrode layer adjacent to the embedded planar resistor, so as to reduce the parasitic capacitance and efficiently enhance the application frequency range, and the dielectric loss between the embedded planar resistor and a metal ground plane or an electrode layer or a power supply layer is also reduced.

In another alternative embodiment, the present invention provides a complementary mirror image embedded planar resistor architecture, in which a mesh structure is formed in a ground plane, an electrode layer, or a power supply layer adjacent to the embedded planar resistor. By such arrangement, the parasitic capacitance is reduced, the interference generated by a signal circuit in the lower layer is efficiently shielded, and the application frequency range is efficiently enhanced, and the dielectric loss between the embedded planar resistor and the metal ground plane, the electrode layer, or the power supply layer is reduced.

A embodiment of the present embodiment is illustrated below with reference to FIGS. 3A and 3B. FIG. 3A is a schematic cross-sectional view of a complementary mirror image embedded planar resistor architecture according to a preferred embodiment of the present invention, and FIG. 3B is a perspective schematic side view. The complementary mirror image embedded planar resistor architecture includes an embedded planar resistor 310 located between two electrodes 320 and 324, and an adjacent conductive layer, such as a ground plane, an electrode layer, or a power supply layer, and the ground plane is taken as an example herein. As shown in the figures, the ground plane 330 is located below the embedded planar resistor 310, and a dielectric layer 340 is located between the ground plane 330 and the embedded planar resistor 310. The electrodes 320 and 324 are respectively connected to transmission lines 322 and 326, which are, for example, micro-strip line structures.

As shown in the figures, the embedded planar resistor 310 has a portion with a length of X and a width of Y in the same layer between the electrodes 320 and 324, and a hollow structure 332 is correspondingly formed in the ground plane 330 by means of complementary mirror image. The size of the hollow structure 332 is substantially the same as that of the portion with a length of X and a width of Y in an embodiment, that is, the area of the hollow structure 332 is substantially equal to the area of the portion of the embedded planar resistor 310 in the same layer between the electrodes 320 and 324. However, in a practical application embodiment, the hollow structure 332 may be slightly larger than or smaller than the portion of the embedded planar resistor 310 in the same layer between the electrodes 320 and 324, which also falls within the scope of the present invention. In a preferred embodiment, the area of the hollow structure 332 is about 0.5-1.5 times of that of the portion of the embedded planar resistor 310. Additionally, the shape of the hollow structure 332 may be similar to or different from that of the portion of the embedded planar resistor 310. The complementary hollow structure formed in the ground plane 330 of the embedded planar resistor 310 reduces the parasitic capacitance 342, efficiently enhance the application frequency range, and reduce the dielectric loss between the embedded planar resistor and the metal ground plane.

In an alternative embodiment of the present invention, the size of the hollow structure 332 is also designed in consideration of the area of the two electrodes 320 and 324, i.e., the area of the hollow structure 332 may be designed to be substantially larger than, equal to, or smaller than the sum of the area of the portion of the embedded planar resistor 310 in the same layer between the two electrodes 320 and 324 and the areas of the two electrodes 320 and 324. In a practical application embodiment, the area of the hollow structure 332 is about 0.5-1.5 times of the sum of the area of the portion of the embedded planar resistor 310 and the areas of the electrodes 320 and 324.

In alternative embodiments of the present invention, as shown in FIGS. 3C and 3D, the complementary mirror image embedded planar resistor architecture includes an embedded planar resistor 310 located between two electrodes 320 and 324, and an adjacent conductive layer, such as a ground plane, an electrode layer, or a power supply layer, and the ground plane 330 is taken as an example herein. A dielectric structure is located between the ground plane 330 and the embedded planar resistor 310. The dielectric structure includes a plurality of stacked dielectric layers, for example, as shown in FIG. 3C, a dielectric layer 371 and a dielectric layer 372. In another embodiment, the dielectric structure includes a plurality of dielectric layers located beside to each other, for example, as shown in FIG. 3D, a dielectric layer 373 and a dielectric layer 374 located in parallel between the ground plane 330 and the embedded planar resistor 310.

Another embodiment of the present invention is illustrated with reference to FIG. 3E. As shown in FIG. 3E, the complementary mirror image embedded planar resistor architecture includes an embedded planar resistor 310, a first electrode 320, a second electrode 324, a ground plane or an electrode layer or a power supply layer 330, and a dielectric layer 340. The embedded planar resistor is located on a first plane. The first electrode and the second electrode are located on the first plane, and the first electrode is used to connect the embedded planar resistor to a first via hole 322, so as to further connect the embedded planar resistor to circuit elements on other planes. The second electrode is used to connect the embedded planar resistor to a second via hole 326, so as to further connect the embedded planar resistor to circuit elements on other planes. The ground plane, the electrode layer, or the power supply layer is disposed on a second plane. The dielectric layer is sandwiched between the first plane and the second plane. A hollow structure is formed in the ground plane or the electrode layer or the power supply layer at the mirror image location corresponding to the embedded planar resistor. The shape and size of the hollow structure can be adjusted according to design requirements.

In an embodiment of the complementary mirror image embedded planar resistor architecture, the first via hole and the second via hole are plated through hole (PTH) structures formed by a mechanical drilling machine.

In an embodiment of the complementary mirror image embedded planar resistor architecture, the first via hole and the second via hole are laser via structures formed by a laser ablation machine.

In an embodiment of the complementary mirror image embedded planar resistor architecture, the first electrode connected to the embedded planar resistor is grounded through the first via hole 322.

In an embodiment of the complementary mirror image embedded planar resistor architecture, the first electrode connected to the embedded planar resistor is grounded through the first via hole 322, and the second electrode is connected to other layers through the second via hole 326.

Another embodiment of the present invention is illustrated with reference to FIGS. 4A and 4B. FIG. 4A is a schematic cross-sectional view of the ground architecture of the complementary mirror image embedded planar resistor according to a preferred embodiment of the present invention, and FIG. 4B is a perspective schematic side view. The ground architecture of the complementary mirror image embedded planar resistor includes: an embedded planar resistor 410 located between two electrodes 420 and 424, a ground plane 430 located below the embedded planar resistor 410, as shown in the figures, and a dielectric layer 440 sandwiched between the embedded planar resistor 410 and the ground plane 430. Another transmission line 460 is disposed below the ground plane 430. The electrodes 420 and 424 are respectively connected to the transmission lines 422 and 426, which are, for example, micro-strip line structures. As shown in FIG. 4A, not only the parasitic capacitance (as indicated by the numeral 442 in the figure) is generated between the embedded planar resistor 410 and the ground plane 430, to affect at high frequency application range, but the embedded planar resistor 410 is also further interfered and affected (as indicated by the numeral 444 shown in the figure) by the transmission line 460 on another layer.

As shown in the figure, the embedded planar resistor 410 has a portion with a length of X and a width of Y on the same layer between the two electrodes 420 and 424, and a mesh structure 432 is formed correspondingly in the ground plane 430 by means of complementary mirror image. The size of the mesh structure 432 is substantially equal to that of the portion with a length of X and a width of Y, and the mesh structure is formed by a plurality of regularly-arranged holes. In another alternative embodiment, the mesh structure 432 may be formed by a plurality of holes, which is arranged in a predetermined order or at random, and the shape and size are not limited as long as there is a plurality of holes, which may be a plurality of strip-shaped holes, for example.

The size of the whole mesh structure 432 may be larger than, equal to, or smaller than that of the portion of the embedded planar resistor 410 on the same layer between the two electrodes 420 and 424, which also falls within the application scope of the present invention. In a preferred embodiment, the area of the mesh structure 432 is about 0.5-1.5 times of that of the portion of the embedded planar resistor 410. The ground plane 430 of the embedded planar resistor 410 is formed into a hollow mesh structure, so as to reduce the parasitic capacitance, efficiently shield the interference generated by a signal circuit in the lower layer, and efficiently enhance the application frequency range, and the dielectric loss between the embedded planar resistor and the metal ground plane is also reduced.

In an alternative embodiment of the present invention, the size of the mesh structure 432 is also designed in consideration of the areas of the two electrodes 420 and 424, that is, the area of the whole mesh structure 432 may be designed to be larger than, equal to, or smaller than the sum of the area of the portion of the embedded planar resistor 410 on the same layer between the two electrodes 420 and 424 and the areas of the two electrodes 420 and 424. In an embodiment of practical application, the area of the mesh structure 432 is about 0.5-1.5 times of the sum of the area of the portion of the embedded planar resistor 410 and the areas of the two electrodes 420 and 424.

Simulation analysis is performed according to the structures in the aforementioned embodiments. For example, the embedded planar resistor has an area of 30*30 mil², a thickness of about 1.8 mil, and a resistance of 1 M ohm per square unit. The dielectric layer between the embedded planar resistor and the ground plane is made of the newly developed dielectric material HiDK17 having a high dielectric constant, and its thickness is about 8 mil. Referring to FIG. 5A, it is mainly a resistance to frequency relation curve of the embedded planar resistor as for different ground planes. In a conventional architecture, the reduction of the resistance as the frequency is increased is shown by the curve 510. As for the ground architecture of the complementary mirror image embedded planar resistor provided by the present invention, the ground plane of the embedded planar resistor is formed into a complementary hollow structure, and the resistance-frequency response is shown by the curve 520. Additionally, as for the ground architecture of the complementary mirror image embedded planar resistor provided by the present invention, the ground plane of the embedded planar resistor is formed into a mesh structure, and the resistance-frequency response is shown by the curve 525. The ground architecture of the complementary mirror image embedded planar resistor provided by the present invention does achieve an improved effect when being used for the high frequency application, wherein it is more preferred to form the ground plane of the embedded planar resistor into be a complementary hollow structure. Furthermore, FIG. 5B is mainly a impedance (db value) to frequency relation curve of the embedded planar resistor as for different ground planes.

As for the ground architecture of the complementary mirror image embedded planar resistor provided by the present invention, after the corresponding part of the ground plane below the embedded planar resistor is completely hollowed, if the resistance is designed to be 400 ohm, the self-resonant frequency is enhanced by about 2 GHz (from 5 GHz to 1 GHz), or the resistance is enhanced by about 20 ohm (from 400 ohm to 420 ohm). However, if the corresponding part of the ground plane below the embedded planar resistor employs the mesh design, and the resistance is designed to be 400 ohm, the self-resonant frequency is enhanced by about 200 MHz, or the resistance is enhanced, but not so obvious.

Still another specific embodiment of the present invention is illustrated with reference to FIG. 6. FIG. 6 is a schematic cross-sectional view of the complementary mirror image embedded planar resistor architecture according to one preferred embodiment of the present invention. The complementary mirror image embedded planar resistor architecture includes an embedded planar resistor 610 located between two electrodes 620 and 624, and an adjacent embedded capacitor structure 630. The embedded capacitor structure 630 includes, for example, an upper electrode plate 632, a lower electrode plate 634, and a dielectric layer 635 sandwiched there-between. As shown in FIG. 6, the upper electrode plate 632 is located below the embedded planar resistor 610, and another dielectric layer 625 is sandwiched between the upper electrode plate 632 and the embedded planar resistor 610. The electrodes 620 and 624 are respectively connected to transmission lines 622 and 626, which are, for example, micro-strip line structures.

As shown in FIG. 6, the embedded planar resistor 610 has a portion with a length of X and a width of Y on the same layer between the two electrodes 620 and 624, and a hollow structure 633 is formed correspondingly in the upper electrode plate 632 by means of complementary mirror image, wherein the size of the hollow structure 633 is substantially equal to that of the portion with a length of X and a width of Y in an embodiment, that is, the area of the hollow structure 633 is substantially equal to that of the portion of the embedded planar resistor 610 on the same layer between the two electrodes 620 and 624. However, in an embodiment of practical application, the hollow structure 633 may also be slightly larger than or smaller than the portion of the embedded planar resistor 610 on the same layer between the two electrodes 620 and 624, which also falls within the application scope of the present invention. Additionally, the shape of the hollow structure 633 is similar to or different from that of the portion of the embedded planar resistor 610. A complementary hollow structure is formed in the upper electrode plate 632 adjacent to the embedded planar resistor 610, so as to reduce the parasitic capacitance, efficiently enhance the application frequency range, and reduce the dielectric loss between the embedded planar resistor and the metal ground plane.

In an alternative embodiment of the present invention, the size of the hollow structure 633 also can be designed in consideration of the areas of the electrodes 620 and 624, that is, the area of the hollow structure 632 may be designed to be larger than, equal to, or smaller than the sum of the area of the portion of the embedded planar resistor 610 on the same layer between the two electrodes 620 and 624 and the areas of the electrodes 620 and 624.

In an alternative embodiment of the present invention, the upper electrode plate 632 and the lower electrode plate 634 of the embedded capacitor 630 are respectively formed into hollow structures 633 and 637 by means of complementary mirror image, so as to reduce the parasitic capacitance, and efficiently enhance the application frequency range.

Another particular embodiment of the present invention is illustrated with reference to FIG. 7. FIG. 7 is a schematic cross-sectional view of a complementary mirror image embedded planar resistor architecture according to another preferred embodiment of the present invention. The complementary mirror image embedded planar resistor architecture includes an embedded planar resistor 710 that is located between two ground planes 730 and 740 and connected to strip lines 720 and 722, which are so-called strip line structures. A common strip line has contacts in the embedded metal, but in this embodiment, the contacts of the metal and the transmission lines are integrated as a whole. Therefore, no specific larger contacts are shown, and thus, no electrodes as that in FIG. 6 are shown. The strip line structure is often used in a design of a micro-wave circuit. Therefore, in this embodiment, the embedded planar resistor 710 requires that the upper ground plane 730 and the lower ground plane 740 both have a hollow structure. The complementary mirror image embedded planar resistor architecture includes, for example, the lower ground plane 730, the upper ground plane 740, and dielectric layers 750 and 760 sandwiched there-between. The lower ground plane 730 and the upper ground plane 740 have the hollow structures 732 and 742 respectively.

Additionally, the shapes of the hollow structures 732 and 742 may be similar to or different from that of the embedded planar resistor 710. The hollow structures 732 and 742 adjacent to the embedded planar resistor 710 are formed into a complementary hollow structure, so as to reduce the parasitic capacitance, efficiently enhance the application frequency range, and reduce the dielectric loss between the embedded planar resistor and the metal ground plane.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A complementary mirror image embedded planar resistor architecture, comprising: an embedded planar resistor, located on a first plane, wherein two ends of the embedded planar resistor are respectively connected to a first conductive wire and a second conductive wire;a conductive layer, located on a second plane; anda dielectric layer, made of at least one material, and sandwiched between the first plane and the second plane,wherein a hollow structure is formed in the conductive layer at the mirror image location corresponding to the embedded planar resistor, and the shape and area of the hollow structure are designed corresponding to the shape and area of the embedded planar resistor.

2. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the hollow structure is an entirely hollow structure, with an area of about 0.5-1.5 times of that of the embedded planar resistor.

3. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the hollow structure is a mesh structure having a plurality of holes.

4. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the hollow structure has plurality of strip-shaped holes.

5. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the first conductive wire and the second conductive wire are micro-strip line structures.

6. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the first conductive wire and the second conductive wire are strip line structures.

7. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the first conductive wire and the second conductive wire are floating line structures.

8. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the conductive layer is a ground plane or a power supply layer.

9. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, wherein the conductive layer is an electrode plate of an embedded capacitor structure.

10. The complementary mirror image embedded planar resistor architecture as claimed in claim 1, further comprising another conductive layer, wherein the conductive layer and said another conductive layer are ground planes, another hollow structure is formed in said another conductive layer at the mirror image location corresponding to the embedded planar resistor, and the shape and area of said another hollow structure are designed corresponding to the shape and area of the embedded planar resistor.

11. A complementary mirror image embedded planar resistor architecture, comprising: an embedded planar resistor, located on a first plane;a first electrode and a second electrode, located on the first plane, wherein the first electrode is used to connect the embedded planar resistor to a first conductive wire, and the second electrode is used to connect the embedded planar resistor to a second conductive wire;a conductive layer, located on a second plane; anda dielectric layer, made of at least one material, and sandwiched between the first plane and the second plane,wherein a hollow structure is formed in the conductive layer at the mirror image location corresponding to the embedded planar resistor, and the shape and area of the hollow structure are designed according to that of the embedded planar resistor, the first electrode, and the second electrode.

12. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the hollow structure is an entirely hollow structure, with an area of about 0.5-1.5 times of that of the embedded planar resistor.

13. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the hollow structure is a mesh structure having a plurality of holes.

14. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the hollow structure has a plurality of strip-shaped holes.

15. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the first conductive wire and the second conductive wire are micro-strip line structures.

16. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the first conductive wire and the second conductive wire are strip line structures.

17. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the first conductive wire and the second conductive wire are floating line structures.

18. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the conductive layer is a ground plane.

19. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the first electrode connected to the embedded planar resistor is grounded.

20. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the first electrode connected to the embedded planar resistor is a power supply, and the second electrode is grounded.

21. The complementary mirror image embedded planar resistor architecture as claimed in claim 11, wherein the first electrode is used to connect the embedded planar resistor to a first via hole, so as to further connect the embedded planar resistor to circuit elements on other planes, and the second electrode is used to connect the embedded planar resistor to a second via hole, so as to further connect the embedded planar resistor to circuit elements on other planes.

22. The complementary mirror image embedded planar resistor architecture as claimed in claim 21, wherein the first via hole and the second via hole are plated through holes (PTH) structures formed by a mechanical drilling machine.

23. The complementary mirror image embedded planar resistor architecture as claimed in claim 21, wherein the first via hole and the second via hole are laser via structures formed by a laser ablation machine.

24. The complementary mirror image embedded planar resistor architecture as claimed in claim 21, further comprising another conductive layer, wherein the conductive layer and said another conductive layer are ground planes, another hollow structure is formed in said another conductive layer at the mirror image location corresponding to the embedded planar resistor, and the shape and area of said another hollow structure are designed corresponding to that of the embedded planar resistor.

25. The complementary mirror image embedded planar resistor architecture as claimed in claim 24, wherein the conductive layer is an electrode plate of an embedded capacitor structure.

26. The complementary mirror image embedded planar resistor architecture as claimed in claim 25, wherein the other electrode plate of the embedded capacitor structure is formed into another hollow structure.