Patent Application
20180164432
This patent document relates to semiconductor technologies.
Semiconductor fabrication and nanotechnology provide techniques or processes for fabricating structures, devices, and systems with features at a micro or nano scale, e.g., structures in a range of one to hundreds of nanometers in some applications. Integrated circuits and microprocessors are examples of such structures, devices and systems.
Techniques, systems, and devices are described for implementing for implementing computation devices and artificial neurons based on nanoelectromechanical (NEMS) systems.
In one aspect, a nanoelectromechanical system (NEMS) based computing element includes: a substrate; two electrodes configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force. The first beam structure is kept at a constant voltage while the other voltage varies based on an input signal applied to the NEMS based computing element.
In another aspect, an artificial neural network includes: a plurality of nanoelectromechanical system (NEMS) based computing elements interfaced with one another and forming synaptic nodes, the NEMS based computing elements including: a substrate; and two electrodes configured as a first beam structure and a second beam structure, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force. The first beam structure is kept at a constant voltage while the other voltage varies based on an input signal applied to the NEMS based computing element.
In another aspect, a device based on nanoelectromechanical system (NEMS) elements includes: a substrate; nanoelectromechanical system (NEMS) elements formed over the substrate, each NEMS element including two electrodes configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact to allow for relative motion therebetween under an electrostatic force in response to an electrical signal applied to the NEMS element; and an array of SONAR (Sound Navigation and Ranging) devices formed over the substrate, each SONAR device operable to produce a sonic signal directed to the NEMS elements so that sonic signals from the SONAR devices form sonic communication links within the NMES elements.
In another aspect, a nanoelectromechanical system (NEMS) based multiplier element includes: a substrate; a first pair of electrodes disposed on the substrate and configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force; a second pair of electrodes disposed on the substrate mirroring the first pair of electrodes and configured as a third beam structure and a fourth beam structure positioned in close proximity with each other without contact, wherein the third beam structure is fixed to the substrate and the fourth beam structure is attached to the substrate while being free to bend under electrostatic force; wherein the first pair of electrodes and the second pair of electrodes mirror each other such that the second and fourth beam structures are on the inside of the combined structure. The multiplier element also includes a fifth beam structure disposed on the substrate between the second and fourth beam structures and serves as an output electrode. The first beam structure is coupled to a first voltage, the third beam structure is coupled to a second voltage that is the negative version of the first voltage, wherein the second and fourth beam structures are coupled to a third voltage. The fifth beam structure is configured to output a fourth voltage which is proportional to the product of the first voltage and the third voltage.
In another aspect, an ion-gas sensor device includes: a substrate including an array of pillars and troughs; a microfan component including a first stack and a second stack of layers of a piezoelectric composite material formed on the pillars of the substrate and protruding over the troughs, the first stack of layers to sense the flow of ions in a gas and the second stack of layers actuate to drive the ions to a detection region of the device at a controlled flow rate; a layer of a radioactive material formed in the trough of the substrate to ionize the gas when flowed above the layer; and an array of electrodes formed in the detection region to detect ion mobility of the ions of the gas
In another aspect, an chip-size gas analyzer includes: a chipscale ionization source configured to generate ions of the target compounds in the gas flowing through the sensor; a gas pump module configured to pump the ions of the target compounds into an area of chemical sensing; and a detection module configured to detect and identify target compounds.
In another aspect, a monolithic ultrasonic fingerprint scanner includes: an acoustic matching layer to provide a contact surface for a finger to make contact; an array of piezoelectric transducers disposed beneath the acoustic matching layer, wherein each of the piezoelectric transducers is operable to generate an incident acoustic wave or an incident acoustic pulse toward the acoustic matching layer and receive reflected acoustic waves or acoustic pulses off of an object being detected; and a CMOS die electrically coupled to the array of piezoelectric transducers to receive and process the piezoelectric transducers outputs produced in response to the reflected acoustic waves or the acoustic pulses.
Silicon-based and other semiconductor integrated circuit (IC) chips typically use conductive wires for in-chip communication links, which create several limitations in IC chip designs including spot heating, thermal cycling degradation of components, signal interference, among others. Some chip-scale communications approaches to mitigating such problems associated with conductive wires include optical and/or wireless in-chip communications which have been explored in several physical domains, but complement and/or add to the traditional metal interconnects.
In one example, photonic interconnects have been proposed as a way to transmit digital and analog information on optical waveguides integrated into a complementary metal-oxide-semiconductor (CMOS) stack. For example, optical waveguide interconnects can provide very high bandwidth and low power consumption information transmission within chips. However, due to the internal losses of optical signals in CMOS compatible optical waveguides, and the resulting high power for optical links, much work is still needed for use of optical interconnects. Also, one of the drawbacks of the photonic links is that the links are defined by lithography in the front end of line (FEOL) or back end of line (BEOL) IC fabrication processes, which can enable adversarial interests in the IC design to physically detect function, e.g., by detecting scattered light, or tracing the optical paths.
In another example, radio-on-chip networks have been proposed for ad-hoc wireless networks on chip. For example, such radio-on-chip networks can transmit over the chip using RF radio. Due to the large signal wavelengths corresponding to common RF frequencies, such RF transmitters are point emitters operating in the near field configurations that tend to use coded signals to reduce EM interference and thus require significant power consumption.
Additionally, there has been some effort in protecting IC designs that are mapped to field programmable gate arrays (FPGAs). For example, the key to determining the functionality of an FPGA is determining its bit-stream patterns with various parts of FPGAs. Bit-streams can be encrypted in high-end FPGAs to protect the contents of the configuration memory. The encryption key (e.g., a key based on the advanced encryption standard (AES)) is stored in volatile memory, and powered by a battery in an effort to defeat unsophisticated tampering. Obfuscation is also a commonly used software technique, and can also be applied to the hardware description language used to create the design mapped to the FPGA. These techniques can be combined with the notion of a physically unclonable function (e.g., logic whose behavior is a function of chip-specific process variations) to protect a design. However, these approaches do not protect against EM-based attacks or differential power analysis. In addition, an adversary may have access to the FEOL processing or the entire IC processing during the fabrication and production at a semiconductor foundry that is operated by another party.
In the past, microelectronic devices were manufactured by companies that both designed and produced the devices. At that time, manufacturing involved fine-tuning device and manufacturing process parameters, which often warranted a need for redesign involving both the research and development (R&D of the microcircuit design and the manufacturing processes. Currently, manufacturing processes are highly advanced and standardized such that multiple microelectronic device designs can be fabricated by a single, large-scale manufacturing entity. For example, separation of manufacturing and design has created a new model for microelectronic device fabrication: the foundry model. The foundry model refers to the separation of a semiconductor fabrication plant operation (foundry) from an integrated circuit design operation, e.g., enabling a “fabless” semiconductor company to operate without any semiconductor manufacturing capability but rather contract production from a separate manufacturer entity (merchant foundry). While the foundry model is economically efficient for rapid development of integrated circuit devices, it is subject to device security concerns including theft of device designs and unauthorized alterations or modifications during production by the merchant foundry or other adversarial actors.
Moreover, as the need for computational power increases, high density integration of transistors and other circuit elements, such as 2D integration and 3D integration of multiple processor layers, are becoming increasingly necessary for many IC applications to increase the IC processing power. One of the problems in highly integrated IC chips, e.g., vertically stacked 3D ICs, is the difficulty to provide complex and a large number of interconnects between different circuit elements. In a 3D stacked chip, for example, the number of communication channels between wafers tends to be limited because of the relatively large size of through-wafer vias (TWV) to ensure bonding reliability.
The technology disclosed in this patent document uses ultrasound transducers as communication transceivers for providing wireless ultrasonic communication interconnects between different circuit elements without hardwiring between circuit elements and as built-in circuit sensors for sensing circuit conditions. Such ultrasonic communication interconnects can significantly reduce the metal interconnects between circuit elements. The disclosed technology can be used to provide programmable or reconfigurable interconnects to enable fixed circuit elements to form various functionally different circuit devices and to conceal the final circuit functions and designs from an unauthorized party and from the physical fabrication or manufacturing of the circuits. The disclosed technology can also be implemented to address the above aforementioned technical problems and limitations.
Techniques, systems, and devices are described to provide 2D and 3D integrated circuit chip designs having integrated ultrasonic or acoustic in-chip communication links and nodes.
The disclosed technology integrates ultrasound actuator arrays into 2D or 3D IC chips to form sonar arrays that transmit a directional sonic pulse from one functional unit or module in the chip to another, providing tunable sonic intra-chip communication links between any two points by adjusting the delays/phases and/or amplitudes of the sonic communication signals on transmit. In some implementations, for example, the ultrasound actuators can be based on piezoelectric materials or elements. In addition, the ultrasound actuators can be configured using electrostatic transducers, e.g., including capacitive/electrostatic materials or elements (e.g., including capacitive micro-machined ultrasonic transducers (CMUT)), which can be implemented, for example, in addition to or instead of the piezoelectric-based actuators (e.g., the piezoelectric AlN transducer elements). Examples of CMUT transducer elements are described in Wygant, I., “A comparison of CMUTs and piezoelectric transducer elements for 2D medical imaging based on conventional simulation models”, Ultrasonics Symposium (IUS), 2011 IEEE International, Vol. 100, No. 18-21, October 2011, which is incorporated by reference as part of this patent document. More generally, the disclosed technology can implement the ultrasound in-chip wireless communication links using any of piezoelectric, electrostatic, magnetic, thermal, electrostrictive actuation/sensing elements acoustic communication signaling. In some implementations, such sonar modules can be used to transmit signals from one chip to another chip through a common substrate, while making use of the frequency-selective nature of acoustic transducers and waveguides to communicate to multiple receivers over different frequency bands at the same time, e.g., via frequency division multiplexing. Frequency division multiplexing can be implemented to carry different channels at different acoustic frequencies. For example, the integrated sonars can also be used to interrogate defects in chip interconnects over time to measure chip reliability.
The architectural diagram of the IC chip design 20 of the disclosed technology shown in
An ultrasound signal tends to have a footprint and spatial extent determined by the acoustic frequency of the signal and the physical conditions of the signal path that may cause diffraction, scattering and spreading of the ultrasound signal. The smallest beam spot size is dictated by the diffraction limit on the order of one half of the ultrasound signal wavelength. Accordingly, a metal interconnect may be configured to have a smaller footprint than that of an ultrasound signal interconnect. In implementing the wireless ultrasound signaling as interconnects for different circuit elements in the IC chip design 20 in
Each of the ultrasound transducer modules of
The disclosed acoustic in-chip communication technology can be implemented to provide many advantages. For example, the disclosed acoustic in-chip communication can use linear and two-dimensional arrays of piezoelectric transducers to generate directional ultrasonic pulses in three dimensions for CMOS information processing and trusted integrated circuit (TIC) operation. For example, exemplary phased array sonic transducers can be operated at GHz frequencies alongside and/or integrated with other analog or digital chip logic on a single IC chip. For example, the disclosed technology can be implemented in a variety of applications including medical (ultrasound) imaging, non-destructive evaluation (NDE) of IC chip components, and sonar communications. Historically, for example, these arrays have operated in the frequency range of 1-30 MHz for medical imaging, 100 kHz to 10 MHz for NDE, and 1-100 kHz for sonar communications. By operating at high frequencies of 1-10 GHz, the wavelength in silicon can be in an exemplary range of 9 to 0.9 μm. Since the elements of a sonar array are spaced by fractions of the sonic wavelength (e.g., λ/2), chip devices employing the disclosed technology can be configured with hundreds to thousands of sonar arrays, e.g., for a millimeter to centimeter sized IC chip.
For example, the disclosed acoustic in-chip communication technology can provide a sonic 2D or 3D programmable interconnect framework for massively parallel computation in IC chip devices. The sonic 2D or 3D IC interconnects can enable communications in one chip, or through IC stacks, forming a user defined communications layer for 3D ICs. In some implementations, encrypted pulse sequences can be used to form secure communication channels that are ad-hoc in nature, e.g., providing programmable wireless interconnections between discrete IC elements (e.g., of the FEOL portion). The added interconnect capability can allow the programmers to use ultra-high fan-out and fan-in capabilities, e.g., which is often needed to implement algorithms in associative pattern recognition algorithms, such as in applications including face or feature recognition in image processing. Furthermore, the added acoustic programmable wireless link can relieve the communications bottleneck encountered in multi-core digital systems.
For example, the disclosed acoustic in-chip communication technology can provide sonar based chip-interrogation. For example, the disclosed integrated piezoelectric transducer arrays can be used to interrogate the chip or a multi-chip package to realize an integrated non-destructive evaluation (NDE) capability. Such interrogations can be employed for chip-scale NDE of wire-bonds, chip-to-chip interconnects, vias, etc. Also, for example, for security, an adversary initiated chip manipulation could be detected at a very early stage (e.g., such as by a merchant foundry for manufacturing of an IC chip design). Moreover, early detection of chip tampering could lead to immediate removal of memory or self-destruction for trusted use of integrated circuits.
Furthermore, most existing IC devices generate substantial amounts of heat that can (1) lead to degradation of portions or the entire IC device and (2) lower performance (e.g., speed) of the device during operation, e.g., particularly during extensive periods of use. IC devices can undergo various spot heating, in which particular locations or regions (e.g., circuit blocks) of the IC generate high heat. For example, the disclosed integrated piezoelectric transducer arrays can be used to monitor spot heating within the IC device to which the disclosed transducer arrays are employed. Knowledge of spot heating during operation of IC devices is of great interest, as such monitoring could be used to reroute process implementations to other IC device resources in areas outside of the spot heating, thereby allowing for the spot heat to dissipate faster and avoid reduced device performance or degradation.
Moreover, for example, the disclosed integrated piezoelectric transducer arrays can be used to image and thereby monitor structural defects and fractures of in-chip elements and chip-to-chip interconnection structures that can lead to device failure. For example, thermal cycling of ICs in various microchip-based devices like computers, mobile communication (smart phone devices), etc. can also cause degradation at the grease interface between IC chips and their coupled heat syncs. Additionally, delamination of solder balls at wire bonding interfaces is a common problems that result in premature failure of such chip-based devices. Thus, using the disclosed technology, sonar based chip-interrogation can be implemented to prolong the lifetime of such chip-based devices.
For example, the disclosed acoustic in-chip communication technology can provide sonar based lock-key operations. For example, for safe operation of some proprietary chip-sets, a lock/key system is employed to ensure activation by a known entity, and deem the chip inoperable by an adversary. Current methods include microelectromechanical systems (MEMS) gears and beams for enabling a lock, which although effective can be not as reliable due to stiction. For example, the disclosed integrated piezoelectric transducer arrays can be used to provide sonar links to read surfaces preprogrammed to reflect ultrasonic pulses through a set of programmable reflectors, triggering a device if the pulse makes it to a target receiver on chip.
In one aspect, an integrated circuit chip device with wireless on-chip communications capabilities includes a semiconductor substrate capable of propagating acoustic energy signals and an array of acoustic signaling modules formed on the substrate and structured to include a sub-array of acoustic transducer elements capable of transmitting and receiving the acoustic energy signals, in which each acoustic transducer element is operable to generate an acoustic communications signal to propagate through the substrate based on an electronic control signal and to receive the acoustic communications signal an acoustic signaling module to communicate with one or more other acoustic signaling modules. For example, the device can further include a control circuit layer formed on the semiconductor substrate and under the array of acoustic signaling modules to receive an external electronic signal and produce the electronic control signal to one or more acoustic transducer elements. For example, the acoustic communications signal can be modulated by the device using one or more of amplitude modulation, frequency modulation, or phase modulation.
In another aspect, a semiconductor integrated circuit device having wireless ultrasonic communication links includes a semiconductor substrate, layers formed over the semiconductor substrate and patterned to form circuit elements including transistors, and an array of ultrasound transducers formed in the layers over the semiconductor substrate, each ultrasound transducer including ultrasound transducer elements which are operable to generate an ultrasound signal carrying information to communicate with one or more ultrasound transducers in the array and are operable to receive an incident ultrasound signal from one or more ultrasound transducers, the ultrasound transducers being communicatively coupled to respective individual circuit elements or blocks of two or more circuit elements of the circuit elements formed in the layers over the semiconductor substrate to act as communication nodes for the respective individual circuit elements or blocks of two or more circuit elements with other individual circuit elements or blocks of two or more circuit elements. Each ultrasound transducer in the array of ultrasound transducers is configured to control transmission or reception of the ultrasound transducers so that the ultrasound transducers in the array of ultrasound transducers are interconnected via ultrasound signals to form an ultrasound communication network of ultrasonic communication links, without hardwiring via metal contacts, between the circuit elements formed in the layers over the semiconductor substrate.
In some implementations, for example, the device 100 can further include an acoustic reflector/mismatching layer 125 capable of reflecting or refracting the exemplary intra-device ultrasound signal, e.g., which can be used to steer the ultrasound communication signal from one or more sonar modules 110 to another one or more sonar modules 110. For example, the acoustic reflector layer 125 can be configured under the acoustic propagation medium substrate 120, as shown in
As shown in
For example, the metal layer structures 133, 134a, 134b, and/or 134c function both as interconnect layer(s) for electronics, and can also function as part of the disclosed technology as custom designed acoustic wave guiding, channeling, or scattering structures. In some examples, is also possible to clear the underlying regions of certain pixels of metals and route them around the pixels to allow propagation of ultrasonic signals without any obstruction.
The sonar modules 110 are operable to receive and convert an electrical control signal to generate an acoustic energy wave or pulse carrying a communication signal to communicate with one or more other sonar modules of the array, which can receive the acoustic communication signal and transduce it to an electrical signal. For example, the array of sonar modules 110 can operate as acoustic transmitter and receiver (transceiver) modules, which can communicate with each other by proper phasing of sonar pulses sent at desired angles, frequency division modulation, or other techniques. As shown in
In some implementations, the generated ultrasound signal 111 can be a continuous or pulsed ultrasound (sonic) wave. For example, the sonic waves can be generated at frequencies from the hundreds of MHz to GHz in a silicon-based propagation medium, with the corresponding wavelengths in a range from the tens to single microns, e.g., including 90 to 9 μm wavelength sonic waves at 100 MHz to 1 GHz frequencies, respectively, in a silicon medium. The relatively small acoustic wavelength, e.g., as compared to the thickness of the silicon medium or substrate, enables the use of the propagation medium 120 to transmit the ultrasound signals from one place to another.
For example, the ultrasound beam 111 can be launched into the propagation medium 120 at a wide range of solid angles and targeted to a specific receiver sonar module 110b, e.g. any of the sonar modules in the array, by adjusting the delays/phases and amplitudes of the ultrasound pulses to each of the piezoelectric transducer elements 130.
In some implementations of the disclosed acoustic in-chip communication technology, for example, further accuracy in targeting can be achieved by recombining the electronic signals from the receiving transducer array with appropriate delays for the desired channel. This sonic programmable communications channel can be used as a reconfigurable interconnect network that a non-desired party (adversarial interests) cannot determine with any physical scheme. The sonic interconnects can be software defined, and hence protectable using many methods of software encoding.
The exemplary acoustic in-chip communication devices can be configured to prevent the acoustic signals from propagating out of the device, or leaking. For example, because sound waves decay very fast and they cannot propagate out of the device, it can be very hard for a non-desired user (or adversary) to listen to the acoustic channels. For example, since optimal communication uses both the configuration of the transmitter and receiver arrays, the actual acoustic signals can be obfuscated with deliberate transmitter spurious signals that match nulls in the receivers but are otherwise indistinguishable from the real signals.
For example, a different modality of ultrasonic chip-scale/board-level communication is possible under acoustically mismatched or highly reflective boundary conditions instead of absorbing boundary conditions. In this exemplary mode, individual ultrasonic transducers on the transmitting array can be used to control standing wave patterns at the transducers of the receiving array. As such, the disclosed acoustic in-chip communication devices can be regarded as a large acoustic resonator, to which different transducers located at different locations couple to with varying coupling coefficients that are a function of frequency of excitation. A matrix approach based on linear superposition is useful to model the linear regime of this modality.
Linear phased arrays can be used to focus a beam and aim it in the desired direction with characteristic radiation profiles. In ultrasound imaging, the beam can be scanned over the target field, and the returned signal is used to form the image based on acoustic reflection/transmission characteristics or time-of-flight information. In the disclosed technology, scanning a beam and focusing it in a single direction allows for the choice of where to communicate data. The principles of beam steering and focusing, e.g., using a linear phased array, is described, which is important for the understanding of the disclosed techniques of SONAR (SOund NAvigation & Ranging) operation. Examples of beam steering and focusing of the disclosed transducer arrays based devices for ultrasound imaging applications, for example, are described in: “An Integrated Circuit with Transmit Beamforming and Parallel Receive Channels for Real-Time Three-Dimensional Ultrasound Imaging” by Wygant et al., 2006 IEEE Ultrasonics Symposium (IUS), pp. 2186-89; “Circuit Design and Simulation of a Transmit Beamforming ASIC for High-Frequency Ultrasonic Imaging Systems” by Athanasopoulos et al., 2011 IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 58, No. 7, pp. 1320-31; and “Medical Imaging: Principles, Detectors, and Electronics—Chapter 7: Electronics for Diagnostic Ultrasound” by Wodnicki et al., Krzysztof Iniewski (ed), John Wiley & Sons 2009, in which the aforementioned documents are incorporated by reference as part of this patent document.
w=Ae
j(kr−ωt+β) (1)
In Equation (1), A is the amplitude of the signal, k is the wavenumber, r is the spherical radius from the source, ω is the frequency, t is time, and β is the time phase delay of the source. If the target point T is far enough away such that R is much greater than the inter-element spacing d, than the angle θ (with respect to the positive z direction) for all the elements can be approximated as the same. This means that effectively all of the paths to the target from the elements are parallel, and the difference in path length, Δrn=Rn−R, can be found from a simple trigonometric identity:
This leads to the pattern radiating from the nth element in the array to have the following form in Equation (3):
w
n
=Ae
j(k(R+Δr
)−ωt+β
) (3)
If the actuation pattern of the array is chosen so that all elements are operated with the same amplitude and frequency but different phases, then the corresponding acoustic phasor at the target point T, ωt, is the sum of all the wave contributions wn of the individual elements as given by Equation (4):
w
t
=Ae
jkR
e
−jωtΣn=0N−1ej(kΔr
From this equation, it can be seen that a maximum will occur when the following equality is met:
By selecting a value for θ, the phase delay needed at each element can be calculated. From Equation (5), it can be seen that the phase is linear between elements. However, for example, due to the cyclic nature of both Equations (4) and (5), in addition to the designed main lobe of the beam, undesirable side-lobes may appear as well. Careful design of element spacing and number of elements is implemented to treat such results. In addition to this, there can be a trade-off in terms of space and power, which is taken into account.
For example, using a single isotropic acoustic radiator as in
Exemplary simulations of the disclosed acoustic in-chip communication devices were performed. For example, the exemplary simulations utilized Finite Element Modeling (FEM) software, which can provide a tool to aid in the phased-array design, especially in the presence of complex boundary conditions. Also, for example, PZFlex was used to calculate time domain responses of materials to phased acoustic excitations of piezoelectric elements on a silicon substrate. In the exemplary simulations, each element is pulsed with wavelet pulses of either in-phase or a linearly changing phase difference between elements. The exemplary resulting acoustic pressure field is plotted in
PZFlex was also used to calculate the time domain response of a single element pulsed as well as the received signals on the neighboring pixels. For example, a voltage signal on the first pixel creates an acoustic wave, which travels through the silicon substrate and reflects off of the back surface and returns to the top surface. As it travels beam spreads out and the neighboring pixel will generate a voltage in response to the acoustic pulse.
Exemplary implementations of the disclosed acoustic in-chip communication technology were performed. In one implementation, for example, exemplary acoustic in-chip communication devices were fabricated using an RF MEMS process. Starting with a silicon substrate, the RF MEMS process involved deposition of silicon dioxide of 3.5 μm. Trenches were etched into the silicon dioxide and filled with tungsten, which was then planarized using chemical mechanical polishing. The tungsten can act as an etch stop for the aluminum nitride in subsequent steps. Next, a bottom electrode was deposited and patterned for the back side electrical contact. This was followed by the deposition of the piezoelectric aluminum nitride layer. After a photolithography step, the piezoelectric aluminum nitride layer was etched until reaching the tungsten layer. Finally, a top layer metal was deposited and patterned for the exemplary devices. In one exemplary embodiment of the devices for a SONAR system, a four by four piezoelectric transducer element array was laid out in this process. The exemplary transducer elements were configured to be 100 μm×100 μm squares separated by 200 μm.
The exemplary fabricated silicon die with the aluminum nitride arrays was mounted to a printed circuit board (PCB) to perform tests using an HP8753ES RF network analyzer, as shown by the image in
In one exemplary implementation, two pixels in the array of the exemplary device shown in
As shown in these exemplary implementations, exemplary ultrasonic phased arrays in-chip communication devices can be integrated on chip to enable pulses to be transmitted from any location to another by beam steering for reconfigurable communication links. Exemplary results showed acoustic coupling between the transducer elements in the array, e.g., by measuring the reflection scattering parameters of the two exemplary microfabricated, 100 μm×100 μm AlN transducer elements, which are spaced 400 μm away within the same 4×4 array.
In some aspects, the disclosed array of CMOS-integrated piezoelectric transducer (sonar) modules can be integrated into a 3D chip-stack to enable pulses to be transmitted from any location to another by beam steering. An array of sonar elements can transmit sound pulses through stacks with mechanical connections.
In some aspects, the disclosed technology includes fabrication methods to produce 2D and 3D in-chip wireless communication signaling devices.
In one exemplary embodiment, a method to fabricate exemplary chip-scale wireless communications IC devices, e.g., including the devices 100 and 700, can include AlN deposition techniques to form the piezoelectric transducer arrays. In some examples, sputter deposition of AlN is implemented at low temperatures (range), e.g., to be compatible with CMOS, but may utilize optimum metals like Tantalum for best films. The deposition of AlN at low temperatures also enables the placement of AlN embedded in the metallization stack. In some implementations, PZT thin films can be deposited though the sol-gel process, and require an anneal step which is typically at 700-800° C. This high temperature implies that the process flow for the PZT is to be implemented after CMOS fabrication. For example, PZT films can be transferred onto CMOS-based chips using oxide-oxide bonding, oxide-metal bonding, or metal-metal bonding.
In some implementations for example, the exemplary AlN stack with TEOS oxide layers can form a 1-D waveguide to launch pressure (P) waves, also referred to as longitudinal waves, with the motion transduced into the thickness of the wafer. For such exemplary implementations, the exemplary devices can be designed and fabricated to effectuate the longitudinal wave impedance of the silicon wafer and possible reflections and transmissions through metal layers, e.g., which can be intentionally placed in the IC design to tune the impedance of the transducer.
For example, the design and fabrication of the exemplary wireless in-chip communication devices can be implemented to mitigate the effects of shear and SAW waves. For example, in addition to the longitudinal waves, the transducers can couple energy into shear and surface acoustic waves. For a pulse transduction, 67% of the energy is emitted as a surface wave if a surface transducer is used. In some examples, the exemplary techniques can determine the transducers design spacing by spacing the array elements in the stop-band of SAW waves. Longitudinal and shear waves can thus be used for the communication links, e.g., to minimize the coupling of energy into shear and SAW modes, as the wave motion corresponding to these modes will travel at different speeds and different directions, leading to unwanted cross-talk. Similarly, for example, shear waves can be minimized by configuring electrodes in symmetrical geometries to cancel out shear motion.
In some aspects, the disclosed technology includes devices and techniques for direct CMOS integration with the disclosed ultrasonic transducers, e.g., including the piezoelectric transducer elements configured in a layer adjacent to a layer of CMOS transmit and receive electronics on the same wafer. For example, such integration reduces load capacitance and inductance by minimizing interconnect and routing area and by eliminating wire bonds. The reduction of the load capacitance presented by the interconnects between the electronics and the piezoelectric transducer elements can lower transmit amplitudes such that higher receive amplitudes can be obtained. Also, a reduction in area allows more transducers and electronics to be integrated in the IC device. Furthermore, parasitic capacitances and inductances from the interconnects and routing between control circuits and transducer elements can be kept to minimum in the disclosed IC designs, such that their effect on the frequency response of the transmit and receive circuitry is negligible. Also for example, in some implementations, the transmit and receive electronics corresponding to a sonar pixel can be configured directly beneath the transducer element such that the problem of signal crosstalk between wiring carrying signals from different pixels is minimized.
The disclosed technology can include a variety of circuits for controlling the phase or delay of pixel excitation waveforms. Described are two exemplary circuit topologies that can be implemented in the exemplary control electronics for controlling the phase or delay of the acoustic waveforms: delay generation through inverter based delay lines and the generation of phase shifts through quadrature mixing.
In one example, digital delay lines can be used to obtain the necessary delays. These exemplary delay lines can include one or more inverter delay elements, such as those shown in
For example, the delay control voltages or current sources, as in the case of the current starving topology in
In another example, phase shifting a sinusoidal waveform can be implemented to generate the necessary delays. For example, the phase shifting is implemented through a quadrature mixing scheme, e.g., including two analog weights A and B that are multiplied with waveforms sin(ωt) and cos(ωt), respectively, and then added for an output waveform of A sin(ωt)+B cos(ωt). For example, this is equivalent to an output of C sin(ωt+φ), where C is √{square root over (A2+B2)} and φ is tan−1 (B/A). Constant amplitude phase shifting can be obtained by selecting the analog weights A and B to be C cos φ and C sin φ, respectively, where C is the desired output amplitude and φ is the desired output phase.
For example, to implement a large number of sonar pixels, it is desired to keep the power and area consumed by the supporting electronics as low as possible. As an exemplary alternative to implementing multiple DACs per pixel, an analog memory for analog weight storage can be used instead. For example, each D/A converter can be replaced by a cell comprising of a single capacitor C1 and a switch S1 used to selectively write to the capacitor.
Several modifications can be made to this exemplary analog memory architecture to increase leakage tolerance. For example, by switching to a differential input mixer topology and using two of the capacitor based analog memory cells instead of a single one, the voltage difference of the two cells is used as the input and thus the effect of leakage can be greatly reduced. Alternatively, active analog memories which employ some form of leak compensation can be used. For even longer term storage, instead of using a capacitor, non-volatile storage elements such as floating gate transistors can be used instead.
Other methods of delay generation derived from ultrasonic imaging systems may also be implemented. In some examples, the transmit path of an ultrasonic imaging system typically includes the transmit beamforming electronics followed by a high voltage pulser. Multilevel pulsers can be used to send signals of different output voltages, which can be used in beamforming. As sufficient receive amplitudes can be obtained while driving the sonar transducer at amplitudes below the nominal supply voltages for transistors on advanced process nodes, a high voltage driver is not necessary.
As the transmit beamformer for ultrasonic imaging applications is typically digital in nature, shift registers or timer/counter circuits may be used to implement the transmit delays. For example, for the case of a counter, instead of applying an input waveform and delaying it, a comparator can be used at the counter outputs to generate a trigger signal once the counter reaches a certain value. This exemplary trigger signal then activates a pulser circuit which outputs a single or multiple pulses at the desired voltage, pulse width, and frequency. For example, delay resolution can be improved by employing clock division with delay locked loop based circuits.
The above-disclosed technology can be implemented in various devices and systems, and applied to various of applications.
Nanotechnology provides techniques or processes for fabricating structures, devices, and systems with features at a molecular or atomic scale, e.g., structures in a range of one to hundreds of nanometers in some applications. For example, nano-scale devices can be configured to sizes similar to some large molecules. Nano-sized materials used to create a nanostructure, nanodevice, or a nanosystem that can exhibit various unique properties, e.g., including optical and electronic properties, that are not present in the same materials at larger dimensions and such unique properties can be exploited for a wide range of applications.
Techniques, systems, and devices are described for implementing for implementing computation devices and artificial neurons based on nanoelectromechanical (NEMS) systems.
Perceptron architectures use a number of computational neurons and learning techniques to adjust the weights depending on the agreements of the outputs of the neurons to input patterns (Hebbian learning). Because the success of the neural computing topologies when performing pattern recognition depend on the number of computational neurons used, much work has focused on providing a higher density of computational neurons and connectivity, attempting to rival the biological neuron densities exhibited in the human brain. For example, CMOS quadrant multiplier arrays in conjunction with analog memory in the form of stored charge on capacitors have been used to form analog CMOS neurons. These approaches consume significant power due to bias currents required for the analog multipliers, compounded by leakage currents in active mode in highly scaled transistors. For example, to maintain a biologically equivalent power budget of 50 W for 1011 neurons, implies 0.5 nW per neuron, further implying an average bias current of 1 nA assuming 0.5 V power supply. These currents are too low for proper operation of even deep-subthreshold analog designs. Furthermore, the synaptic connection density to other neurons is limited both by the size of the multipliers and by interconnect densities enabled with planar processes.
Table 1 shows the power and area associated with CMOS analog and CMOS digital budgets for adders and multipliers, as well as for that of an exemplary NEMS implementation. In digital systems, the ½CV2 is determined by the number of transistors at the given technology node.
Described herein is NEMS (Nano Electromechanical Systems) technology to realize multipliers and adders that operate with bias currents on the order of femto-amps at voltages of less than one volt, for example, across capacitances on the order of femtowatts. Hence the power consumed in such multipliers can be on the order of femtowatts.
In the discussion below, a perceptron refers to a network of building blocks (also referred to as “computational neurons”) that is operable to multiply the inputs by weights, sum the multiplied terms, and then use a nonlinear function to determine if the neurons should produce output pulses. A “synapse” refers to a weights used to multiply within the computational neuron.
where ε0 is the permittivity of air, go is the initial gap, and x is the displacement due to electrostatic force. In the exemplary case the displacement x is going to be much less than the gap g, and then the force can be written as
The current across this capacitor is dominated by the Fowler-Nordheim tunneling current. This current is typically in fA/um2 for 15V/um electric fields, providing the basis of average DC power consumption of femtowatts.
The building block actuator can be combined to form analog multipliers.
The net force is the sum of F+ and F−, where the quadratic terms cancel out, and only the products remain. This motion can be used to transduce the product term of xi, and wi,j.
Capacitive Product Transduction
Referring back to
The individual capacitance values can be found as follows:
where x1 and x2 are found from
In the above expressions, k (e. g.,
is the spring constant of a clamped-clamped cantilever beam. By substituting these values into the expression for Vout the following expression is obtained:
One important assumption made to get (7) is that the displacements x1 and x2 are small compared to the gap length g.
The operating voltages can be chosen such that the beams never touch and hence will not suffer from stiction, which is one of the concerns in NEMS reliability. Because the multiplication and adding operations in the array of capacitive multipliers shown in
The product of the weight and input is related to the difference between the two capacitances. Since these capacitances are not constant, the sum of the two capacitances will cause a nonlinearity in the circuit read-out. The change in capacitance is small compared to the magnitude of the capacitance; this expression is approximately linear. A simulation is run using this expression for the following design parameters: beam length is 3 um, width is 2 um, thickness is 50 nm, and gaps are 50 nm.
For the chosen dimensions and the voltages shown in
where m is the mass of the beam, kB is Boltzmann constant, T is temperature, k is the spring constant, and Δf is the bandwidth. Using this expression for displacement, the RMS value of the output voltage due to thermal noise is on the order of 10 nV. This leads to a dynamic range of 60 dB given the maximum unamplified signal amplitude of 20 mV as mentioned before.
Another useful metric is the resonance frequency and hence the upper bound frequency of device operation. Considering the geometries as described above, the resonant frequency can depend on the spring constant and the mass of the beam. For the previously mentioned geometry, the resonant frequency is 190 MHz. This frequency can be increased by shortening the beam dimensions, which also allows optimization between noise and dynamic range of the overall system. For instance, decreasing the beam length from 3 μm to 1 μm results in a resonant frequency of 1.7 GHz, an RMS noise level of 2 nV, and a signal level of 0.2 mV.
Piezoresistive Product Transduction
While
In
CMOS Digital/Analog (D/A) Converter for Capacitive Weights
While the NEMS multipliers described above operate in analog domain, conversion of the digital outputs from the digital implementation of a perceptron is necessary. While D/A conversions can be implemented in CMOS technology, Table 1 suggests that NEMS implementations can be used to achieve lower energy per operation and therefore high integration density because using capacitive/electrostatic actuation of beams to replace CMOS transistors requires near zero DC power consumption.
Assume individual spring constants are designed such that ki=ka(2i) where and where ka is a unit spring constant that is arbitrary based on the design and is equal to the spring constant of the bit 0. Actuator corresponding to bit i moves according to the expression:
Denote the sum of spring constants of all actuators as Σki=(2N−1)ka=ks. Then the displacement of the shuttle can be expressed as
which is the ideal DAC characteristic. Here kshuttle is the spring constant associated with the common shuttle that all the DAC units are mechanically connected to. It is possible to introduce non-volatility to the digital inputs bi by associating each bit with the bistable state of a buckled beam, essentially acting as a binary memory.
An alternative route to spring constant adjustment for DAC operation can be realized by repetition of unit cells. This exemplary approach can be more robust in the case of fabrication variations in deep-sub-micron processes that can make precise adjustment of spring constants difficult. Here each bit bi is repeated 2i times based on its binary weight, to avoid precise tuning of spring constants.
The above-described concept of low power high density integration of perceptron nodes (i.e. “computational neurons”) using capacitive actuated beams can be applied to implementing low power high density switches.
The increase of the number of synapses or neurons to obtain high spatial densities is a key to increasing the effectiveness of artificial intelligence (AI) learning techniques. Furthermore, the connections among neurons for communication purposes often need to be formed over large distances. The communications for setting up the weights and the connectivity among neurons need to be programmable and power-efficient. The above-described SONAR (Sound Navigation and Ranging) techniques can be used to form a 3D communication networks to read and set the weights of each neuron to facilitate very high fanouts in a programmable manner. At present many efforts are underway to investigate chip-scale optical, magnetic, and RF approaches to signal routing in 3D configuration. These approaches are used for higher bandwidth, but are limited by their fanout capability. The proposed neuron computing architectures require moderate bandwidth, but result in great number of inputs and outputs.
The neuron building blocks can be in the size scale of 20-100 um in all directions. In order to address each neuron individually in a 3D space, a communication channel can be focused into 100-um size volumes. For localization of digital pulses, this means that the associated communication wavelengths also have to be in the 20-100 um range. Acoustic and ultrasonic waves have reasonably low frequencies at such wavelengths, owing to the much lower speed of sound. Hence, beam-forming sonars can be used to construct communication channels, for example, using N piezoelectric pixel elements/actutators. These pixels can focus sonic energy onto different directions in a 3D space, for example, by adjusting the actuation amplitude and phase or time-delay of the N actuators (
In one example, 3D programmable ultrasonic interconnects comprise an array of ultrasonic transducers, operating at 1-GHz, and can generate waves with 9-micron wavelength in silicon. Each transducer itself is a multiple of few half-wavelengths. By developing a phased array of such transducers, a transmitting beam can be focused with approximately 4.5-micron focus. These beams can be used to transmit and listen generated sonic waves. The outputs of each neuron can be used to drive a receiver sonic transducer. This architecture allows for a high degree of 3D integration. Each pulse can be synthesized with a number of acoustic cycles to ensure desired signal to noise ratio at the receivers. The sonic absorption of GHz sound in silicon is very low (˜0.1 db/m), due to the high quality factor of silicon. Furthermore, the variations in speed of sound in materials in silicon chips are not substantial leading to transmission of energy through interfacial bonds, metallization layers, and oxide layers. The ultrasonic waves can travel through ultrasonic waveguides with minimal reflection and scattering losses, the minimization of which can be explored by developing sections of each NEMS computational neuron.
Exemplary NEMS Process Development:
Exemplary SOI based process flow to implement NEMS switches. This exemplary process can provide 50 nm gaps using e-beam and DUV lithography, e.g. with an exemplary design space of the spring constants, and the device variability can be measured to help in optimized bounded designs. This exemplary process can be modified such that the connections to beams can be made to a CMOS chip by flip chip bonding.
Exemplary NEMS Vector Product Design Space:
a multivariable optimization code can extract the equivalent SPICE models for the NEMS multipliers and adders, such that the models can be directly be interfaced to CADENCE CMOS layout tools. An exemplary model for NEMS switches can be adopted for an exemplary analog computation model.
Exemplary NEMS DAC Development—
exemplary NEMS process flow and models. Different DAC designs based on NEMS conversion can be implemented to chart out the tradeoffs between power, bit resolution, and space per weight. CMOS circuits to implement the weight storage and connections to the DAC can be included in the MOSIS tapeouts. In the exemplary Phase I, 8 bits DAC resolution, which can be extended to 16 bits in the exemplary Phase II. Conversion from floating point numbers can be implemented to extend the dynamic range of the weights that can allow for more direct translation of the software inference engine.
Exemplary AlN Ultrasonic Sonar for High Fanout Development:
An exemplary process flow to integrate AlN pixel array and simple digital drivers for phased array but transmission in 3 dimensions. CMOS circuits can be implemented after characterizing AlN transducers for the equivalent circuit at the peak transduction frequency. The range, link budget as function of carrier frequency and power can be modeled and verified from 3D interconnects.
Exemplary Implementation of the Inference Engine in NEMS—
The exemplary NEMS chip can be interfaced to the CMOS circuitry to enable the direct hardware mapping of the inference engines. Sonic fanout and direct wired connectivity between nodes can be compared to see what will give higher degree of accuracy for output and learning. The learning algorithms can be implemented in the digital electronics section.
In some aspects, the disclosed technology includes nanoscale devices for ultralow power vector product computation and high fanout.
NEMS Nanoelectromechanical Synapses—
The quadratic relationship between the force and the applied voltage across nano-scale beams can be used to realize femtowatt multiplications between weights and input. In addition, nanomechanical transduction of the multiplication weights can be added in series in parallel with zero additional power. Capacitive addition and resistance addition can be used to achieve massively parallel addition. Nanoscale transduction can be provided by the piezoelectricity in graphene, an effect recently discovered as part of the disclosed technology. The disclosed technology can include parallelizing the multiplication and addition vector product in parallel at speeds in the gigahertz range, e.g., enabling real-time image processing applications. The weights can be stored in analog and digital states. The weights can be presented to the multipliers through analog CMOS and exemplary NEMS of the disclosed technology. The disclosed NEMS D to A converters can use new architectures to provide femtowatt DA converters. With the NEMS vector-product architecture, 107 ops/ns μW can be achieved. The disclosed base technology includes nanomechanical switches as synaptic nonlinear switches which consume femotowatt DC power, and multi-gap electrostatic inputs enables multi-threshold actuation for high dynamic range of weights. The disclosed NEMS technology can be used in non-contact mode, sidestepping issue with the reliability of actual mechanical contacts, and relying only on nm-scale displacements of beams to modulate gaps and strains.
Sonar Interconnections—
The inference engine requires high fanout, to a sparse network of computational nodes. Furthermore, these fanout nodes need to be formed on the fly as the network evolves. In the disclosed technology, ultrasonic pulses in the GHz range can be used to form a programmable sonar interconnect system. The wavelengths of GHz sonic pulses can be the 5-10 um range enabling focusing sonic pulses from one channel to another in 3D using piezoelectric phased arrays with programmability and ability to write to thousands of inputs serially at kHz rates, e.g., rates needed for real time image processing. The SONAR elements can take information and transmit it to each 3D stacked NEMS neurons, which each has power going to them and may be locally connected, allowing for weights to be changed across a much larger volume, and creating a very high fanout.
Integrated Circuits Based Devices for Volatile Compound Detection
Fast and reliable detection of toxic gas-phase industrial chemicals and warfare agents, which may be combustible, odorless, and colorless, necessitates the use of miniaturized multi-functional and portable gas analyzing systems. Disclosed are gas sensor devices, systems, and techniques for measuring ion-mobility and identifying chemical compounds in a gas-phase sample using a silicon micro-machined ion-mobility spectrometer array (IMSA), which is obtained from a versatile high aspect-ratio 3-D fabrication process. The multi-electrode architecture facilitates simultaneous detection of more than one gas species. Such a device has potential use for on-chip ion trapping in a quadrupole or hexapole electrode configuration. It also paves the way for a label-free gas analyzing system that can be monolithically integrated with on-chip low-noise amplifiers to produce a low-cost mobile platform for detection and analysis of multiple gas species.
CMOS Ionization Source
In order to identify multiple species of volatile organic compounds (VOC) in charge neutral mixture of compounds in air on the basis of ion-mobility, the molecules need to be ionized. Electrons can ionize gas molecules effectively, and the generated ions have a specific time history of creation and recombination. Ion-formation processes are well-understood. The first ionization energies of gas-phase molecules are of the order of 1-100 eV based on electron-affinity of the molecules, molecular size which determines the tightness of the electron binding, steric hindrance properties etc. The creation of the ions occurs at the time scale of nanoseconds, while recombination can occur at time scale of micro-seconds to milliseconds. It is assumed that the time history of the charge cloud formation and annihilation will contain information to identify the gas species ionized.
Basis for Performance Targets (Calculations, Simulations, Data):
For the measurement of ion-motion, the ions need to be generated in air. Traditionally, this has been done with on-chip heating via tungsten wires which emit thermal electrons. However, such ion-generation is power hungry (1-100 mW) and can lead to device failure over time due to heating and corrosion. This problem can be overcome using electron-emitting radioactive 63Ni for ionization—from the Fermi theory of beta decay, the shape of the energy distribution for allowed transitions in 63Ni−N(E)=C(E2+2Emec2)1/2(Q−E)2(E+mec2)F(Z,E).
The Fermi function F is given by—
where N(E) is the number of electrons emitted at a certain energy E; me is mass of an electron; c is the speed of light; Q is the maximum kinetic energy of the emitted electron; Z is nuclear charge on the daughter nucleus. 63Ni has an average emitted primary electron energy of 17.2 keV and a half-life of 100 years. This is effectively a zero input power source that does not require heating. The penetrating power of these electrons is also very low and can be easily stopped by thin film thicknesses in μm, making them suitable for commercial applications. Monte-Carlo simulations reveal primary electrons on collision with air molecules produce many more secondary electrons with energies up to 300 eV which then produce majority of the ionization.
A 1-millcurie film of 63Ni (1 cm×1 cm size) can produce a number of 3.7×107 primary electrons per second that hit a nanoelectrode surface with nano-gaps. The primary electron and cascade secondary electrons can create 7.4×109 ions per second in one centimeter square area, based on experimental data and the a cross-section data obtained from
Implementations:
63Ni films of various activities from tens of uCi up to 1 mCi (1 cm×1 cm) are housed. A device is developed by the integration of electron-emitting radioactive 63Ni with CMOS-compatible devices, as well as low-cost microfabricated structures. Recently, we have used 63Ni for the realization of a self-powered ion gauge and ion pump which utilizes electrons emitted from the thin-film radioisotope to compute the pressure based on ionization current and for near-IR scintillation of xenon by radioisotope decay for wavelength calibration and analysis with Spencer's theory of electron penetration using xenon cross-sections derived from the Thomas-Fermi theory. Over the past decade, we have demonstrated the use of 63Ni for: self-reciprocating radioisotope-powered micromechanical resonators, harvesting mechanical stored energy in these resonators to generate electric power, energy harvesting with integrated betavoltaics, self-powered wireless transmission with, parallel electron lithography.
The specific technique for ionization plays an important role in the broad-band performance of the breath biosensors. Thermal ionization forms the basis of high sensitivity mass spectroscopy in which a purified and pre-concentrated sample is heated after desorption from the pre-concentration surface to produce ions. However, such ionization is power hungry due to the required heating element. Also, the degree of ionization depends on the components of the mixture and a static heating element with a preset heating mechanism may not be able to ionize all the components of the mixture. Photo-ionization with a broad-band light source is limited by the production of predominantly positively charged ions as photoelectrons are knocked out of the analyte mixture and only a small percentage of these are captured by neutral molecules to form negatively charged ions for mobility-based separation.
In contrast, ionization with a Ni-63 thin-film beta-decaying radioisotope provides the advantages of:
VOC+H
+(H2O)n↔(VOC)(H+(H2O)n−1)+H2O
VOC+O2(H2O)n↔(VOC)(O2−(H2O)n−1)+H2O
Gas Pumping Module
Following ionization of the VOCs with the zero-input power 63Ni, the ions are transferred to the ion mobility spectrometer for detection. In the disclosed system, a mechanical piezoelectric resonator is used for acoustically streaming and pumping the ionized VOCs and hydrated ion-complexes into the IMS for mobility-based sensing. Piezoelectric fans (piezofans) using bulk lead zirconate titanate (PZT) have been previously demonstrated as low-power-consumption and low-noise devices for the dissipation of accumulated heat in confined regions for macro-scale devices with applications in portable electronics such as cell phones and laptops.
Basis for Performance Targets (Calculations, Simulations, Data):
The disclosed piezofan is a PZT plate attached to a Si-cantilever beam or just a fixed-free PZT bimorph beam with electrodes patterned on it for contact. When an AC voltage is applied across the electrodes at the resonance frequency of the structure, the electric field induces mechanical strain in the beam, producing micro-motion of the tip. The structure stiffness may be given by
wherein Y is the effective Young's modulus of the structure, L is the length of the suspended beam and I is the moment of inertia about the fixed point expressed in terms of the width ‘W’ and thickness ‘T’ of the beam, given by
The resonance frequency of such a beam is given by
The oscillation of this beam to generate air flow by means of acoustic streaming has been well-studied and theoretical results have been verified in conjunction with experiments. In some implementations, the designed cantilevers with thin film PZTs have resonance frequencies varying between 300 Hz and 500 Hz. Acoustic streaming models for such structures are well-known. Disclosed is the use of such piezofans at their resonant frequencies as well as at higher modes to investigate the flow of ionized molecules into the device. Enhanced gas mixing to produce a more homogenous mixture prior to injection into the IMS is possible with higher resonance modes at the cost of higher power, as seen with macroscale fans before.
Implementations:
Surface micromachined hubs are developed for flexure mode excitation to produce acoustic streaming.
Piezofans are promising as gas pump due to their low electromagnetic noise as well as minimum space requirement. The effects of tip structure, gap, and amplitude of the piezoelectric fan have been studied. Significantly scaled-down miniature thin-film microfabricated PZT fans can be used for modulating the air flow fairly precisely.
The disclosed gas pumping module can regulate the ion-flow accurately with precise micro-motion of resonant cantilever fans. The prototypes have been developed using a novel thin-film deposition process for PZT and air-bridges for metallization contacts to actuate the fan electrodes. In the disclosed sensor, an optimal design for a ion flow regulator that can simultaneously minimize the power consumption, actuation voltage and positioning to transfer ions to the IMS device need to be investigated. With basic COMSOL simulations, various resonance frequencies of the fabricated devices of different lengths and widths for a fixed PZT thickness can be determined and a mode can be chosen that provides maximum homogeneity of the ionized mixture as well as dynamic range in flow rates over the IMS device, based on tip micro-motion. The modes of the resonator can be confirmed experimentally using an impedance analyzer to determine the frequencies for lowest motional impedance and interferometric vibrometer measurements with frequency scanning. In addition, the resonant frequency can be fine-tuned by atomic layer deposition (ALD) of platinum electrodes as well as focused ion beam (FIB) etching precisely as a fabrication process. Typical power consumptions for bulk-PZT-based piezofans are between 1-100 mW. However, for thin-film PZT piezofans <1 mW consumption is expected.
Some advantages of the disclosed technology include: (1) reduced form factor to match the CMOS scaling of breath sensing devices in the IMS; and (2) electromechanical coupling factors of microfabricated single crystal structures are usually higher than bulk devices, making the former easier to benefit from a larger dynamic range actuated modes with lower actuation voltages.
Also disclosed in this disclosure are molecular sensor devices, systems, and techniques for measuring ion-mobility to detect gases in ultra-portable packages capable of integration with mobile communication devices. The disclosed sensors includes a piezoelectric micro fan that is low power, low voltage, and sufficiently small to provide air molecule samples at rates determined by convection. In other aspects, the disclosed sensor devices include semiconductor integrated circuits having integrated in-chip acoustic communication links and nodes for use in fingerprint scanners.
In some aspects, the disclosed molecular sensor devices includes a chip-scale gas sensor using a low-voltage thin-film piezoelectric sense-actuate fan pair.
In one aspect, an ion-gas sensor device includes a substrate including an array of pillars and troughs, a microfan component including a first stack and a second stack of layers of a piezoelectric composite material formed on the pillars of the substrate and protruding over the troughs, the first stack of layers to sense the flow of ions in a gas and the second stack of layers actuate to drive the ions to a detection region of the device at a controlled flow rate, a layer of a radioactive material formed in the trough of the substrate to ionize the gas when the gas is flowed above the layer, and an array of electrode formed in the detection region to detect ion mobility of the ions of the gas.
Microscale ion-mobility measurement is an approach to sensing gases in ultra-portable packages such as the burgeoning hand-held smart-phone markets. A key component of a gas sensor is the ability to sample the air molecules at rates determined by convection rather than diffusion for faster detection time. The disclosed technology includes devices having a piezoelectric micro fan, including a micro-fan architecture that is low power (e.g., 10.6 mW/sccm), low voltage (e.g., 8.5 V/sccm), and sufficiently small (0.1 mm3/sccm). In some implementations, for example, the devices can include a multi-electrode configuration of ion-detection with less than 5V operating voltage. Exemplary implementations of the disclosed technology described herein demonstrate a pathway towards a chip-scale ion-mobility based gas detector with a process compatible with the ion-detection system, and the actuate and sense micro-fan architecture presented here.
In ion-mobility gas sensors, one desires high ion flow velocity without turbulence, to maximize the sampled air volume for a given sampling time. To prevent turbulence in micro-channels, inertial fluid forces should be weaker than viscous forces. For a Reynolds number ˜10, a flow velocity of ˜2 m/s can be tolerated for a 100 μm diameter micro-channel. These velocities can be achieved by actuators driving air directly, but typically require high voltages. Alternatively, secondary flow due to nonlinear effects such as acoustic streaming can result in high motion even with low motion in small channels due to high gradients of acoustic and ultrasonic fields. In order to achieve the high velocities, micro-scale fans and pumps have been explored for use in micro-gas analyzers, mass-specs, ion-mobility-based sensors as well as cooling via convective airflow and gas accumulation. For example, micro-valve-based multi-stage micropumps can be useful in producing large flow rates and pressure differentials for on-chip gas flow. In some examples, electrostatically actuated torsional micro-fans can also been used. These devices, however, require high-voltage operation (e.g., ˜100 V) not compatible with portable and low-power platforms. Rotary fans have scratch-drive actuators and <30Vp-p resonant operation, but are prone to frictional wearing inherent in their principle of operation.
The disclosed devices include a micro-fan design that uses a thin-film SiO2—TiPt-PZT-Pt stack as a composite unimorph actuated at resonance. For example,
Exemplary implementations of the exemplary devices were performed. The exemplary actuate-sense fan pairs with widths of 200 μm and lengths 800 μm and 1000 μm, respectively, were tested in micro-channels. Multilayer analysis for arbitrary piezoelectric-elastic layer stacks, and exemplary measured data from DC actuation from 0-6V, yielded piezoelectric coupling coefficient d31=−85.8±5 pC/N for the PZT films, less than values for bulk PZT but within expectation for multi-layer stressed thin-film devices. Resonance frequencies were measured to be at 614 Hz and 505 Hz, with peak-to-peak tip-displacement >200 um 2-Vpp, with 2.5 mW power input. A RTD element was used to measure air-velocity close to the tip of the fan.
Table 2 compares the exemplary device with previous conventional designs.
Moreover, the sense-fan signal is measured (subplot C and subplot D in
A Monolithic Ultrasonic Fingerprint Scanner
In some aspects, the disclosed technology includes a monolithic ultrasonic fingerprint scanner integrated on a CMOS die.
As personal portable electronics such as cell-phones and laptops become ubiquitous along with multiple digital identities one uses in cyberspace, the need for biometric identification has expanded well beyond the traditional areas of law enforcement or control of cleared access. In addition, the trends in the personalization of the services offered by companies and government, the demand in the security of the associated data generated by daily activities, and recent regulations on border security constitute firm signs that, the importance of biometric identification systems will continue to increase.
While biometric identification systems can use one or more types of any characteristic patterns in face, iris, or DNA, fingerprint imaging is one of the most common techniques due to its relatively optimal standing in terms of cost of equipment, time of identification (e.g., throughput), difficulty in falsifying results, ease of application to the subject, and operator-free (e.g., automatic) operation. The simplicity and relatively good performance of pen and ink method have made this approach the traditional standard to build the law enforcement databases used in criminal practice. This method, however, is gradually being replaced by more convenient and sophisticated devices utilizing optical, capacitive, and ultrasonic techniques that yield digitized data directly and minimize use of consumables and operation cost.
Ultrasonic fingerprint imaging, which is the working principle of the disclosed device, uses an initial acoustic pulse and records the magnitude and time delay of the reflected acoustic waves from discontinuities along its path.
Some exemplary advantages of the ultrasonic imaging as compared to optical and/or capacitive approaches include: (1) improved image quality, especially in case of very dry or oily fingers or in humid conditions; (2) higher performance in the presence of contaminants such as grease, ink, as sound waves can penetrate through those; (3) possibility for 3D imaging as well as temporal imaging to distinguish blood flows within the tissues, thereby enabling a higher security against detached fingers or finger skins for breaching security.
Biometric identification products can be implemented based on the above-described ultrasonic fingerprint imaging principle. Unlike the conventional method of using bulk-piezoelectric ceramics and connecting these to drive and sense electronics using hybrid packaging approaches, the exemplary devices of the disclosed technology include a monolithic approach that relies on deposition of a thin-film piezoelectric film, e.g., AlN or PZT, as ultrasonic transducers on a CMOS die. This technology can be used to realize on-chip ultrasonic communication links based on beam forming principles to achieve configurability as shown in
Thin film piezoelectric transducers have long been studied in the area of RF MEMS for their high Quality Factor and Piezoelectric coupling co-efficient (kt2). Much work has been done in this area to create CMOS compatible processes for RF resonators and filters. For example, we demonstrated the use of one of these process to utilize the Silicon wafer itself as a medium to transport mechanical ultrasonic waves
As ultrasound is a wave phenomenon, there are many properties which are directly analogous to transmission line and electromagnetic wave theory, including acoustic impedance. All materials have an acoustic impedance determined by their mechanical properties, in particular density (ρm) and elastic stiffness (c) (Z0=√{square root over (ρmc)}). This acoustic impedance determines the relationship between the stress component and the particle velocity component of the wave. As with electromagnetics, a boundary between two mediums with different impedances will reflect some of a waves energy and allow some to pass through, depending on the relationship between the two impedances (Γ=(Z2−Z1)/(Z2+Z1)). This reflection coefficient will be utilized to determine the properties of whatever may be present on the back side of the silicon wafer.
Using silicon as the substrate, a piezoelectric thin film such as Aluminum Nitride can be fabricated on the top surface of a CMOS die, with the drive and sense electronics needed for interrogation integrated with the transducer. This transducer can be pulsed so as to excite an ultrasonic wave into the silicon which will reflect off of the back surface. Depending on the material attached to the back side of the silicon, different levels of power will return to the transducer. These can be quantified to distinguish between the presence or absence of a finger or even distinguish between a set of materials. For instance, as seen in Table 3, silicon itself has an acoustic impedance of almost 20 MRayls (106 kg/m2 sec), whereas air has an impedance of about 400 Rayls (kg/m2 sec) in this case the reflection coefficient is almost 1 and nearly all the energy in the wave is reflected back toward the transducer. However if something like Teflon (Z0=3 MRayls) were on the back then the reflection coefficient would be 73% and the signal returning would be measureable lower than the air backed case. Additionally human tissue is closely matched to water and on the order of 1.5 to 3 MRayls which would be measurable.
Experimentally this phenomenon has been demonstrated, as seen in
Note that the signal is the greatest in subplot (d) when there is nothing on the backside. The signal is reduced when the polymer is attached to the back as in subplot (e). This first measurement is made when the polymer is placed on the back in a gelatinous form as in (c). As the polymer solidifies its material properties change, and therefore it presents a higher acoustic impedance and a lower reflected signal in subplot (f) when the polymer solidified. In one embodiment, the polymer used is PVDF, having an acoustic impedance (1.5-3 MRayls) on the same order as human tissue (1.5-2 MRayls), operating as a suitable phantom for modelling the presence of a finger underneath the silicon. Similarly, the oils in the skin which leave a fingerprint behind could be detected as they also have a greater acoustic impedance than air.
An important aspect to this is the acoustic impedance presented by the polymer and whether or not its thickness matters. Crystalline materials have very low acoustic losses, silicon for instance, when operated at 3 GHz, has loss on the order of 1e-4 dB/wavelength. Polymers on the other hand exhibit 15-750 dB/wavelength of loss at 3 Ghz. The speed of sound in polymers is on the order of 1000-2000 m/s, at 1 Ghz this corresponds to a wavelength of 300-700 nm.
Another technique of detection involves measuring changes in the quality factor of an acoustic resonator. Thin disk transducers, that is transducers which are much smaller than their area, have resonances associated with their thickness. The transducer by itself has a resonant mode when the thickness of the ultrasonic wave is integer multiples of the half-wavelength. If a lossy material is placed on either side of the resonator, the resonator will lose energy to that material and lower its quality factor.
In the case of a thin film bulk acoustic resonator (FBAR), the proposed process can be altered so that the transducer is released from the substrate to create the resonator. In this case the polymer can be placed on the top side of the FBAR which presents a different acoustic boundary condition for the FBAR. If we model a 1 μm AlN FBAR with varying loads,
If instead, we continue with the original structure the silicon layer would represent a mass load for the thin disk resonator. This structure is known as a highly over-tone bulk acoustic resonator (HBAR) since now the resonant mode is established due to the composite of the silicon and the transducer. The advantage of such a structure is that the intrinsic quality factor of silicon is much higher than that of AlN. Therefore, the composite structure has a larger quality factor than FBAR. The disadvantage is that there are many more resonant frequencies, so careful design is needed to lock to the correct one.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
This application is a continuation of U.S. patent application Ser. No. 14/273,540 entitled “COMPUTATION DEVICES AND ARTIFICIAL NEURONS BASED ON NANOELECTROMECHANICAL SYSTEMS”, filed on May 8, 2014, which is a continuation-in-part of International Patent Application No. PCT/US2013/050772 entitled “INTEGRATED CIRCUITS HAVING INTEGRATED ACOUSTIC COMMUNICATION LINKS,” filed on Jul. 16, 2013, which claims the benefit of U.S. Provisional Patent Application No. 61/672,214 entitled “3D SEMICONDUCTOR CHIPS HAVING INTEGRATED ULTRASONIC COMMUNICATION LINKS AND NODES”, filed on Jul. 16, 2012. In addition, U.S. patent application Ser. No. 14/273,540 claims the benefit of priority of U.S. Provisional Patent Application No. 61/821,195 entitled “COMPUTATION DEVICES AND ARTIFICIAL NEURONS BASED ON NANOELECTROMECHANICAL SYSTEMS,” filed on May 8, 2013 and U.S. Provisional Patent Application No. 61/932,234 entitled “INTEGRATED CIRCUITS BASED BIOSENSORS,” filed on Jan. 27, 2014. The entire content of the before-mentioned patent applications is incorporated by reference as part of the disclosure of this application.
This invention was made with government support under Grant No. N66001-12-C-2009, awarded by the Intelligence Advanced Research Projects Activity (IARPA) Trusted Integrated Chips (TIC) program. The government has certain rights in this invention.
| Number | Date | Country | |
|---|---|---|---|
| 61672214 | Jul 2012 | US | |
| 61821195 | May 2013 | US | |
| 61932234 | Jan 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14273540 | May 2014 | US |
| Child | 15880261 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/US2013/050772 | Jul 2013 | US |
| Child | 14273540 | US |
