Claims
- 1. A system, comprising:
a first processor; a second processor coupled to the first processor; an operating system that executes exclusively only on the first processor and not on the second processor; and a middle layer software running on the first processor and that distributes tasks to run on either or both processors.
- 2. The system of claim 1 wherein the middle layer software comprises a Java virtual machine.
- 3. The system of claim 1 further comprising a synchronization unit coupled to the first and second processors, said synchronization unit synchronizes the execution of the first and second processors.
- 4. The system of claim 3 wherein the synchronization unit causes the first processor to transition to a wait mode while the second processor executes a task.
- 6. The system of claim 4 wherein the first processor is transitioned from the wait mode to a fully operational mode by a signal being asserted by the either the first or second processor to the synchronization unit.
- 7. The system of claim 1 further comprising a shared TLB containing a plurality of entries in which virtual-to-physical address translations are stored, each entry also containing a task ID field in which a task ID associated with the corresponding translation and with a task running on the first or second processor is stored.
- 8. The system of claim 7 wherein the operating system selectively flushes some of the entries in the shared TLB based on task ID.
- 9. The system of claim 7 wherein the middle layer software selectively flushes some of the entries in the shared TLB based on task ID.
- 10. The system of claim 9 wherein the middle layer software comprises a Java virtual machine.
- 11. The system of claim 7 wherein some of the shared TLB entries are invalidated, and those entries that are invalidated have task IDs that are associated with tasks that are running or have run on only one of the first or second processors.
- 12. The system of claim 1 wherein the second processor has a programmable context and autonomously switches its own context without support from the operating system executing on the first processor.
- 13. The system of claim 1 wherein the second processor includes a programmable task ID register which contains a value indicative of the task currently running on the second processor that is written by the middle layer software running on the first processor.
- 14. A method usable in a multi-processor system, comprising:
executing an operating system on only one of a plurality of processors; and distributing tasks to each of the plurality of processors by middle layer software running on the processor on which the operating system executes.
- 15. The method of claim 14 wherein distributing tasks comprises distributing tasks by a Java virtual machine.
- 16. The method of claim 14 further comprising causing the processor on which the operating system executes to transition to a wait mode while another processor executes tasks and subsequently transitioning the processor in the wait mode to an active mode as a result of a signal being asserted by any of the plurality of processors.
- 17. The method of claim 14 wherein each task has a unique task identifier value and the method further comprises writing virtual-to-physical address translations and task identifier values associated with the task to which the translations pertain into a translation lookaside buffer that is shared between the plurality of processors.
- 18. The method of claim 17 further selecting task identifier values and invalidating entries in the translation lookaside buffer that contain the selected task identifier values and not invalidating other entries in the translation lookaside buffer.
- 19. The method of claim 14 wherein, in a processor having a context and that does not execute the operating system, autonomously switching said context without support from the operating system.
- 20. The method of claim 14 further comprising writing a task ID register by the processor executing the operating system, the task ID register contained in another processor.
Priority Claims (1)
Number |
Date |
Country |
Kind |
03291926.8 |
Jul 2003 |
EP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Application Serial No. 60/400,391 titled “JSM Protection,” filed Jul. 31, 2002, incorporated herein by reference. This application also claims priority to EPO Application No. 03291926.8, filed Jul. 30, 2003 and entitled “Concurrent Task Execution In A Multi-Processor, Single Operating System Environment,” incorporated herein by reference. This application also may contain subject matter that may relate to the following commonly assigned co-pending applications incorporated herein by reference: “System And Method To Automatically Stack And Unstack Java Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35422 (1962-05401); “Memory Management Of Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35423 (1962-05402); “Memory Management Of Local Variables Upon A Change Of Context,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35424 (1962-05403); “A Processor With A Split Stack,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35425(1962-05404); “Using IMPDEP2 For System Commands Related To Java Accelerator Hardware,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35426 (1962-05405); “Test With Immediate And Skip Processor Instruction,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35427 (1962-05406); “Test And Skip Processor Instruction Having At Least One Register Operand,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35248 (1962-05407); “Synchronizing Stack Storage,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35429 (1962-05408); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35430 (1962-05409); “Write Back Policy For Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35431 (1962-05410); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35432 (1962-05411); “Mixed Stack-Based RISC Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35433 (1962-05412); “Processor That Accommodates Multiple Instruction Sets And Multiple Decode Modes,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35434 (1962-05413); “System To Dispatch Several Instructions On Available Hardware Resources,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35444 (1962-05414); “Micro-Sequence Execution In A Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35445 (1962-05415); “Program Counter Adjustment Based On The Detection Of An Instruction Prefix,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35452 (1962-05416); “Reformat Logic To Translate Between A Virtual Address And A Compressed Physical Address,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35460 (1962-05417); “Synchronization Of Processor States,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35461 (1962-05418); “Conditional Garbage Based On Monitoring To Improve Real Time Performance,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35485 (1962-05419); “Inter-Processor Control,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35486 (1962-05420); “Cache Coherency In A Multi-Processor System,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35637 (1962-05421); and “A Multi-Processor Computing System Having A Java Stack Machine And A RISC-Based Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35710 (1962-05423).
Provisional Applications (1)
|
Number |
Date |
Country |
|
60400391 |
Jul 2002 |
US |