BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a top view of a conventional conductive shielding pattern.
FIGS. 2A through 2C are top views showing other conventional conductive shielding patterns.
FIG. 3A is a top view showing a conductive shielding pattern according to one embodiment of the present invention.
FIG. 3B is a cross-sectional view of FIG. 3A along line B-B.
FIG. 3C is an enlarged diagram of a C region of FIG. 3A.
FIG. 4 is an alternative type of FIG. 3B.
FIG. 5 is an alternative type of FIG. 3B.
FIG. 6A is a top view showing a semiconductor structure according to another embodiment of the present invention.
FIG. 6B is a cross-sectional view of FIG. 6A along line B-B.
FIG. 7 is a frequency-versus-factor Q plot diagram according to the conductive shielding structures of the present invention and two conventional conductive shielding structures.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 3A is a top view showing a conductive shielding pattern according to one embodiment of the present invention. FIG. 3B is a cross-sectional view of FIG. 3A along line B-B. FIG. 3C is an enlarged diagram of a C region of FIG. 3A.
As shown in FIG. 3A together with FIGS. 3B and 3C, in this embodiment, the conductive shielding pattern 300 is used to shield an inductor device (not shown). This conductive shielding pattern 300 is composed of alternatively arranged conductive layers 302 and diffusion regions 304. The conductive layers are made of polysilicon or metal such as copper, gold, nickel, aluminum and tungsten. The conductive layers 302 are located on the substrate 310 and the diffusion regions 304 are located in the substrate 310. The conductive layers 302 and the diffusion regions 304 are free ends. Moreover, the conductive shielding pattern 300 of this embodiment further comprises several metal lines 306 located conductive layers 302 and the diffusion regions 304 respectively and connected the conductive layers 302 to each other and connected the diffusion regions 304 to each other. The metal lines 306 can be a metal layer, which is so-called metal 1 layer in the semiconductor process technology, used to form the gate electrode, source and drain of the semiconductor device. Alternatively, the metal lines 306 can be an additional metal layer over the metal 1 layer. Furthermore, the pattern composed of the metal lines 306 and the conductive layers 302 is a free end. The pattern composed of the metal lines 306 and the diffusion regions 304 is a free end as well. In this embodiment, each conductive layer 302 is apart from each diffusion region 304 for a distance d.
FIG. 4 is an alternative type of FIG. 3B. FIG. 5 is an alternative type of FIG. 3B. As shown in FIG. 4, the arrangement of the conductive layers 402 and the diffusion regions 404 is an edge-to-edge arrangement. Alternatively, in FIG. 5, the conductive layers 502 partially overlap the diffusion regions 504 respectively.
FIG. 6A is a top view showing a semiconductor device according to another embodiment of the present invention. FIG. 6B is a cross-sectional view of FIG. 6A along line B-B.
As shown in FIG. 6A and FIG. 6B, the semiconductor structure of this embodiment comprises a substrate 600 and an inductor device 610, a conductive shielding pattern 620 and an insulating layer 630 over the substrate 600. The inductor device 610 can be, for example but not limited to, a round shape spiral inductor device as shown in FIG. 6A and FIG. 6B or a square shape spiral inductor device. The conductive shielding pattern 620 is located under the inductor device 610 and used to shield the inductor device 610. The conductive shielding pattern 620 comprises several conductive layers 622 and diffusion regions 624. The conductive layers 622 are located on the substrate 600 and the diffusion regions 624 are located in the substrate 600. The conductive layers 622 and the diffusion regions 624 are alternatively arranged and the conductive layers 622 and the diffusion regions 624 are free ends. Moreover, the insulating layer 630 is located between the conductive shielding pattern 620 and the inductor device 610. Furthermore, the arrangement of the conductive layers 622 and the diffusion regions 624 can be, for example but not limited to, an edge-to-edge arrangement or a partially overlapped arrangement.
In order to prove the efficiency of the present invention, FIG. 7 is a frequency-versus-factor Q plot diagram according to the conductive shielding structures of the present invention and two conventional conductive shielding structures. The conventional conductive shielding patterns are similar to what shown in FIG. 3 but one is single-material (i.e. poly-silicon) conductive shielding pattern, and the other is to utilize diffusion regions as the conductive shielding pattern.
As shown in FIG. 7, the factor Q of the inductor device with the use of the conductive shielding pattern according to the present invention is larger than those of the inductor devices with the uses of the convention conductive shielding patterns. Hence, the factor Q of the inductor is improved by using the conductive shielding pattern according to the present invention.
Altogether, in the conductive shielding pattern according to the present invention, since the conductive layers and the diffusion regions are alternatively arranged, the permeance interference of the substrate to the inductor device is decreased and the factor Q of the inductor device is increased. Meanwhile, no eddy current is generated by the conductive shielding pattern so that the inductance of the inductor device is maintained and the parasitic capacitance is decreased.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.
Patent Application
20080029854
