Patent Application
20170200884
Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to configurations and techniques to increase interfacial anisotropy of magnetic tunnel junctions.
Some magnetic memories, such as a spin transfer torque memory (STTM), utilize a magnetic tunnel junction (MTJ) for switching and detection of the memory's magnetic state. Thermal stability of these memories is a concern; however, current techniques to increase thermal stability in the MTJ may increase resistance in the MTJ.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. Unless explicitly indicated otherwise, the figures are not depicted in scale.
A magnetic tunnel junction may be formed from two ferromagnetic layers separated by an insulating layer, also known as a tunnel barrier. One of the two ferromagnetic layers may be a strong magnet with a fixed polarity, also known as a fixed magnetic layer. The other ferromagnetic layer may be configured to undergo a change in polarity when a spin-polarized current is applied to it, and is also known as a free magnetic layer.
The change in polarity of the free magnetic layer may act to increase or decrease the electrical resistance across the MTJ. If the polarity of the free magnetic layer is the same as (e.g., parallel to) the polarity of the fixed magnetic layer, then the MTJ may be in a low resistance state. On the other hand, if the polarity of the free magnetic layer is opposite (e.g., anti-parallel to) the polarity of the fixed magnetic layer, then the MTJ may be in a high resistance state. In such magnetic memories, the magnetic state is what may cause data to persist in the memory, and the data may be read by measuring the resistance across the MTJ. As a result, stability of the free magnetic layer to maintain polarity, absent application of a spin-polarized current, is essential for maintaining the state of the MTJ.
Regarding STTM specifically, one form of STTM includes perpendicular STTM (pSTTM). Where a traditional MTJ or non-perpendicular MTJ generates a magnetization “in plane” (with which “high” and “low” memory states are set), a perpendicular MTJ (pMTJ) generates magnetization “out of plane.” This reduces the switching current needed to switch between the high resistance state and the low resistance state. This also allows for better scaling (e.g., smaller size memory cells). Traditional MTJs are converted to pMTJs by, for example, thinning the free layer in the presence of interface magnetic anisotropy, thereby making the tunnel barrier/free layer interface more dominant in magnetic field influence (the interface promotes anisotropic out of plane magnetization).
Embodiments of the present disclosure describe configurations and techniques to increase interfacial anisotropy of magnetic tunnel junctions. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments is defined by the appended claims and their equivalents.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
The description may use perspective-based descriptions such as top/bottom, in/out, over/under, and the like. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments described herein to any particular orientation.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.
As used herein, the term “module” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a system-on-chip (SoC), a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.
Die 102 may be attached to package substrate 104 according to a variety of suitable configurations, including a flip-chip configuration, as depicted, or other configurations, such as, for example, being embedded in the package substrate 104 or being configured in a wirebonding arrangement. In the flip-chip configuration, the die 102 may be attached to a surface of the package substrate 104 via die interconnect structures 106 such as bumps, pillars, or other suitable structures that may also electrically couple die 102 with the package substrate 104.
Die 102 may include embedded memory cells (e.g., spin transfer torque random access memory (STT-RAM) 118). STT-RAM 118 may include a magnetic tunnel junction (MTJ) 128. In some embodiments, MTJ 128 may include a first cap layer 130, a buffer layer 132, ferromagnetic layers 134 and 138, a tunnel barrier 136 separating ferromagnetic layers 134 and 138, and a second cap layer 140. In embodiments, buffer layer 132 may be selected to increase thermal stability, hereinafter referred to merely as “stability,” of MTJ 128 by increasing the interfacial anisotropy of MTJ 128 when compared with embodiments without buffer layer 132. Interfacial anisotropy is a directional energy created from the interface, or contact area, between two materials. Interfacial anisotropy may be measured by the amount of energy created per area of interface (e.g., millijoules per square meter (mJ/m2)). The interfacial anisotropy between two materials varies based on the materials selected. Interfacial anisotropy is the energy responsible for converting an in-plane MTJ to an out-of-plane MTJ, or perpendicular MTJ (pMTJ). In addition, interfacial anisotropy is cumulative, so the interfacial anisotropy of an MTJ would be the sum of the individual interfacial anisotropies for each interface of the MTJ. A greater overall interfacial anisotropy of the MTJ corresponds with greater stability of polarity in the free magnetic layer.
The MTJ may couple bit line (BL) 120 to selection switch 126 (e.g., transistor), word line (WL) 122, and sense line (SL) 124. STT-RAM 118 may be read by assessing a change of resistance (e.g., tunneling magnetoresistance (TMR)) for different relative magnetizations of ferromagnetic layers 134 and 138. More specifically, MTJ resistance may be determined by the relative polarization of layers 134 and 138. When the polarization of layers 134 and 138 are opposite, or anti-parallel, the MTJ may be in a high resistance state. When the polarization of layers 134 and 138 are the same, or parallel, the MTJ may be in a low resistance state. In embodiments, layer 138 may be a fixed magnetic layer because its polarization may be fixed. As a result, ferromagnetic layer 134 may be a free magnetic layer. As discussed above, a free magnetic layer is a magnetic layer that may be configured to undergo a change in polarity by applying a driving current polarized by the fixed layer (e.g., a positive voltage applied to layer 138 rotates the magnetization direction of layer 134 opposite to that of layer 138 and negative voltage applied to layer 138 rotates the magnetization direction of layer 134 to the same direction of layer 138).
STT-RAM 118, described above, is just one example of a “beyond CMOS” technology (or “non-CMOS based” technology), which relates to devices and processes not entirely implemented with complementary metal-oxide-semiconductor (CMOS) techniques. Beyond CMOS technology may rely on spin polarization (which concerns the degree to which the spin or intrinsic angular momentum of elementary particles is aligned with a given direction) and, more generally, spintronics (a branch of electronics concerning the intrinsic spin of an electron, its associated magnetic moment, and the electron's fundamental electronic charge). Spintronics devices may concern TMR, which uses quantum-mechanical tunneling of electrons through a thin insulator to separate ferromagnetic layers, and STT, where a current of spin-polarized electrons may be used to control the magnetization direction of ferromagnetic electrodes.
Beyond CMOS devices include, for example, spintronics devices implemented in memory (e.g., 3 terminal STT-RAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (IMOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall memory, and the like.
Die 102 may represent a discrete chip made from a semiconductor material and may be, include, or be a part of a processor, memory, or ASIC in some embodiments. In some embodiments, an electrically insulative material such as, for example, molding compound or underfill material (not pictured) may partially encapsulate a portion of die 102 and/or interconnect structures 106. Die interconnect structures 106 may be configured to route electrical signals between die 102 and package substrate 104.
Package substrate 104 may include electrical routing features configured to route electrical signals to or from die 102. The electrical routing features may include, for example, traces disposed on one or more surfaces of package substrate 104 and/or internal routing features such as, for example, trenches, vias, or other interconnect structures to route electrical signals through package substrate 104. For example, in some embodiments, package substrate 104 may include electrical routing features (such as die bond pads 108) configured to receive die interconnect structures 106 and route electrical signals between die 102 and package substrate 104.
In some embodiments, the package substrate 104 is an epoxy-based laminate substrate having a core and/or build-up layers such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate 104 may include other suitable types of substrates in other embodiments including, for example, substrates formed from glass, ceramic, or semiconductor materials.
Circuit board 116 may be a printed circuit board (PCB) composed of an electrically insulative material such as an epoxy laminate. For example, circuit board 116 may include electrically insulating layers composed of materials such as, for example, polytetrafluoroethylene, phenolic cotton paper materials such as Flame Retardant 4 (FR-4), FR-1, cotton paper and epoxy materials such as CEM-1 or CEM-3, or woven glass materials that are laminated together using an epoxy resin prepreg material. Structures (not shown), for example, vias, may be formed through the electrically insulating layers to route the electrical signals of die 102 through circuit board 116. Circuit board 116 may be composed of other suitable materials in other embodiments. In some embodiments, circuit board 116 is a motherboard (e.g., motherboard 902 of
Package-level interconnects such as, for example, solder balls 112 or land-grid array (LGA) structures may be coupled to one or more lands (hereinafter “lands 110”) on package substrate 104 and one or more pads 114 on circuit board 116 to form corresponding solder joints that are configured to further route the electrical signals between package substrate 104 and circuit board 116. Other suitable techniques to physically and/or electrically couple package substrate 104 with circuit board 116 may be used in other embodiments.
First and second cap layers 202 and 212 may, in some embodiments, be composed of tantalum (Ta), as depicted. In other embodiments, first and second cap layers 202 and 212, respectively, may be composed of other material, such as, for example, hafnium (Hf), ruthenium (Ru), titanium (Ti), zirconium (Zr), molybdenum (Mo), tungsten (W), vanadium (V), chromium (Cr), niobium (Nb) and alloys of these materials. In embodiments, ferromagnetic layer 206 may be a free magnetic layer and ferromagnetic layer 210 may be a fixed magnetic layer, hereinafter referred to as free magnetic layer 206 and fixed magnetic layer 210, respectively. Free magnetic layer 206 and fixed magnetic layer 210 may be composed of a combination of cobalt (Co), iron (Fe), and boron (B). In some embodiments, CoFeB may be Fe rich, for example, the CoFeB may be composed of 20% Co, 60% Fe, and 20% B. In some embodiments, CoFeB may be Co rich, for example, the CoFeB may be composed of 60% Co, 20% Fe, and 20% B. As mentioned above, free magnetic layer 206 and fixed magnetic layer 210 may be separated by tunnel barrier 208. In some embodiments, tunnel barrier 208 may be composed of magnesium oxide (MgO), as depicted. In other embodiments, tunnel barrier 208 may be composed of other materials, such as, for example, hafnium oxide (HfO2).
Buffer layer 204 may, in some embodiments, be disposed between first cap layer 202 and free magnetic layer 206. In embodiments, buffer layer 204 may be selected, or designed, such that an interface between buffer layer 204 and first cap layer 202 has a greater interfacial anisotropy, depicted as Ki, than an interfacial anisotropy of the free magnetic layer 206 and first cap layer 202. For example, as depicted, buffer layer 204 may be composed of Co, which, as discussed further in reference to
MTJ 300 differs from MTJ 200 of
In some embodiments, first cap layer 402 may be composed of a contact sub-layer 404 and an oxide sub-layer 406. In embodiments, oxide sub-layer 406 may be composed of MgO. In such an embodiment, first buffer layer 408 may be composed of Fe, as depicted, or Co; however, as can be seen from graph 700 of
MTJ 600 differs from MTJ 500 in that sub-layers 610-618 may include buffer sub-layers 612 and 616. Buffer sub-layers 612 and 616 may be selected, or designed, such that an interface between buffer sub-layer 612 or 616 and an adjacent sub-layer 614 has a greater interfacial anisotropy, depicted as Ki3 and Ki4, than an interfacial anisotropy of the MTJ without buffer sub-layers 612 and 616. As a result, the overall interfacial anisotropy of MTJ 600 may be increased by the sum of Ki1-Ki4. In some embodiments, only a single buffer sub-layer 612 or 616 may be utilized instead of both 612 and 616 being utilized. As depicted, in some embodiments, buffer sub-layers 612 and 616 may be composed of Co and adjacent sub-layer 614 may be composed of Ta. In an alternate embodiment, as depicted in the box labeled alternate 608 embodiment, buffer sub-layers 612 and 616 may be composed of Fe and adjacent sub-layer 614 may be composed of Hf. It will be appreciated that these are merely illustrative embodiments and that any other suitable material, or combination of materials, such as, for example, those materials discussed in reference to
Starting from the left, the first material depicted is hafnium (Hf). As can be seen at bar 704 and bar 706, Hf has a positive Ki when interfacing with Fe or Co. As a result, a buffer layer of either of Fe or Co may be utilized to interface with Hf; however, an interface of Hf and Fe clearly generates a greater Ki, as depicted by bar 704.
The next material depicted is chromium (Cr). As can be seen at bar 708 and bar 710, Cr has a negative Ki when interfacing with Fe or Co. As a result, a buffer layer of either Fe or Co may not be desirable to interface with Cr where the goal is to increase overall Ki.
Moving to the right, the next material depicted is tantalum (Ta). As can be seen at bar 712, an interface of Ta and Fe has a fairly small positive Ki, while an interface with Ta and Co has a much greater positive Ki, as depicted by bar 714. As a result, a buffer layer of either Fe or Co may be utilized to interface with Ta; however, Co clearly has a bigger impact on overall Ki when interfacing with Ta than Fe does.
The next material depicted is copper (Cu). As can be seen at bar 716, an interface of Cu and Fe has a positive Ki, while an interface of Cu and Co has a much smaller positive Ki, as depicted by bar 718. As a result, a buffer layer of either Fe or Co may be utilized to interface with Cu; however, Fe clearly has a bigger impact on overall Ki when interfacing with Cu than Co does.
The next material depicted is magnesium oxide (MgO). As can be seen at bar 720 and bar 722, MgO has a positive Ki when interfacing with either of Fe or Co. As a result, a buffer layer of either Fe or Co may be utilized to interface with MgO; however, an interface of MgO and Fe clearly generates a greater Ki, as depicted by 720.
Moving farther to the right, the next material depicted is hafnium oxide (HfO2). As can be seen at bar 724 and bar 726, HfO2 has a positive Ki when interfacing with either of Fe or Co. As a result, a buffer layer of either Fe or Co may be utilized to interface with HfO2; however, an interface of HfO2 and Co clearly generates a greater Ki, as depicted by 726.
Both of the final materials, bars 728-734, involve ruthenium (Ru). As can be seen at bar 728 and bar 730, Ru has a positive Ki when interfacing with a thin (e.g., 0.4-0.5 nm) layer of either of Fe or Co. As a result, a thin buffer layer of either Fe or Co may be utilized to interface with Ru; however, an interface of Ru and a thin layer of Fe clearly generates a greater Ki, as depicted by 728. This is in contrast to the results depicted when utilizing a Ru layer in contact with a thick (e.g., >4 nm) layer of Fe or Co. As depicted by bars 732 and 734, a Ru layer when interfacing with either of thick Fe or Co has a negative Ki. As a result, a thick buffer layer of either Fe or Co may not be desirable to interface with a Ru layer where the goal is to increase overall Ki.
Each of these layers may be composed of any of the materials discussed herein or any other suitable material. In addition, the layers may be formed in any manner known in the art, such as, for example, sputter and/or vapor deposition. In some embodiments, the first magnetic layer may be a fixed magnetic layer while the second magnetic layer may be a free magnetic layer. In some embodiments, an additional buffer layer may be formed over the second magnetic layer prior to forming the cap layer at block 812. This additional buffer layer may be formed in place of, or in addition to, the buffer layer formed at block 808.
In some embodiments, additional sub-layers may be formed as part of the individual procedures. For example, to form the cap layer at block 812, an oxide sub-layer may be formed over the second magnetic layer, and a contact sub-layer may be formed over the oxide sub-layer. In some embodiments, in forming the first or second magnetic layers, a number of magnetic sub-layers may be formed that may be magnetically coupled. In these embodiments, buffer sub-layers may also be formed between the magnetic sub-layers.
Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the motherboard 902. These other components may include, but are not limited to, volatile memory (e.g., dynamic random access memory (DRAM) 908), non-volatile memory (e.g., read-only memory (ROM) 910), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 906 may enable wireless communications for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments, they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible BWA networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 906 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 906 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 906 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 906 may operate in accordance with other wireless protocols in other embodiments.
The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.
The processor 904 of the computing device 900 may include a die (e.g., die 102 of
The communication chip 906 may also include a die (e.g., die 102 of
In various implementations, the computing device 900 may be a mobile computing device, a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.
According to various embodiments, the present disclosure describes a method. Example 1 is a magnetic tunnel junction comprising: a cap layer; a tunnel barrier; a magnetic layer disposed between the cap layer and the tunnel barrier; and a buffer layer disposed between the magnetic layer and a selected one of the cap layer or the tunnel barrier, wherein an interfacial anisotropy of the buffer layer and the selected one of the cap layer or the tunnel barrier is greater than an interfacial anisotropy of the magnetic layer and the selected one of the cap layer or the tunnel barrier.
Example 2 may include the subject matter of Example 1, wherein the cap layer further comprises a contact sub-layer and an oxide sub-layer disposed between the contact sub-layer and the magnetic layer, wherein an interfacial anisotropy of the oxide sub-layer and the magnetic layer is greater than an interfacial anisotropy of the magnetic layer and the contact sub-layer.
Example 3 may include the subject matter of Example 2, wherein the oxide sub-layer comprises a conductive oxide.
Example 4 may include the subject matter of Example 1, wherein the buffer layer is a first buffer layer disposed between the magnetic layer and the cap layer, the magnetic tunnel junction further comprising: a second buffer layer disposed between the magnetic layer and the tunnel barrier, wherein an interfacial anisotropy of the second buffer layer and the tunnel barrier is greater than an interfacial anisotropy of the magnetic layer and the tunnel barrier.
Example 5 may include the subject matter of Example 1, wherein the magnetic layer is composed of a plurality of magnetic sub-layers that are magnetically coupled to form a single magnet.
Example 6 may include the subject matter of Example 5, wherein the plurality of magnetic sub-layers comprise one or more buffer sub-layers designed to increase an interfacial anisotropy of the magnetic layer.
Example 7 may include the subject matter of Example 6, wherein the plurality of magnetic sub-layers comprise a middle sub-layer disposed between a first outside magnetic sub-layer and a second outside magnetic sub-layer, wherein the middle sub-layer comprises one or more of tantalum (Ta) or hafnium (Hf), and wherein the first and second outside magnetic sub-layers comprise cobalt (Co), iron (Fe), and boron (B).
Example 8 may include the subject matter of Example 7, further comprising a buffer sub-layer disposed between the middle sub-layer and a selected one of the first or second outside magnetic sub-layers, wherein the buffer sub-layer comprises Co or Fe.
Example 9 may include the subject matter of Example 7, further comprising a first buffer sub-layer disposed between the middle sub-layer and the first outside magnetic sub-layer and a second buffer sub-layer disposed between the middle sub-layer and the second outside magnetic sub-layer, wherein the first and second buffer sub-layers comprise Co or Fe.
Example 10 may include the subject matter of Example 1, wherein the cap layer comprises tantalum (Ta) or hafnium (Hf).
Example 11 may include the subject matter of Example 1, wherein the tunnel barrier comprises magnesium oxide (MgO) or hafnium oxide (HfO2).
Example 12 may include the subject matter of Example 1, wherein the magnetic layer comprises cobalt (Co), iron (Fe), and boron (B).
Example 13 may include the subject matter of Example 1, wherein the buffer layer comprises iron (Fe) or cobalt (Co).
Example 14 may include the subject matter of Example 1, wherein the buffer layer comprises cobalt (Co) rich cobalt (Co), iron (Fe), and boron (B), CoFeB, and wherein the magnetic layer comprises Fe rich CoFeB.
Example 15 may include the subject matter of any one of Examples 1-14, wherein the magnetic layer is a free magnetic layer.
Example 16 is a method of forming a magnetic tunnel junction comprising: providing a substrate; forming a first magnetic layer over the substrate; forming a tunnel barrier over the first magnetic layer; forming a second magnetic layer over the tunnel barrier; forming a cap layer over the second magnetic layer; and forming a buffer layer, the buffer layer being disposed between the second magnetic layer and a selected one of the cap layer or the tunnel barrier, wherein an interfacial anisotropy of the buffer layer and the selected one of the cap layer or the tunnel barrier is greater than an interfacial anisotropy of the second magnetic layer and the selected one of the cap layer or the tunnel barrier.
Example 17 may include the subject matter of Example 16, wherein forming the cap layer further comprises: forming an oxide sub-layer over the second magnetic layer; and forming a contact sub-layer over the oxide sub-layer.
Example 18 may include the subject matter of Example 17, wherein the oxide sub-layer comprises a conductive oxide.
Example 19 may include the subject matter of Example 16, wherein the buffer layer is a first buffer layer disposed between the second magnetic layer and the cap layer, the method further comprising: forming a second buffer layer, wherein the second buffer layer is disposed between the second magnetic layer and the tunnel barrier, wherein an interfacial anisotropy of the second buffer layer and the tunnel barrier is greater than an interfacial anisotropy of the second magnetic layer and the tunnel barrier.
Example 20 may include the subject matter of Example 16, wherein forming the second magnetic layer further comprises forming a plurality of magnetic sub-layers that are magnetically coupled.
Example 21 may include the subject matter of Example 20, wherein forming the second magnetic layer further comprises forming a buffer sub-layer disposed between two magnetic sub-layers of the plurality of magnetic sub-layers, wherein the buffer sub-layer is designed to increase an interfacial anisotropy of the second magnetic layer.
Example 22 may include the subject matter of Example 20, wherein the plurality of magnetic sub-layers comprise a middle sub-layer formed between a first outside magnetic sub-layer and a second outside magnetic sub-layer, wherein the middle sub-layer comprises one or more of tantalum (Ta) or hafnium (Hf), and wherein the first and second outside magnetic sub-layers comprise cobalt (Co), iron (Fe), and boron (B).
Example 23 may include the subject matter of Example 22, further comprising forming a buffer sub-layer disposed between the middle sub-layer and a selected one of the first or second outside magnetic sub-layers, wherein the buffer sub-layer comprises Co or Fe.
Example 24 may include the subject matter of Example 22, further comprising forming a first buffer sub-layer between the middle sub-layer and the first outside magnetic sub-layer and forming a second buffer sub-layer between the middle sub-layer and the second outside magnetic sub-layer, wherein the first and second buffer sub-layers comprise Co or Fe.
Example 25 may include the subject matter of Example 16, wherein the cap layer comprises tantalum (Ta) or hafnium (Hf).
Example 26 may include the subject matter of Example 16, wherein the tunnel barrier comprises magnesium oxide (MgO) or hafnium oxide (HfO2).
Example 27 may include the subject matter of Example 16, wherein the first magnetic layer and the second magnetic layer comprise cobalt (Co), iron (Fe), and boron (B).
Example 28 may include the subject matter of Example 16, wherein the buffer layer comprises iron (Fe) or cobalt (Co).
Example 29 may include the subject matter of Example 15, wherein the buffer layer comprises cobalt (Co) rich cobalt (Co), iron (Fe), and boron (B), CoFeB, and wherein the magnetic layer comprises Fe rich CoFeB.
Example 30 may include the subject matter of Example 15-27, wherein the second magnetic layer is a free magnetic layer and the first magnetic layer is a fixed magnetic layer.
Example 31 is a spin transfer torque memory (STTM) comprising: a bit line; a sense line; a magnetic tunnel junction coupling the bit line with the sense line, wherein the magnetic tunnel junction comprises: a cap layer, a tunnel barrier, and a magnetic layer disposed between the cap layer and the tunnel barrier; and a buffer layer disposed between the magnetic layer and a selected one of the cap layer or the tunnel barrier, wherein an interfacial anisotropy of the buffer layer and the selected one of the cap layer or the tunnel barrier is greater than an interfacial anisotropy of the magnetic layer and the selected one of the cap layer or the tunnel barrier.
Example 32 may include the subject matter of Example 31, wherein the cap layer further comprises a contact sub-layer and an oxide sub-layer disposed between the contact sub-layer and the magnetic layer, wherein an interfacial anisotropy of the oxide sub-layer and the magnetic layer is greater than an interfacial anisotropy of the magnetic layer and the contact sub-layer.
Example 33 may include the subject matter of Example 32, wherein the oxide sub-layer comprises a conductive oxide.
Example 34 may include the subject matter of Example 31, wherein the buffer layer is a first buffer layer disposed between the magnetic layer and the cap layer, the magnetic tunnel junction further comprising: a second buffer layer disposed between the magnetic layer and the tunnel barrier, wherein an interfacial anisotropy of the second buffer layer and the tunnel barrier is greater than an interfacial anisotropy of the magnetic layer and the tunnel barrier.
Example 35 may include the subject matter of Example 31, wherein the magnetic layer is composed of a plurality of magnetic sub-layers that are magnetically coupled to form a single magnet.
Example 36 may include the subject matter of Example 35, wherein the plurality of magnetic sub-layers comprise one or more buffer sub-layers designed to increase an interfacial anisotropy of the magnetic layer.
Example 37 may include the subject matter of Example 36, wherein the plurality of magnetic sub-layers comprise a middle sub-layer disposed between a first outside magnetic sub-layer and a second outside magnetic sub-layer, wherein the middle sub-layer comprises one or more of tantalum (Ta) or hafnium (Hf), and wherein the first and second outside magnetic sub-layers comprise cobalt (Co), iron (Fe), and boron (B).
Example 38 may include the subject matter of Example 37, further comprising a buffer sub-layer disposed between the middle sub-layer and a selected one of the first or second outside magnetic sub-layers, wherein the buffer sub-layer comprises Co or Fe.
Example 39 may include the subject matter of Example 37, further comprising a first buffer sub-layer disposed between the middle sub-layer and the first outside magnetic sub-layer and a second buffer sub-layer disposed between the middle sub-layer and the second outside magnetic sub-layer, wherein the first and second buffer sub-layers comprise Co or Fe.
Example 40 may include the subject matter of Example 31, wherein the cap layer comprises tantalum (Ta) or hafnium (Hf).
Example 41 may include the subject matter of Example 31, wherein the tunnel barrier comprises magnesium oxide (MgO) or hafnium oxide (HfO2).
Example 42 may include the subject matter of Example 31, wherein the magnetic layer comprises cobalt (Co), iron (Fe), and boron (B).
Example 43 may include the subject matter of Example 31, wherein the buffer layer comprises iron (Fe) or cobalt (Co).
Example 44 may include the subject matter of Example 29, wherein the buffer layer comprises cobalt (Co) rich cobalt (Co), iron (Fe), and boron (B), CoFeB, and wherein the magnetic layer comprises Fe rich CoFeB.
Example 45 may include the subject matter of Example 31-43, wherein the magnetic layer is a free magnetic layer.
Example 46 may include the subject matter of Example 45, wherein the STTM is a perpendicular STTM wherein the magnetic layer has an out of plane polarization (pSTTM).
Example 47 may include the subject matter of Example 46, wherein the STTM is part of a random access memory (RAM) module.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2014/049794 | 8/5/2014 | WO | 00 |
