Patent Application
20080096364
In
The present invention addresses and solves various reliability problems attendant upon conventional semiconductor fabrication techniques. These problems arise as semiconductor memory device dimensions continue to shrink, making it increasingly more difficult to deposit an ILD0 to effectively fill high aspect ratio gaps between closely spaced apart gate electrode structures, particularly wherein the gate electrode stacks comprise spacers with undercut regions. The inability to effectively fill such high aspect ratio gaps leads to various reliability problems and reduced yields.
The present invention addresses and solves that problem, and provides methodology enabling the fabrication of gate electrode structures with nickel silicide layers, by strategically depositing an extremely thin conformal layer of silicon oxide or silicon nitride as a liner in the gap and into the undercut portions. The silicon oxide liner can be deposited by various techniques, such as atomic layer deposition, pulsed deposition or subatmospheric chemical vapor deposition (SACVD) employing tetraethyl orthosilicate (TEOS) and ozone (O3). The conformal silicon nitride layer can be deposited by atomic layer deposition, pulsed deposition or plasma enhanced chemical vapor deposition (PECVD).
Embodiments of the present invention include depositing the conformal silicon nitride or silicon oxide liner at a thickness of about 50 Å to about 500 Å, as at a thickness of 10 to 100 atomic layers, e.g. 50 atomic layers, with thickness sufficient to seal off the undercut region by the conformally deposited first layer deposition.
Gap filling is then implemented by depositing one or more layers of dielectric material. For example, gap filling can be effected by depositing a layer of BPSG followed by rapid thermal annealing at a temperature of about 720° C. to about 840° C. However, when the transistors contain nickel silicide layers, the deposition of the dielectric liner and gap filling are implemented at a temperature less than about 430° C. Accordingly, in applying the inventive methodology to gap filling between transistors having an upper nickel silicide layer, it is desirable to deposit P-HDP oxide without any annealing. Gap filling with P-HDP oxide can be implemented at a temperature below 430° C., while deposition of the conformal liner can be implemented at a temperature of about 150° C. to about 350° C. Agglomeration of nickel silicide is prevented by maintaining the temperature of ILD0 below 430° C. during formation.
The inventive sequence of initially depositing a conformal liner, as by atomic layer deposition, advantageously enables deposition of the gap fill dielectric, such as an HDP oxide, at a higher etch/deposition rate, because the conformal liner provides protection against plasma damage and/or clipping the structure. In accordance with embodiments of the present invention, gap filling after conformal liner deposition can be conducted at a high bias power to achieve a sputter to deposition ratio of up to or about 0.4 where the sputter to deposition ratio is calculated by measuring the deposition rate of a process and then measuring the sputter rate of the process after removing the silicon precursor as given by the following equation: sputter to deposition ratio=sputter rate/(sputter rate+deposition rate).
Mirrorbit technology is fundamentally different and more advanced than conventional floating gate technology, thereby enabling innovative and cost-effective advancements. A mirrorbit cell doubles the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell, typically within the nitride layer of the ONO stack of the gate dielectric layer separating the gate from the substrate. Each bit within a cell serves as a binary unit of data, e.g., either 1 or 0, mapped directly to the memory array. Reading or programming one side of a memory cell occurs independently of whatever data is stored on the opposite side of the cell. Consequently, mirrorbit technology delivers exceptional read and write performance for wireless and embedded markets.
An embodiment of the present invention comprising a flash memory mirrorbit device is schematically illustrated in
With continued reference to
Subsequently, as illustrated in
The present invention provides methodology enabling the fabrication of various types of semiconductor devices, e.g., semiconductor memory devices, particularly high speed flash memory devices, such as mirrorbit devices, exhibiting improved reliability at high manufacturing throughout and at a reduced cost. Semiconductor memory devices produced in accordance with the present invention enjoy industrial applicability in various commercial electronic devices, such as computers, mobile phones, cellular handsets, smartphones, set-top boxes, DVD players and recorders, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras.
In the preceding detailed description, the present invention is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present invention, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not restrictive. It is understood that the present invention is capable of using various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.
