Patent Application
20100127344
Integrated circuits, comprised of numerous circuit elements, are typically fabricated in layers on the surface of a semiconductor wafer. Many fabrication processes are repeated numerous times, constructing layer after layer until fabrication is complete. Metal layers (which typically increase in number as device complexity increases) include patterns of conductive material that are insulated from one another vertically by alternating layers of insulating material. Vertical, conductive tunnels called “vias” typically pass through insulating layers to form conductive pathways between adjacent conductive patterns.
Periodically, an electrical malfunction or design flaw is found when an integrated circuit is electrically tested. Implementing a design change can be an expensive process. Typically, among other tasks, a circuit designer may have to produce new schematics, a vendor may need to supply new masks or other fabrication supplies, and wafer fab personnel may need to implement new process flows on various equipment sets. Rather than commencing a lengthy and costly redesign process only to have the new design fail in operation, it is often preferable to modify and test a physical sample of the integrated circuit prior to formalizing the modified design.
Integrated circuit failure analysis often involves the use of several different types of equipment, or tools. One of the most versatile failure analysis tools is the focused ion beam (“FIB”) apparatus, which can facilitate device modification. The FIB is a tool including one or more ion columns for generating ion beams. In general, the FIB is used for performing integrated circuit repair, editing, cross-sectioning, modifications to aid microprobing of the integrated circuit, and other common failure analysis applications. As an aside, it is noted that a device may need to be preprocessed before being operated on by the FIB tool. For example, a packaged device may need to be decapsulated, or “decapped,” and an etching or grinding process for removing the encapsulant surrounding the die may need to be performed prior to operations by the FIB tool.
A FIB system generates an ion beam from a liquid metal ion source-typically gallium. Positively charged gallium ions (“Ga+”) are drawn off a field-emitter point source and accelerated by the application of a large potential, generally in the 30-50 kilovolt (kV) range, though in some systems the potential can be as low as 5 kV. With the aid of electrostatic lenses, the emission is focused into a beam typically having a sub-micron diameter. The ion beam can be used to mill through a sample integrated circuit, as may be required in failure analysis. The sample is usually positioned inside a vacuum chamber.
Typically, secondary electrons, secondary ions (i+ or i−), and neutral molecules and atoms are ejected from the sample surface when the ion beam impacts the sample. The charged particles are drawn toward an electrically-biased grid and collected by a detector generally positioned at an angle from the ion beam. The signal from the ejected particles may be amplified and displayed to provide a real-time image of the area of interest.
While the ion beam itself typically has a sputtering effect on the sample materials, there is often a need to add gases to assist in chemically removing material, thereby enhancing material removal process. Gas-assisted etching is a common feature in modern FIBs. An optional gas injection column delivers a localized gas to the area to be milled. This gas can interact with the primary ion beam to provide selective gas-assisted chemical etching. Alternatively, the primary ion beam can be used to decompose the gas to provide selective deposition of conductive or insulating materials on the sample.
Semiconductor device modification can be facilitated by the FIB by directing the ion beam at a localized area of the modification to be performed. The ion beam removes material in the local area, milling through the various layers. When the layer of interest is reached, circuit edits can be performed by depositing a new metal line or other material in a desired location to establish a connection, or by cutting through an existing conductive line to sever a connection.
Unfortunately, integrated circuit editing by application of a FIB, is not without its difficulties. A typical integrated circuit consists of alternating layers of conducting material and insulating dielectrics, with many layers containing patterned areas of both. Creating a reliable FIB connection to a particular integrated circuit internal node on a selected layer can be problematic. For example, imprecise endpoint detection, which can create either opens or shorts in the circuits, is one of several problems that can result in FIB edit failure. Accordingly, a reliable method of using a FIB to provide a connection to an integrated circuit internal node is desirable
Various apparatus and methods for providing a reliable connection to an internal node from the backside of an integrated circuit using a focused ion beam (“FIB”) are disclosed herein. In accordance with at least some embodiments, an integrated circuit includes an isolation region, an active region, a first contact, and a metal layer. The isolation region separates adjacent integrated circuit devices. The first contact is disposed between the isolation region and the metal layer. The first contact is electrically connected to the active region.
In accordance with at least some other embodiments, a method includes milling a via from an outer surface of an integrated circuit to a contact disposed above an isolation region of the integrated circuit. The contact is electrically connected to an active region of the integrated circuit. The via conducts a signal provided by the active region.
In accordance with yet other embodiments, a semiconductor device includes a first contact disposed over a dummy structure. The dummy structure is disposed over a shallow trench isolation (“STI”) region.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . . ” The term “integrated circuit” refers to a set of electronic components and their interconnections (internal electrical circuit elements, collectively) that are patterned on the surface of a microchip. The term “semiconductor device” refers generically to an integrated circuit (“IC”) or portion thereof, which may be integral to a semiconductor wafer, singulated from a wafer, or packaged for use on a circuit board. Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The phrase “directly coupled” is intended to mean a direct physical and/or electrical connection with no electrical devices connected interstitially between the two coupled devices. To the extent that any term is not specially defined in this specification, the intent is that the term is to be given its plain and ordinary meaning.
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
Disclosed herein are apparatus and methods for creating a reliable connection to an internal node of an integrated circuit using, for example, a focused ion beam (“FIB”).
Gate structure 110 can be, for example, the gate of a metal oxide semiconductor field effect transistor (“MOSFET”). The dummy structure 106 is generally formed of the same material as gate structure 110. In some embodiments, structures 106/110 can comprise polysilicon or metal, but are not limited to any particular material. For purposes of the present disclosure, dummy structure 110 can be referred to as a “dummy poly,” and gate structure 100 can be referred to as a “poly.” Generally, in integrated circuits, a dummy poly structure provides no function related to the device and is not connected to a voltage or current source. In embodiments of the present disclosure, however, the dummy poly 106 is disposed between the STI 104 and the contact 108. Generally, there is ample space around the active region 116 to add the contact 108 between a metal layer 112 and the STI 104 without increasing the size of the integrated circuit 100. The active region 116, can comprise, for example, the source or drain of a MOSFET, though embodiments do not limit the active region to any particular structure or device. In embodiments of the present disclosure, any voltage or current source present on the integrated circuit 100 can serve as the active region 116.
The contact 108 electrically connects the dummy poly 106 to the metal layer 112. In general, a contact provides a vertical conductive path that connects a device (e.g., the source, drain, or gate of MOSFET) to a conductive network (e.g., a metal layer). A contact, for example the contact 108, may be composed of tungsten, or any other suitable material, for example, copper, aluminum, titanium, or an alloy. The metal layer 112 interconnects various active and passive devices of the integrated circuit 100. The metal layer 112 may be formed of any suitable metal, for example, copper or aluminum.
As shown in
As a matter of convenience the STI 104 underlying dummy poly 106 and contact 108 is shown adjacent to active region 116, however, embodiments of the present disclosure do not require such an arrangement. Dummy poly 106 and contact 108 can be formed on any isolation structure connectable to contact 114 by metal layer 112 or any combination of metal layers and inter-layer vias.
The structure comprising the contact 108 and dummy poly 106 over the STI 104 allows the FIB milled via 102 to make a reliable connection with the active region 116 from the backside of the integrated circuit 100. As used herein, the “backside” of the integrated circuit 100 refers to the side of the die wherein no semiconductor devices are constructed. The contact 108 and dummy poly 106 over the STI 104 allow a hole to be milled from the backside of the integrated circuit 100 through the substrate 120, the STI 104, and the dummy poly 106 into the contact 108. The hole milled by the FIB is filled with a conductor (e.g., tungsten) to form the via 102. The via 102 is thus electrically connected to the active region 116 through contacts 108 and 114, and metal interconnect 112.
By connecting the via 102 to the contact 108 over the dummy poly 106, embodiments of the present disclosure avoid the difficulties inherent in attempting to connect the via 102 directly to the metal layer 112.
In
Via 304, of
Via 308, of
Embodiments of the present disclosure avoid these difficulties by providing a structure allowing reliable FIB connections from the integrated circuit 100 backside. Furthermore, by allowing reliable connections to the first metal layer 112 from the backside of the integrated circuit 100, embodiments avoid having to route vias across any number of intervening metal layers, as may occur when milling from the top of the die.
The metal of the contact 108 provides margin against over milling not found in other integrated circuits. Thus, the via 102 need not be milled as precisely as required in an embodiment requiring connection of the via 102 to the metal layer 112. Slight over milling of the via 102 into the contact 108 neither causes shorts to adjacent metal layers, nor disrupts contact integrity.
Each of the structures described above, including the STI 104, the dummy poly 106, the contact 108, the metal layer 112, etc. can be created using conventional integrated circuit fabrication methods and materials.
In at least some embodiments, in block 412, a dielectric is deposited in the hole milled by the FIB. The dielectric insulates the structures through which the hole was drilled from the conductor to be deposited. In such embodiments, a second hole is milled, in block 414, through the insulator to the contact. In block 416, the hole to the contact is filled with a conductor to form a via between the contact and the backside of the integrated circuit 100. Thus, a reliable connection is formed between the active region 116 and the backside of the integrated circuit.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
