(1) Technical Field
This invention generally relates to electronic devices, and more specifically to field effect transistor (PET) devices.
(2) Background
In the structure of certain types of FETs, particularly silicon-on-insulator (SOI) based complementary metal oxide semiconductor (CMOS) devices, a parasitic back channel FET exists. The structure of the parasitic back channel FET is formed by the Source, substrate 100, BOX layer 102, and Drain. The substrate 100 acts as the gate for the parasitic back channel FET.
An unwanted side effect of the parasitic back channel FET is that it can be strongly influenced by electrical fields that are created by back channel charge present at or near the interface 120 of the substrate 100 and the BOX layer 102, as well as by trapped charge within the BOX layer 102. The sources of such charge can be many, but are mainly due to the manufacturing process related to the construction of the substrate, construction of the FET devices themselves, or charging effects related to exposure of the FET devices to energetic irradiation such as high energy plasmas, x-rays, gamma rays, or cosmic radiation.
In order to mitigate the effects of such parasitic back channel FETs, typically “front-side” channel ion implantation techniques are used to control the electrical characteristics of the interface 120 of the substrate 100 and the BOX layer 102, particularly for SOI CMOS devices. This technique requires implanting ions into the active device layer 104 near the interface between the active device layer 104 and the BOX layer 102 before formation of the Gate structure 106. While economical and very compatible with standard fabrication processes, this technique has very severe limitations due to the inherent nature of ion species distribution characteristics when implanting through the entire active device layer 104 (which, as noted above, is typically a thin layer of silicon). This technique also has the inherent undesirable effect of altering the front-side interface characteristics as well as those of the “backside” interface 120, thus affecting the performance characteristics of the principal FET. Additionally, this technique limits the range of ion species available for implantation due to physical size of the implantation species or diffusion and activation characteristics. Another drawback of this technique is that physically large tons can impart severe mechanical damage in critical regions of the active device layer 104, which can degrade the overall electrical performance of the active FET device.
Accordingly, there is a need for a method and device structure that mitigate the effects of parasitic back channel FETs within FET devices without the drawbacks of conventional ion implantation. The present invention provides such a method and device structure.
U.S. patent application Ser. No. 13/528,825 (Publication No. 20130154049A1, entitled “Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology”, filed Jun. 20, 2012 and assigned to the assignee of the present invention), describes a layer transfer technology in which an integrated circuit (IC) device is fabricated in two or more parts that are then bonded together. In addition, other examples of layer transfer technologies are known in the art.
The present invention is based in part on the insight that such layer transfer technologies, when used in the manufacture of IC devices (particularly FETs based on SOI substrates), makes the insulator/active device layer interface easily accessible at an early stage of the IC wafer construction to perform ion implantation. Thus, in the manufacture of IC wafers utilizing layer transfer techniques, it is not necessary to implant through the thin active device layer utilized to manufacture the principal FET device in order to control the back channel interface, because there is a point in the various manufacturing processes before the actual bonding process where all of the interfaces are accessible for implantation.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
U.S. patent application Ser. No. 13/528,825 (Publication No. 20130154049A1, entitled “Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology”, filed Jun. 20, 2012 and assigned to the assignee of the present invention), describes a layer transfer technology in which an integrated circuit (IC) device is fabricated in two or more parts that are then bonded together. In addition, other examples of layer transfer technologies are known in the art.
The present invention is based in part on the insight that such layer transfer technologies, when used in the manufacture of IC devices (particularly FETs based on SOI substrates), makes the insulator/active device layer interface easily accessible at an early stage of the IC water construction to perform ion implantation. Thus, in the manufacture of IC wafers utilizing layer transfer techniques, it is not necessary to implant through the active device layer utilized to manufacture the principal FET device in order to control the back channel interface, because there is a point in the various manufacturing processes before the actual bonding process where all of the interfaces are accessible for implantation.
Since layer transfer technology allows a complete device structure to be fabricated in two parts, process steps can be performed on “outer” layers or exposed surfaces of such layers of either or both parts before they are bonded together.
Once the desired implantation is performed, the remaining conventional layer transfer technology manufacturing processes can be executed to complete the formation of the final fully bonded wafer, as shown in
As is the case with the configuration state shown in
As another example,
As is the ease with the configuration state shown in the above embodiments, in the configuration state shown in
As yet another example,
Subsequently, as shown in
At this point, implantation of selected materials may be made into the exposed surface 612 of the insulator layer 604, as described for the embodiments disclosed above. Again, such implantation does not require implanting through the active device layer 606.
Thereafter, as shown in
It should be appreciated that other layers may be formed on either the donor substrate or the base substrate before or after any of the layers shown in
Without adversely affecting the structure or characteristics of a principal FET, the present invention enables modification of the electrical characteristics of an associated parasitic FET by either implanting dopant material at or within a desired interface (for example, by ion implantation or diffusion), or by implantation of selected ion species to impart mechanical damage at or within that interface that will change the electrical characteristics of the parasitic device through modification of the atomic bond structure of the interfacial layers; examples of such species include silicon, argon, nitrogen, and oxygen. In particular, the invention allows selection of a broad range of implantation species and desired implantation depths, and a more localized control of ion implantation that can be achieved without adversely affecting the front-side interface characteristics or damaging the active device layer of the principal FET. By way of example, implantations using the present invention can be used to modulate or improve device threshold voltage, breakdown voltage, carrier lifetimes, surface state, radiation hardness, etc. The invention can be practiced using standard IC fabrication and processing tools and processes.
Another aspect of the invention includes a method for control of FET back-channel interface characteristics during fabrication of an integrated circuit using a layer transfer process, the integrated circuit having at least an active device layer, including the step of implanting selected material at or within a FET back channel interface of the integrated circuit to control electrical characteristics of such interface without implanting such material through the active device layer.
Yet another aspect of the invention includes a method for control of FET back-channel interface characteristics of an integrated circuit, including the acts of:
Forming a donor substrate for an integrated circuit; forming at least one layer on the donor substrate, including an active device layer, the active device layer having a front side interface facing towards the donor substrate and a backside interlace facing away from the donor substrate; forming a base substrate for an integrated circuit; forming at least one layer on the base substrate, including an insulating layer, the insulating layer having a front side interface facing away from the base substrate and a backside interface facing towards the base substrate; implanting selected material at or within at least one of the backside interface of the active device layer or the front side interface of the insulating layer to control electrical characteristics of the implanted interface; bonding the backside interface of the active device layer to the front side interface of the insulating layer; and removing at least the donor substrate from all layers.
Still another aspect of the invention includes a method for control of FET back-channel interface characteristics of an integrated circuit, including the acts of:
Forming a donor substrate for an integrated circuit; forming at least one layer on the donor substrate, including an active device layer, the active device layer having a front side interface facing towards the donor substrate and a backside interlace facing away from the donor substrate; forming at least one layer on the backside interface of the active device layer, including an insulating layer having a front side interface facing towards the donor substrate and a backside interface facing away from the donor substrate; forming a base substrate for an integrated circuit, the base substrate having an exposed bonding interface; implanting selected material at or within at least one of the backside interlace of the insulating layer or the exposed bonding interface of the base substrate to control electrical characteristics of the implanted interface; bonding the backside interface of the insulating layer to the exposed bonding interface of the base substrate; and removing at least the donor substrate from all layers.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims.