Claims
- 1. A test socket for a chip scale packaged semiconductor die using a ball grid array interface comprising:
a vertical compression socket comprising a base and a retaining element activating frame wherein the retaining element activating frame is configured and positioned such that downward vertical movement of the retaining element activating frame causes at least one retaining element within the vertical compression socket to move rotationally away from the base to an open position, and wherein upward movement of the retaining element activating frame causes the at least one retaining element to move rotationally towards the base to a closed position; and a die contact insert disposed upon said die contact insert support comprising:
a semiconductor substrate; a plurality of electrical connections configured to be removably electrically coupled with an array of balls from a chip scale packaged semiconductor die; and a conductive element electrically coupled with and extending from each of the plurality of electrical connections, each conductive element being configured for electrical communication with external circuitry.
- 2. The test socket of claim 1, wherein the vertical compression socket includes at least one biasing member disposed between the at least one retaining element and the base.
- 3. The test socket of claim 3, wherein the at least one biasing member is substantially in a state of tension while the at least one retaining element is in the closed position.
- 4. The test socket of claim 2, wherein the vertical compression socket includes at least one other biasing member disposed between the retaining element activating frame and the base.
- 5. The test socket of claim 4, wherein the at least one biasing member is continually in substantial tension and wherein the at least one other biasing member is in compression when the at least one retaining element is in the open position.
- 6. The test socket of claim 1, wherein the die contact insert is removable from the base and replaceable by another die contact insert.
- 7. The test socket of claim 6, wherein the plurality of electrical connections includes a plurality of wells formed in a top surface of the semiconductor substrate.
- 8. The test socket of claim 7, wherein each of the plurality of wells is configured to receive a corresponding one of the array of balls of the chip scale packaged semiconductor die.
- 9. The test socket of claim 8, wherein the plurality of electrical connections includes a conductive lining in each of the plurality of wells.
- 10. The test socket of claim 9, wherein at least one of the plurality of wells exhibits a trapezoidal cross section.
- 11. The test socket of claim 9, wherein the at least one retaining element includes at least one tong configured and oriented to retain the semiconductor die by an edge thereof.
- 12. The test socket of claim 11, wherein the at least one tong includes at least two tongs.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No. 09/941,749, filed Aug. 29, 2001, pending, which is a divisional of application Ser. No. 09/234,593, filed Jan. 21, 1999, now U.S. Pat. No. 6,369,595, issued Apr. 9, 2002.
Divisions (1)
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Number |
Date |
Country |
Parent |
09234593 |
Jan 1999 |
US |
Child |
09941749 |
Aug 2001 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09941749 |
Aug 2001 |
US |
Child |
10228549 |
Aug 2002 |
US |