This disclosure relates generally to a Semiconductor-On-Insulator (SOI) device, and more specifically to a deep trench isolation and substrate connection on SOI and methods for manufacturing the same.
Deep trench structures in SOI devices have been used to provide high voltage isolation and to make electrical contact to a substrate of the SOI. In some examples, the same trench has been used for both high voltage isolation and for making contact to the substrate. A deep trench relies upon a sidewall dielectric to provide high voltage isolation between adjacent circuit blocks.
Increasing a thickness of the dielectric will improve voltage isolation but at the expense of a narrower conductive plug or a wider trench. Reducing the width of the plug will undesirably increase the resistance of the substrate connection. Alternatively, increasing the width of the trench increases die size area as well as a level of defects due to dislocation faults introduced during formation of the trench.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Embodiments described herein provide for independently optimizing a low resistance contact to a substrate or other buried layer, while providing for high voltage isolation. Two separate trenches are formed with different widths with a minimal impact to fabrication process complexity. A wide trench is formed to permit a low resistance contact, while a narrow trench is formed for high voltage isolation and in some embodiments, a contact to a buried layer or well.
The first trench 12 has a first width 22, a first depth 24, a first bottom surface 26 and a first sidewall 28. The second trench 16 has a second width 32, a second depth 34, a second bottom surface 36 and a second sidewall 38. A Shallow Trench Isolation (STI) layer 40 is formed on a top epitaxial surface 42. A Nitride layer 44 is formed on top of the STI 40. A High Density Plasma (HDP) hardmask is formed on top of the Nitride layer 44. An HDP hardmask is a silicon oxide film formed in a high density plasma. It should be understood that references to HDP throughout this disclosure can be replaced with a silicon oxide (or dioxide) film formed with Chemical Vapor Deposition (CVD), to form alternate embodiments. The Nitride layer 44 and the HDP hardmask are used to facilitate the formation of the trenches 12 and 16.
A Buried Oxide (BOX) layer 50 is located between a bottom epitaxial surface 52 and the substrate 54. In the example embodiment 10, the first trench 12 and the second trench 16 are each formed with a timed etch so that the first bottom surface 26 of the first trench 12, and the second bottom surface 36 of the second trench 16 both contact the BOX 50 layer. Hence, the first depth 24 is equal to the second depth 34, within manufacturing tolerances. In the various embodiments described herein, the epitaxial layer 14 is shown above the BOX layer 50 for ease of illustration. More specifically, in various embodiments the silicon closest to the BOX layer 50 is formed from a pulled crystal and is topped-up with epitaxial silicon.
Turning now to
Traditionally, the formation of a contact to a buried conductive layer in a semiconductor device has required a high energy implant. The use of high energy implants requires a limited dosage level of implanted species, thereby undesirably increasing contact resistance to the buried conductive layer. In the following embodiments, the high energy implant resist mask is replaced with an etch mask to create a low resistance doped polysilicon connection to a buried layer or well. The advantages of a low resistance substrate contact and high voltage isolation are maintained. It should be understood that in other embodiments, one or more of the advantages of a low resistance substrate connection, a high voltage isolation and a buried layer (or well) connection are realized. In some embodiments, the trench used for contacting the buried layer (or well) is a different width than the first trench 12 or the second trench 16.
In some embodiments, the formation of the second trench 16 occurs by etching through the STI layer 40. In other embodiments, the formation of the second trench 16 occurs by etching through only a silicon (or epitaxial) layer. However, when etching the trench solely through silicon, it is possible for the second trench 16 not to be etched down to the BOX layer 50, depending upon the width of the second trench 16.
The example embodiment 100 of
In one embodiment, a subsequent step is performed on the example embodiment 88 to remove the nitride layer 44 using etching, thereby leaving a low resistance substrate contact in the first trench 12 and a contact to the buried conductive layer 102 in the second trench 16.
Similar to the second embodiment described in
The example embodiment 130 of
As will be appreciated, embodiments as disclosed include at least the following. In one embodiment, an apparatus comprises a first trench formed in a semiconductor layer, the first trench comprising a first width and a first depth. A second trench is formed in the semiconductor layer, the second trench comprising a second width and a second depth, wherein the first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate, the buried oxide layer contacting a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extending to the substrate through an opening formed on the first bottom surface.
Alternative embodiments of the apparatus include one of the following features, or any combination thereof. The first depth of the first trench is equal to the second depth of the second trench, the liner dielectric formed on a second bottom surface of the second trench and a second sidewall of the second trench, and the first layer formed on the liner dielectric in the second trench. The second sidewall of the second trench contacts a shallow trench isolation disposed on a top semiconductor surface of the semiconductor layer. The first depth of the first trench is equal to the second depth of the second trench, the liner dielectric formed on a second bottom surface of the second trench and a first portion of a second sidewall of the second trench, the first layer formed on the liner dielectric, and the second layer formed on a second portion of the second sidewall. The second layer contacts a side portion of the first layer. The second depth of the second trench is less than the first depth of the first trench, the second layer formed on a second bottom surface of the second trench and the second sidewall of the second trench, wherein the second bottom surface is separated from the buried dielectric layer by the semiconductor layer. The second sidewall of the second trench is separated from the shallow trench isolation by the semiconductor layer.
In another embodiment, a method for manufacturing a deep trench isolation and substrate connection on Semiconductor-On-Insulator comprises forming a first trench in a semiconductor layer, the first trench comprising a first width and a first depth, wherein a shallow trench isolation is formed on a top semiconductor surface of the semiconductor layer, a buried oxide layer formed between a bottom semiconductor surface of the semiconductor layer and a substrate, and the buried dielectric layer contacting a first bottom surface of the first trench. A second trench is formed in the semiconductor layer, the second trench comprising a second width and a second depth, wherein the first width is wider than the second width. A liner dielectric is deposited in the first trench and the second trench. A first layer is deposited on the liner dielectric, wherein the first layer fills the second trench. A portion of the liner dielectric and the buried dielectric layer is etched from the first bottom surface of the first trench to form an opening on the first bottom surface. A second layer is deposited on the first layer to form a contact to the substrate through the opening.
Alternative embodiments of the method for manufacturing a deep trench isolation and substrate connection on Semiconductor-On-Insulator include one of the following features, or any combination thereof. The first layer is anisotropically etched to expose a top liner surface of the liner dielectric on the first bottom surface of the first trench, wherein the liner dielectric on a second bottom surface of the second trench is not etched. The first trench and the second trench are etched concurrently. Removing a surface layer of the second layer to expose the first layer in the first trench and the second trench. The first depth of the first trench is equal to the second depth of the second trench. The first trench and the second trench are each formed by etching through the shallow trench isolation. A mask is patterned to expose the second trench, wherein the first depth of the first trench is equal to the second depth of the second trench; the first layer is etched to recess the first layer in the second trench to a depth of a buried conductive layer formed in the semiconductor layer; the mask is removed; and a third layer is deposited in the second trench to form a conductive contact to the buried conductive layer. A mask is patterned to expose the second trench, wherein the second depth of the second trench is less than the first depth of the first trench, and a second bottom surface of the second trench is separated from the buried dielectric layer by the semiconductor layer; the first layer is etched to remove the first layer in the second trench; the mask is removed; and a third layer is deposited in the second trench to form a conductive contact to the buried conductive layer formed in the semiconductor layer. The second layer and the third layer are each polysilicon layers doped with a conductive dopant.
In another embodiment, a method for manufacturing a deep trench isolation and substrate connection on Semiconductor-On-Insulator comprises forming a first trench in a semiconductor layer, the first trench comprising a first width and a first depth, a buried dielectric layer formed between a bottom semiconductor surface of the semiconductor layer and a substrate, and the buried dielectric layer contacting a first bottom surface of the first trench. A second trench is formed in the semiconductor layer, the second trench comprising a second width and a second depth, wherein the first width is wider than the second width, and the second depth is less than the first depth. A liner dielectric is deposited in the first trench and the second trench. An undoped first layer is deposited on the liner dielectric, wherein the undoped first layer fills the second trench. A portion of the liner dielectric and the buried dielectric layer is etched from the first bottom surface of the first trench to form an opening on the first bottom surface. A second layer is deposited on the undoped first layer to form a contact to the substrate through the opening.
Alternative embodiments of the method for manufacturing a deep trench isolation and substrate connection on Semiconductor-On-Insulator include one of the following features, or any combination thereof. A mask is patterned to expose the second trench. The undoped first layer is etched to remove the undoped first layer in the second trench. The mask is removed. A third layer is deposited in the second trench to form a conductive contact to a buried layer formed in the semiconductor layer. A shallow trench isolation is formed on a top semiconductor surface of the semiconductor layer, wherein the first trench is formed by etching through the shallow trench isolation and the second trench is formed by etching through a silicon region not comprising the shallow trench isolation. The second layer and the third layer are each polysilicon layers doped with a conductive dopant.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Number | Name | Date | Kind |
---|---|---|---|
6627484 | Ang | Sep 2003 | B1 |
7119015 | Park et al. | Oct 2006 | B2 |
7402487 | Rennie et al. | Jul 2008 | B2 |
7468307 | Hartner et al. | Dec 2008 | B2 |
7723204 | Khemka et al. | May 2010 | B2 |
7723800 | Moens et al. | May 2010 | B2 |
7723818 | Tilke et al. | May 2010 | B2 |
7791161 | Zhu et al. | Sep 2010 | B2 |
8258028 | Tilke et al. | Sep 2012 | B2 |
8383488 | Enichlmair et al. | Feb 2013 | B2 |
8809994 | Booth, Jr. et al. | Aug 2014 | B2 |
9601564 | Cheng et al. | Mar 2017 | B2 |
10163680 | Hu et al. | Dec 2018 | B1 |
20040018705 | Colson et al. | Jan 2004 | A1 |
20070224738 | Khemka | Sep 2007 | A1 |
20080012090 | Meiser et al. | Jan 2008 | A1 |
20080283960 | Lerner | Nov 2008 | A1 |
20110143519 | Lerner | Jun 2011 | A1 |
20120091593 | Cheng et al. | Apr 2012 | A1 |
20120139080 | Wang | Jun 2012 | A1 |
20160233296 | Cheng | Aug 2016 | A1 |
20180233514 | Lee et al. | Aug 2018 | A1 |
20180358257 | Enda | Dec 2018 | A1 |
20200176359 | Chen | Jun 2020 | A1 |
Entry |
---|
Wang, J.J., “Selective Substrate Contact with Dual Width Trenches”, Motorola Technical Developments, vol. 18, pp. 18-21, Mar. 1, 1992. |
Number | Date | Country | |
---|---|---|---|
20210217655 A1 | Jul 2021 | US |