Patent Grant
9311698
1. Field of the Invention
The present invention generally relates to detecting defects on a wafer using template image matching.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
Inspection generally involves applying some defect detection parameters to output generated by scanning and/or imaging a wafer. The defect detection parameters may include a threshold that is applied to the output or to a difference between the output and some reference output. Different detection thresholds can be set depending on varying characteristics of the output such as brightness and/or noise due to roughness of different regions of a device, but typically not depending on the locations of the regions within the inspected area. There is no easy way to treat different regions in the output separately according to the device context resolved in the output.
Information beyond simple defect detection is often generated during inspection processes. For example, the detected defects are often classified into different groups. In one such example, after finding defects, they may be classified into different groups based on the defect characteristics such as size, magnitude, and location. Defects can also be classified based on the information contained within a patch image, a relatively small subsection of the full image. Sometimes, the context in which a defect was found cannot be determined from a patch image alone, requiring a larger section of the image surrounding the defect.
Accordingly, it would be advantageous to develop methods and systems for detecting defects on a wafer that do not have one or more of the disadvantages described above.
The following description of various embodiments is not to be construed in any way as limiting the subject matter of the appended claims.
One embodiment relates to a computer-implemented method for detecting defects on a wafer. The method includes generating a template image using information about a device being formed on the wafer. At least some pixels in the template image are associated with regions in the device having different characteristics. The method also includes acquiring output of an electron beam inspection system for the wafer and matching the template image to the output based on patterns in the template image and the output. In addition, the method includes identifying the regions that pixels in the output are located within based on the regions that are associated with the pixels of the template image that match the pixels in the output. The method further includes applying defect detection parameters to the pixels in the output based on the regions that the pixels are located within to thereby detect defects on the wafer. The steps described above are performed by a computer system.
Each of the steps of the method described above may be further performed as described herein. In addition, the method described above may include any other step(s) of any other method(s) described herein. Furthermore, the method described above may be performed by any of the systems described herein.
Another embodiment relates to a non-transitory computer-readable medium containing program instructions stored therein for causing a computer system to perform a computer-implemented method for detecting defects on a wafer. The computer-implemented method includes the steps of the method described above. The computer-readable medium may be further configured as described herein. The steps of the method may be performed as described further herein. In addition, the method may include any other step(s) of any other method(s) described herein.
An additional embodiment relates to a system configured to detect defects on a wafer. The system includes an electron beam inspection subsystem configured to acquire output for a wafer. The system also includes a computer subsystem configured to generate a template image using information about a device being formed on the wafer. At least some pixels in the template image are associated with regions in the device having different characteristics. The computer subsystem is also configured to match the template image to the output based on patterns in the template image and the output and to identify the regions that pixels in the output are located within based on the regions that are associated with the pixels of the template image that match the pixels in the output. The computer subsystem is further configured to apply defect detection parameters to the pixels in the output based on the regions that the pixels are located within to thereby detect defects on the wafer. The system may be further configured according to any embodiment(s) described herein.
Further advantages of the present invention will become apparent to those skilled in the art with the benefit of the following detailed description of the preferred embodiments and upon reference to the accompanying drawings in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. The drawings may not be to scale. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Turning now to the drawings, it is noted that the figures are not drawn to scale. In particular, the scale of some of the elements of the figures is greatly exaggerated to emphasize characteristics of the elements. It is also noted that the figures are not drawn to the same scale. Elements shown in more than one figure that may be similarly configured have been indicated using the same reference numerals.
One embodiment relates to a computer-implemented method for detecting defects on a wafer. The method includes generating a template image using information about a device being formed on a wafer. At least some pixels in the template image are associated with regions in the device having different characteristics. The method, therefore, partitions a semiconductor device to be inspected into different regions of interest (ROIs) according to the device context. The device context (or a section of it) may then be rendered into a template image appropriate for inspection.
The different characteristics of the regions in the device may include different electrical characteristics that the regions will have in the final manufactured device. For example, as described further herein, different contacts within an array area of a device may have different electrical functions in the completed device and therefore may have different electrical characteristics. Each of the contacts having the same electrical functions may be grouped into one region while the electrical functions of contacts in different regions may be different. Other disparate device elements may be similarly grouped. For example, each contact, regardless of its region, may be in a region different than the dielectric material that electrically insulates the contacts from each other.
In one embodiment, the information includes design data for the device. For example, device context can be obtained in the form of a device layout design database (e.g., GDSII files) and may include any design information known in the art. In another embodiment, the information includes a high resolution image of the device being formed on the wafer. For example, device context information can be obtained in the form of relatively high resolution images of the device to be inspected. A “high resolution image,” as used herein, generally refers to any image in which the patterns on the wafer are resolved, and are preferably relatively well resolved, such that information about patterns in the device formed on the wafer can be determined from the image with relatively high accuracy. High resolution images of patterns of a device formed on a wafer can be acquired using, for example, an electron beam inspection system. In this manner, the context can be derived empirically from a relatively good quality image.
In one embodiment, the method includes determining the regions that the pixels in the template image are associated with prior to acquiring the output as described further herein. For example, the method may partition the semiconductor device into different ROIs prior to the inspection of the wafer. The template image with the information for the different regions may then be stored into some file or data structure that can be accessed by the inspection system that will be performing the inspection of the wafer. In to addition, the template image and the associated information may be used for the inspection of more than one wafer.
In another embodiment, the method includes determining the regions that the pixels in the template image are associated with based on properties of the device, defects of interest (DOI), known nuisance defects, or some combination thereof. For example, segmentation schemes can be formed to partition the device context into multiple regions based on the device physics, DOI at the moment, and/or the presence of dominating nuisances. In many cases, the locations of DOI within a cell or a device are known as is the location of noise and/or nuisance. Such information can be used to separate the regions in the template image into those that correspond to DOI and those that do not. The device context-based segmentation scheme can be formulated with the assistance of design-based hot spot analysis software. In addition, from an abstracted unit cell context, the user can mark out the areas of interest, and these may be the only areas to be inspected for defects during the inspection. However, the determination of the regions may be completely automated.
In one embodiment, at least one of the regions corresponds to only a single contact within a repeating memory cell structure of the device. For example, regions can be as small as individual contacts within a repeating memory cell structure. In addition, one or more of the regions may be as small a contact or as any other feature or structure in the device while other regions may include more than one feature, a layer, etc.
In another embodiment, at least some of the regions correspond to different types of contacts within a repeating memory cell structure of the device. For example,
In some embodiments, at least one of the regions corresponds to an oxide area between contacts in a repeating memory cell structure of the device, and applying defect detection parameters as described further herein is not performed for the oxide area. For example, some regions can be excluded from the inspection such as the oxide area between contacts. In the example shown in
As described herein, the regions may be defined based on electrical characteristics of features in the device, known DOI, and known nuisances. Therefore, regions that may produce output in the inspection system having similar characteristics (e.g., noise, signal, signal-to-noise ratio, brightness, contrast, and any other image, signal, or data characteristics) may be separated into different regions. In other words, unlike other methods that may separate pixels based on image characteristics, the embodiments described herein may separate at least some of the inspection area into regions without regard to how the regions affect the inspection system output.
In an additional embodiment, the method includes generating multiple template images using the information about the device, and each of the multiple template images is generated for one of multiple pixel sizes and optical conditions for the electron beam inspection system described further herein. For example, the template image (i.e., the abstracted unit cell context) may be rendered to the pixel size of the inspection system (i.e., the correct pixel size). In addition, a relatively high resolution template unit cell can be rendered to be used in multiple pixel sizes and/or optics conditions. In this manner, the template image may be rendered to simulate how the portion of the device corresponding to the template image will appear to the inspection system thereby increasing the ability of the method to correctly match the template image to the output of the inspection system. In addition, when there are more than one template image, each of which corresponds to different pixel sizes and/or other optical conditions of the inspection system, the correct template image may be selected at the beginning of the inspection based on the parameters of the inspection system in the inspection recipe that will be used for inspection of the wafer.
The method also includes acquiring output of an electron beam inspection system for the wafer. Acquiring the output may include actually performing an inspection of the wafer (e.g., by scanning the wafer using the electron beam inspection system). However, acquiring the output may not include performing an inspection on the wafer. For example, acquiring the output may include acquiring the output from a storage medium in which the output has been stored by another method or the electron beam inspection system. The inspection may include any suitable inspection including any of those described further herein. The output may include any and all output that may be generated by an inspection process or system.
The method further includes matching the template image to the output based on patterns in the template image and the output. For example, during the inspection process, the device context template image is matched to the acquired output (e.g., an inspection image or images) to determine the location of the context (e.g., each unit cell context) within the inspection image. In particular, pattern matching may be used to locate the unit cell or portion of the device corresponding to the template image within the array region or another region of the device. In one such embodiment, as shown in
As shown in
As further shown in
A match between the template image and the output of the electron beam inspection system may be declared in situations in which a “perfect” match cannot be found. For example, “matching” may include searching for “perfect matches” and also matches within some range of uncertainty or error. In this manner, the matching may be performed while taking into account the fact that the output of the electron beam inspection system may vary due to variations in the wafer itself, which may be caused by, for example, variations in the parameters of the process used to form the patterns on the wafer.
In one embodiment, the template image corresponds to a unit cell within an array region of the device, and matching the template image to the output includes matching the template image to the pixels in the output corresponding to one unit cell in the array region based on the patterns and propagating the matching throughout the array region based on information about the unit cell and the array region. For example, the unit cell may be propagated throughout the array region utilizing the array cell size and a small search range. In other words, if the template image corresponds to one unit cell, since the array region is made up of multiple unit cells, once a match between the template image and some portion of the output has been found, the template image will be matched to one unit cell in the output. Information about the dimensions and arrangement of the unit cells in the array region may then be used to identify other unit cells in the output without performing the matching. Propagating the matching in this manner may be advantageous because it may speed up the inspection process overall and, in instances in which the wafer properties vary across unit cells in the same array region, propagating the matching in this manner can increase the accuracy in which the locations of the unit cells in the output can be identified.
In another embodiment, the template image corresponds to a unit cell within an array region of the device, and matching the template image to the output is performed for an entire row and column of unit cells within a care area in the array region. For example, in “smart” array inspection, pattern matching of the template image to the inspection pixels may be performed for a complete row and column of cells within the array care area. The array care area may be determined in any suitable manner by the embodiments described herein or another method or system.
In some embodiments, the template image corresponds to a unit cell within an array region of the device, and the matching is performed for every unit cell within the array region. For example, for array real time alignment (RTA), pattern matching may be to performed for every unit cell inside the array region. In addition, the alignment can be performed in both the x and y directions, similar to multi-segmented alignment (MS).
The method also includes identifying the regions that pixels in the output are located within based on the regions that are associated with the pixels in the template image that match the pixels in the output. In this manner, during the inspection, the locations of the different regions are identified according to the details of the device context resolved in the image. Each pixel in the image can then be allocated to one of the predetermined regions. In this manner, rendering and matching of the device context is performed for the purpose of identifying the location of the context within the inspection image. In addition, the device context-based segmentation of the inspection image can be performed prior to defect detection. As such, the embodiments described herein can be used to “bin” pixels in the inspection image before inspection is performed using those pixels.
In one embodiment, identifying the regions includes overlaying a region segmentation scheme onto the pixels in the output that match the template image. For example, once the location of the context within the inspection image is obtained, the region segmentation scheme may be overlaid on the inspection image to partition all pixels in the inspection image into different regions. In addition, once the location of each unit cell context is obtained, the region segmentation scheme may be applied in any other manner and all pixels in the inspection image may be partitioned into appropriate regions.
The method also includes applying defect detection parameters to the pixels in the output based on the regions that the pixels are located within to thereby detect defects on the wafer. In this manner, the embodiments described herein are configured for context sensitive electron beam wafer inspection. For example, pixels in the different regions can be processed separately using different defect detection methods that are appropriate for each individual region. In one such example, pixels in each region can be processed to with different detection methods or ignored altogether if desired. For example, there could be multiple groups of areas of interest, and each group could have its own threshold, defect detection method, or defect detection parameters. In another example, during inspection of the context regions, since the exact location of each feature within a cell is known due to the matching described herein, each of the regions may be histogrammed and inspected separately with their individual threshold method and parameters. In addition, some areas can be marked as background and will not be inspected.
In this manner, context sensitive inspection (CSI) may utilize the design knowledge of a unit cell within an array region or of any other region within a device to perform targeted inspections of specific ROIs at sensitive locations where the DOI are expected to occur. In addition, the embodiments described herein can be used to determine the location of each unit cell within a swath image and the location of the ROIs within the cell such that only the part of the cell that is of potential interest needs to be inspected while leaving out uninteresting background areas. In this manner, only the pixels within the user-defined areas of interest can be inspected for defects. Therefore, nuisances outside these areas do not decrease the signal-to-noise ratio for DOI and do not need binning to filter out. As such, the embodiments described herein provide a sensible way for a user to perform targeted inspection based on the design knowledge of the device context. In addition, segmentation of the inspection image gives the user the flexibility to customize the inspection for each region thereby making possible new ways to suppress nuisance defects and improve inspection sensitivity for DOIs. Furthermore, optics selection could utilize the reduction in nuisance detection due to the methods described herein to increase the signal-to-noise ratio for DOI only, with no need to suppress irrelevant nuisances. In one such example, the embodiments described herein can be used with optics selector, which may be configured and/or performed as described in U.S. Pat. No. 8,073,240 issued on Dec. 6, 2011 to Fischer et al., which is incorporated by reference as if fully set forth herein, and even image optimization, where the gain of the inspection system is adjusted to maximize contrast of the ROI.
In one embodiment, the defect detection parameters include whether or not to perform defect detection in one or more of the regions and, for the regions in which the defect detection is to be performed, a threshold that depends on the regions in which the pixels are located, and the threshold is to be applied to a difference between the pixels in the output and reference pixels. For example, after the region segmentation scheme has been applied to pixels in the inspection image, defect detection can be performed on the predetermined DOI regions (each with its own detection threshold) only, while ignoring all information from the background dielectric and non-DOI regions. The detection threshold of each region can be set individually. In one such example, knowing the layout of a cell, each contact could be assigned its own region with its own threshold. Regions where a relatively small DOI is expected can be inspected with relatively high sensitivity while other regions that may contain lots of leakage nuisance defects can be detuned. In addition, regions that contain significant noise can be excluded before they overwhelm a defect detection algorithm. Therefore, thresholds can be significantly lowered in other regions, which could make possible or optimize the detection of DOI.
In one such example, a memory structure that is relatively well-resolved with electron beam inspection system optics can be partitioned into individual contact types such as PMOS/NMOS/Bitline or Wordline contacts, etc. The threshold for each of these contacts can be set individually. For example, if one contact type is prone to leakage-induced gray level variation that is considered a nuisance, its detection threshold can be detuned so as to not overwhelm the inspection result with nuisances. The segmentation of these leakage-proven contacts also prevents the leakage signal from impacting the detection sensitivity of defects from other regions, which can greatly improve the overall inspection sensitivity to the defect types that the customer is interested in.
In another embodiment, applying the defect detection parameters includes averaging multiple pixels in the output corresponding to multiple unit cells in an array region of the device to generate a reference image, subtracting the reference image from a test image in the output that corresponds to one of the multiple unit cells to generate a difference image, and applying the defect detection parameters to the difference image based on the regions that pixels in the difference image are located within. For example, for cell averaging, neighboring cells can be averaged for a relatively low noise reference image, without the restriction of alignment. Cells from above and below can be used in the averaging as well.
In one embodiment, the method includes automatically associating the detected defects with the regions in which they are located. In other words, defects that are detected as described herein can be automatically associated with the region in which they are detected. For example, all defects detected in inspections described herein can be associated with a particular region and relative location within the unit cell context.
The above-described information can then be used for further classification of the defects. For example, in another embodiment, the method includes classifying the detected defects based on the regions in which they are located. In this manner, any defect that is detected during an inspection can be automatically classified by the region it was found in. As such, the information about the region in which the defects are detected can be used for further classification of the defects. In addition, classifying the detected defects may include using the region and location-within-context information for each defect (automatically obtained from the device context-based segmentation) for the purpose of defect classification. In this manner, defects detected during the inspection may be classified according to the device context-based region and/or location thereby giving the user useful information relevant to the design faster.
In some embodiments, each contact type in the device is associated with a different one of the regions, and the method includes displaying density of the detected defects in each contact type. For example, detected defects can be automatically binned by region based on the region in the template image that they are located within. Therefore, wafer maps of each defect type would be trivial to generate. In addition, every contact type can be set as its own ROI. After the inspection, the defect density of each contact type can be displayed in any suitable manner. In one such example, defect density can be displayed for PMOS contact defects, Bitline contact mis-shaped defects, Bitline contact open defects, Wordline contact open defects, and/or NMOS S/D contact open defects.
Generating the template image, acquiring the output, matching the template image to the output, identifying the regions, and applying the defect detection parameters are performed using a computer system, which may be configured as described further herein.
Although some of the steps of the method are described herein with respect to memory cell portions of a device, similar operations can be performed for non-memory cell parts of the wafer if the relevant design database is available.
All of the methods described herein may include storing results of one or more steps of the method embodiments in a non-transitory, computer-readable storage medium. The results may include any of the results described herein and may be stored in any manner known in the art. The storage medium may include any storage medium described herein or any other suitable storage medium known in the art. After the results have been stored, the results can be accessed in the storage medium and used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, etc.
Each of the embodiments of the method described above may include any other step(s) of any other method(s) described herein. In addition, each of the embodiments of the method described above may be performed by any of the systems described herein.
Another embodiment relates to a non-transitory computer-readable medium containing program instructions stored therein for causing a computer system to perform a computer-implemented method for detecting defects on a wafer. One embodiment of such a computer-readable medium is shown in
The computer-implemented method includes the steps of the method described herein. The computer-implemented method may also include any other step(s) of any other method(s) described herein. In addition, the computer-readable medium may be further configured as described herein.
Program instructions 30 implementing methods such as those described herein may be stored on computer-readable medium 28. The computer-readable medium may be a non-transitory computer-readable storage medium such as a magnetic or optical disk, a magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.
The program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and/or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (“MFC”), or other technologies or methodologies, as desired.
Computer system 32 may take various forms, including a personal computer system, mainframe computer system, workstation, image computer, parallel processor, or any other device known in the art. In general, the term “computer system” may be broadly defined to encompass any device having one or more processors, which executes instructions from a memory medium.
The system also includes computer subsystem 36 configured to generate a template image using information about a device being formed on the wafer, according to any of the embodiments described herein. As described further herein, at least some pixels in the template image are associated with regions in the device having different characteristics. The computer subsystem is also configured to match the template image to the output based on patterns in the template image and the output, which may be performed according to any of the embodiments described further herein. In addition, the computer subsystem is configured to identify the regions that pixels in the output are located within based on the regions that are associated with the pixels of the template image that match the pixels in the output, which may be performed according to any of the embodiments described further herein. The computer subsystem is further configured to apply defect detection parameters to the pixels in the output based on the regions that the pixels are located within to thereby detect defects on the wafer, which may be performed according to any of the embodiments described further herein. The computer subsystem and the system may be further configured to perform any other step(s) of any method(s) described herein.
Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. For example, methods and systems for detecting defects on a wafer are provided. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.
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| Number | Date | Country | |
|---|---|---|---|
| 20140193065 A1 | Jul 2014 | US |
