The description herein relates to a mechanism for determining mask rule check violations and mask design for photolithography masks to be employed in in semiconductor manufacturing.
A lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a patterning device (e.g., a mask) may contain or provide a circuit pattern corresponding to an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the circuit pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target portions to which the circuit pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatuses, the circuit pattern on the entire patterning device is transferred onto one target portion in one go; such an apparatus is commonly referred to as a stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the circuit pattern on the patterning device are transferred to one target portion progressively. Since, in general, the lithographic projection apparatus will have a magnification factor M (generally <1), the speed F at which the substrate is moved will be a factor M times that at which the projection beam scans the patterning device. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
Prior to transferring the circuit pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the transferred circuit pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
As noted, lithography is a central step in the manufacturing of ICs, where patterns formed on substrates define functional elements of the ICs, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.
As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced while the number of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as “Moore's law”. At the current state of technology, layers of devices are manufactured using lithographic projection apparatuses that project a design layout onto a substrate using illumination from a deep-ultraviolet illumination source, creating individual functional elements having dimensions well below 100 nm, i.e., less than half the wavelength of the radiation from the illumination source (e.g., a 193 nm illumination source).
This process in which features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×W/NA, where λ is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus, CD is the “critical dimension”—generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1 the more difficult it becomes to reproduce a pattern on the substrate that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the lithographic projection apparatus and/or design layout. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting patterning devices, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET). The term “projection optics” as used herein should be broadly interpreted as encompassing various types of optical systems, including refractive optics, reflective optics, apertures and catadioptric optics, for example. The term “projection optics” may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, collectively or singularly. The term “projection optics” may include any optical component in the lithographic projection apparatus, no matter where the optical component is located on an optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, adjusting and/or projecting radiation from the source before the radiation passes the patterning device, and/or optical components for shaping, adjusting and/or projecting the radiation after the radiation passes the patterning device. The projection optics generally exclude the source and the patterning device.
Disclosed herein is a mechanism for improving mask rule checks (MRC) related to mask designs, for example, having curvilinear mask features. The existing MRC techniques involve cutline-based violation detections. The existing techniques lack tuning capability and cannot accommodate different curvature shapes. Also, these techniques rely on heuristic rules applied at curvature regions of the mask features. Thus, existing techniques results in several false violations detection. The present disclosure provides detectors configured to determine MRC for curvilinear features. The detectors herein provide flexibility and high tuning capability to accommodate MRC for different curved shapes of the mask features. Using the detectors, improves the MRC violation detection with less false violations thereby speeding up the MRC violation determination. Also, mask designs can be improved based on information related to MRC violations detected by the detectors herein. This in turn improves the semiconductor manufacturing process that employs a mask designed based on information related to MRC violations, according to the present disclosure.
According to an embodiment of the present disclosure, a method for determining mask rule check violations associated with mask features is described. The method includes obtaining a detector having geometric properties corresponding to a mask rule check (MRC). The detector is configured to include a curved portion to detect a curvature violation, an enclosed area (e.g., a fully enclosed area or a partially enclosed area having an opening), a predefined orientation axis configured to guide relative positioning of the detector with a mask feature, and a length along the orientation axis to detect a critical dimension violation. The orientation axis of the detector is aligned with a normal axis at a location on the mask feature to cause the length of the detector to extend along the normal axis of the mask feature. Further, the method identifies, based on the orientation axis of the detector aligned with the normal axis of the mask feature, an MRC violation corresponding to a region of the mask feature that intersects the enclosed area. The aligning and geometry of the detector causes the detector to intersect the region of mask feature to identify the curvature violation, and/or the critical dimension violation.
In an embodiment, the detector is non-circular and has at least a first curved portion and a second curved portion, wherein the first curved portion has a first radius of curvature, where the second curved portion has a second radius of curvature, and where the first radius is different from the second radius. For example, the non-circular detector has an elliptical shape, wherein a radius of curvature is configured to detect a curvature violation and a length along an orientation axis is configured to detect a critical dimension violation.
In an embodiment, the curved portion of the detector has a shape and size corresponding to a curvature of a tip portion of the mask feature, and a minimum size of the mask feature defined by mask manufacturability check.
In an embodiment, the identifying step involves determining MRC violations including a curvature violation and a critical dimension violation based on the intersection of the detector with the mask feature at a single position. In an embodiment, MRC violations associated with a curvature violation and a space violation is determined based on intersection between at least two mask features at a single position.
In an embodiment, the method further involves performing a mask design to determine shape and size of mask features of the mask design by adopting a mask design process (e.g., OPC, mask optimization or SMO) to include MRC violation detection using one or more detectors herein.
According to an embodiment of the present disclosure, a method for determining a mask design for manufacturing a mask to be employed in a semiconductor manufacturing is described. The method involves simulating, using a design layout, a mask optimization process (e.g., SMO, OPC, etc.) to determine mask features for the mask design. The design layout corresponds to features to be printed on a semiconductor chip. Using a detector portions of the mask features that violate a mask rule check (MRC) is determined. The detector (e.g., elliptical shaped) is configured to have a curved portion, an enclosed area (e.g., fully or partially enclosed), and an orientation axis that is perpendicular to a point of the curved portion, the orientation axis for guiding an orientation of the detector with respect to a mask feature to detect MRC violations. Responsive to the portions of the mask feature violating the MRC, the corresponding portions of the mask features are modified to satisfy the MRC.
In an embodiment, the determining the portions of the mask features that violate the MRC involves obtaining the detector having geometric properties corresponding to the MRC; aligning the orientation axis with a normal axis of a location on a mask feature; and identifying, based on the orientation axis of the detector and the normal axis of the mask feature, the MRC violation corresponding to a region of the mask feature that intersects the enclosed area.
In an embodiment, the detector is a single detector configured to determine MRC violations including a curvature violation and a width violation associated with the mask feature. In an embodiment, the detector is a single detector configured to determine MRC violations associated with a curvature violation and a space violation between at least two mask features.
According to an embodiment, there is provided a non-transitory computer-readable medium for determining mask rule check violations associated with mask features, the medium comprising instructions stored therein that, when executed by one or more processors, cause operations including steps of the method herein.
Although specific reference may be made in this text to the manufacture of ICs, it should be explicitly understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle”, “wafer” or “die” in this text should be considered as interchangeable with the more general terms “mask”, “substrate” and “target portion”, respectively.
In the present document, the terms “radiation” and “beam” are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g., with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g., having a wavelength in the range of about 5-100 nm).
The term “optimizing” and “optimization” as used herein refers to or means adjusting a lithographic projection apparatus, a lithographic process, etc. such that results and/or processes of lithography have more desirable characteristics, such as higher accuracy of projection of a design layout on a substrate, a larger process window, etc. Thus, the term “optimizing” and “optimization” as used herein refers to or means a process that identifies one or more values for one or more parameters that provide an improvement, e.g., a local optimum, in at least one relevant metric, compared to an initial set of one or more values for those one or more parameters. “Optimum” and other related terms should be construed accordingly. In an embodiment, optimization steps can be applied iteratively to provide further improvements in one or more metrics.
Further, the lithographic projection apparatus may be of a type having two or more tables (e.g., two or more substrate table, a substrate table and a measurement table, two or more patterning device tables, etc.). In such “multiple stage” devices a plurality of the multiple tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic projection apparatuses are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The patterning device referred to above comprises, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. One or more of the design rule limitations may be referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the substrate (via the patterning device).
The term “mask” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term “light valve” can also be used in this context. Besides the classic mask (transmissive or reflective; binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include:
As a brief introduction,
In an optimization process of a system, a figure of merit of the system can be represented as a cost function. The optimization process boils down to a process of finding a set of parameters (design variables) of the system that optimizes (e.g., minimizes or maximizes) the cost function. The cost function can have any suitable form depending on the goal of the optimization. For example, the cost function can be weighted root mean square (RMS) of deviations of certain characteristics (evaluation points) of the system with respect to the intended values (e.g., ideal values) of these characteristics; the cost function can also be the maximum of these deviations (i.e., worst deviation). The term “evaluation points” herein should be interpreted broadly to include any characteristics of the system. The design variables of the system can be confined to finite ranges and/or be interdependent due to practicalities of implementations of the system. In the case of a lithographic projection apparatus, the constraints are often associated with physical properties and characteristics of the hardware such as tunable ranges, and/or patterning device manufacturability design rules, and the evaluation points can include physical points on a resist image on a substrate, as well as non-physical characteristics such as dose and focus.
In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device and projection optics direct and shape the illumination, via the patterning device, onto a substrate. The term “projection optics” is broadly defined here to include any optical component that may alter the wavefront of the radiation beam. For example, projection optics may include at least some of the components 14A, 16Aa, 16Ab and 16Ac. An aerial image (AI) is the radiation intensity distribution at substrate level. A resist layer on the substrate is exposed and the aerial image is transferred to the resist layer as a latent “resist image” (RI) therein. The resist image (RI) can be defined as a spatial distribution of solubility of the resist in the resist layer. A resist model can be used to calculate the resist image from the aerial image, an example of which can be found in U.S. Patent Application Publication No. US 2009-0157360, the disclosure of which is hereby incorporated by reference in its entirety. The resist model is related only to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, PEB and development). Optical properties of the lithographic projection apparatus (e.g., properties of the source, the patterning device and the projection optics) dictate the aerial image. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the source and the projection optics.
An exemplary flow chart for simulating lithography in a lithographic projection apparatus is illustrated in
More specifically, it is noted that the source model 31 can represent the optical characteristics of the source that include, but not limited to, numerical aperture settings, illumination sigma (σ) settings as well as any particular illumination shape (e.g., off-axis radiation sources such as annular, quadrupole, dipole, etc.). The projection optics model 32 can represent the optical characteristics of the projection optics, including aberration, distortion, one or more refractive indexes, one or more physical sizes, one or more physical dimensions, etc. The design layout model 35 can represent one or more physical properties of a physical patterning device, as described, for example, in U.S. Pat. No. 7,587,704, which is incorporated by reference in its entirety. The objective of the simulation is to accurately predict, for example, edge placement, aerial image intensity slope and/or CD, which can then be compared against an intended design. The intended design is generally defined as a pre-OPC design layout which can be provided in a standardized digital file format such as GDSII or OASIS or another file format.
From this design layout, one or more portions may be identified, which are referred to as “clips”. In an embodiment, a set of clips is extracted, which represents the complicated patterns in the design layout (typically about 50 to 1000 clips, although any number of clips may be used). These patterns or clips represent small portions (e.g., circuits, cells or patterns) of the design and more specifically, the clips typically represent small portions for which particular attention and/or verification is needed. In other words, clips may be the portions of the design layout, or may be similar or have a similar behavior of portions of the design layout, where one or more critical features are identified either by experience (including clips provided by a customer), by trial and error, or by running a full-chip simulation. Clips may contain one or more test patterns or gauge patterns.
An initial larger set of clips may be provided a priori by a customer based on one or more known critical feature areas in a design layout which require particular image optimization. Alternatively, in another embodiment, an initial larger set of clips may be extracted from the entire design layout by using some kind of automated (such as machine vision) or manual algorithm that identifies the one or more critical feature areas.
In an embodiment, the design layout or portions of the design layout are used for designing a mask to be employed in the semiconductor manufacturing. A mask design includes determining mask features based on mask optimization simulations and checking whether mask rule checks (MRC) are satisfied. In an embodiment, the mask design includes Manhattan shaped mask feature or curvilinear mask features. The mask features are desired to satisfy mask rule checks associated with mask manufacturing process. As the mask design technology e.g., optical proximity correction (OPC) technology is migrating from Manhattan to curvilinear shapes, current MRC engine can no longer consistently flag MRC violations and drive optimization. In an embodiment, the MRC includes one or more constrains related to geometric properties associated with the mask feature that can be manufactured. For example, the geometric properties include, but not limited, to a minimum CD of a mask feature, a minimum curvature of mask feature that can be manufactured, or a minimum space between two features that can be manufactured.
The MRC detector needs to be flexible enough to accommodate different mask manufacturing technologies, especially in curvilinear feature shapes having sharper curves such as tips. The tip shapes of the mask feature may depend on mask manufacturing technology as well as may differ through use cases (e.g., chip designs) and machine settings. The present disclosure provides a detector that can be configured to perform MRC for curvilinear masks having different curvature shapes and sizes. In some examples, the detector can be configured to detect MRC violations related to spaces between two mask features (e.g., see
Process P602 involves obtaining a detector 601 having geometric properties configured to facilitate MRC detection, and a mask feature MF. In an embodiment, the detector 601 is configured to include a curved portion to detect a curvature violation, an enclosed area, an orientation axis configured to guide relative positioning of the detector 601 with the mask feature MF, and a length along the orientation axis to detect a critical dimension violation or a space violation. In an embodiment, a plurality of detectors having different shapes and sizes may be employed for a mask feature or multiple mask features. In an embodiment, the mask feature MF has a curvilinear shape. In an embodiment, the MRC may include one or more geometric properties associated with the mask feature MF. The geometric properties include, but not limited, a minimum CD of a mask feature that can be manufactured, a minimum curvature of mask feature that can be manufactured, or a minimum space between two features that can be manufactured.
In an embodiment, the obtaining of the detector 601 involves accessing a detector from a library of detectors. In an embodiment, obtaining involves receiving a pre-defined detector defined based on a shape and size of the mask feature MF and mask feature manufacturing limitations associated with a mask manufacturing process. For example, a user may define a curvature, a length, a width, an area, or geometry of the detector. Furthermore, the user may define an orientation axis of the detector 601, for example, the orientation axis may indicate a direction along a perpendicular a point of the curved portion of the detector 601.
In an embodiment, the detector 601 may be non-circular, for example, and may have an oval, a key shape, or an irregular curved shape having different radius of curvatures. For example, the detector 601 has a first curved portion and a second curved portion different from the first curved portion. The first curved portion has a first radius of curvature, and the second curved portion has a second radius of curvature, where the first radius is different from the second radius. In an embodiment, the detector 601 may be drawn using a drawing tool configured to allow a user to define shapes of different radius of curvatures and orientation axis. In an embodiment, the detector 601 may be represented as a polynomial equation, pixel representation, a GDSII or OASIS compatible representation, or other digital file formats.
In an embodiment, obtaining of the detector 601 involves receiving the detector 601 shaped based on feature size, and a curvature of the mask feature MF that is dictated by mask manufacturability or other limits. For example, a user may define the curved portion of the detector 601 to have a shape and size corresponding to a curvature of a tip portion of the mask feature MF, and a minimum size of the mask feature MF that can be manufactured.
In an embodiment, obtaining of the detector 601 involves receiving (e.g., via a user interface or a database) a single detector configured to determine MRC violations including a curvature violation and a width violation associated with the mask feature MF. In an embodiment, obtaining of the detector 601 involves receiving (e.g., via a user interface or a database) a single detector configured to determine MRC violations associated with a curvature violation and a space violation between at least two mask features.
In an embodiment, the obtaining of the detector 601 includes accessing, from a library of detectors, the detector 601 for determining MRC violation of the mask feature MF. In an embodiment, the library of detectors includes a plurality of detectors, each detector having a different shape and size than other detectors defined.
In
In
In
The present disclosure is not limited to shape and sizes discussed herein. Also, although the exemplary detectors (e.g., in
Process P604 involves aligning the orientation axis with a normal axis at a location on the mask feature MF. The normal axis is a normal drawn perpendicular to a curve at the location of interest of the mask feature MF. In an embodiment, aligning the orientation axis of the detector 601 with the normal axis of the mask feature MF involves determining a normal axis at the location of the mask feature MF; contacting an edge of the detector 601 with an edge of the feature at the location; and aligning or orienting the orientation axis of the detector 601 with the normal axis at the location of the feature. Such aligning of the detector 610 and the mask feature MF enables MRC violations caused due to curvatures as well as size to be detected. Thus, during the MRC detection along the mask feature MF, the detector 610 may be oriented and re-oriented several times depending on the geometry of the mask feature. An advantage of such orientation and re-orientation is providing the flexibility of using a single detector to check multiple MRC constraints (e.g., curvature and size) simultaneously. Example orientation and re-orientation of the detector 610 is illustrated in
Although embodiments of the present disclosure are described in detail with an orientation axis of a detector aligned with a normal axis at each location of the mask feature, the present disclosure is not limited thereto. In some embodiments, during detection, a detector may be slid along the mask feature edge with its orientation axis maintaining a certain non-zero angle with the normal axis at each location of the mask feature. In this manner, the length of the detector extends along a prescribed axis of the location on the mask feature, where the prescribed axis forms the certain non-zero angle with the normal axis of the mask feature location.
Process P606 involves identifying, based on the detector 601 aligned with the mask feature MF, an MRC violation 610 corresponding to a region of the mask feature MF that intersects the enclosed area. In an embodiment, identifying the MRC violation 610 includes determining the MRC violations by sliding the detector 610 along an edge of the mask feature MF while maintaining the orientation axis of the detector 610 aligned to a normal axis of each location of the mask feature MF.
In an embodiment, identifying the MRC violation 610 involves (a) aligning the orientation axis of the detector 610 with a first normal axis at a first location of the mask feature MF; (b) identifying, based on the detector aligned with the mask feature MF, whether a region of the mask feature MF around the first location is inside the enclosed area; (c) responsive to the region of the mask feature MF being inside the enclosed area, flagging the first location as the MRC location; and (d) responsive to the region of the mask feature MF not being inside the enclosed area, sliding the detector to a second location of the mask feature MF, and identifying the MRC violation 610 by performing steps (a)-(c) at the second location, for example, using a second normal axis at the second location of the mask feature MF.
In
Similarly, at a second location L2, the orientation axis O1 of the detector D1 may be aligned with a normal axis at the second location L2. It can be seen that the detector D1 does not includes any portion of the mask feature inside the enclosed area. Hence, the second location L2 may not be flagged as an MRC violation, or may be flagged as satisfying the MRC. Similarly, at a third location L3, an MRC violation may be detected and geometric properties of the mask feature at location L3 may be extracted similar to at location L1.
A circular detector may be limited to either a size violation detection or a curvature detection, but not both. In other words, multiple circular detectors may be needed to detect different types of MRC violation. On the other hand, the detector according to the present disclosure are configured to determine, using a single detector, different types of violations. As such, a single pass along the mask feature may determine different types of violations. Examples of detectors in present disclosure are shown in
In an embodiment, MRC violations may be determined by sliding the detector D2 inside the mask feature along the edge of mask feature and orienting the detector D2 based on the orientation axis O2. In an embodiment, an MRC violation is detected when a portion of the mask feature is inside the detector D2. In an embodiment, an absence or occurrence of an MRC violation at a first location L1 is determined by aligning the orientation axis O2 (dotted line) with a normal axis (not shown) of the mask feature at the first location L1.
At the first location L1, the detector D2 does not include any portion of the mask feature inside the enclosed area, or does not intersects with the mask feature edge except the point or points of tangency around L1. Hence, the first location L1 is not flagged as an MRC violation. Similarly, at a second location L2, the orientation axis O2 of the detector D2 may be aligned with a second normal axis at the second location L2. It can be seen that the detector D1 does not includes any portion of the mask feature inside the enclosed area. Hence, the second location L2 is not flagged as an MRC violation, or may be flagged as satisfying the MRC. At a third location L3, the detector D2 is oriented by aligning the orientation axis O2 with a third normal axis at the location L3 as D2 intersects with the mask edge in addition to points of tangency. Upon orientating, an MRC violation may be detected, as a portion of the mask feature 800 is inside the detector D2. For example, at location L3, a CD violation is detected by the detector D2 because a length of the detector (which characterizes CD violations) along the orientation axis causes a portion of the mask feature 800 to intersect with the detector D2 and cause the portion of the mask feature 800 to be inside the detector D2. In an embodiment, at location L3, geometric properties of the mask feature at location L3 may be extracted similar to at location L1. In an embodiment, geometric properties associated with the mask feature may be extracted and further used for performing mask designs (e.g., OPC). For example, upon detecting an MRC violation, geometric properties such as a curvature, length of the feature inside the detector, etc. may be determined.
The above examples show different types of MRC violations (e.g., CD violation, curvature violation) at different locations on mask features. Depending on the shape of the mask features, the detector may detect only CD violation, only curvature violation, or both CD and curvature violation at a single position. Thus, the detectors configured according to the present disclosure can advantageously detect multiple types of violation at a single position of a mask feature using a single detector thereby enhancing MRC violation detecting capabilities in a single pass over the mask feature. Accordingly, modifications may be made to the mask feature shapes to overcome such multiple violations in a single step, which in turn will reduce the number of iterations that may be required in a mask design process and expedite the mask design process.
In an embodiment, the method 600 further involves performing a mask design by employing the detectors discussed herein. In an embodiment, the mask design process may determine shape and size of mask features of the mask design using MRC violations detected by one or more detectors discussed herein. As an example, performing of the mask design involves (a) simulating, using a design layout, a mask optimization process to determine the mask features for the mask design, the design layout corresponding to features to be printed on a semiconductor chip; (b) determining, via the detector, portions of the mask features that violate the MRC (e.g., as discussed with respect to processes P602-606); and (c) responsive to violating the MRC, modifying the corresponding portions of the mask features to satisfy the MRC; and repeating steps (a)-(c).
In an embodiment, the mask optimization process involves a mask only optimization process, a source mask co-optimization process, and/or an optical proximity correction process. Example mask design process including OPC are discussed with respect to
In an embodiment, the OPC process may be tailored to include the MRC violation check using detectors as discussed herein (e.g.,
Process P902 involves simulating a mask optimization process using a design layout to determine mask features for the mask design. The design layout includes features corresponding to target features to be printed on a semiconductor chip. In an embodiment, the mask optimization process involves executing one or more process models of a patterning process and performing mask design to determine curvilinear shapes of the mask feature. The process model may be a rigorous, empirical or semi-empirical physical model or a machine learning model. In an embodiment, the mask design involves free form mask design, level-set method, or other methods related to continuous transmission mask (CTM), etc. However, although such curvilinear may generate ideal target features to be printed on the semiconductor chip, it is desired to perform MRC violations related to the mask features to ensure manufacturability of the mask to be employed in the patterning process.
Process P904 involves determining MRC violations by a detector 901. In an embodiment, the determination of MRC violations involves determining portions of the mask features that violate a mask rule check (MRC). As discussed herein, an example detector has a curved portion, an enclosed area, and an orientation axis that is perpendicular to a point of the curved portion (e.g., as discussed with respect to
In an embodiment, the MRC includes one or more geometric properties associated with the mask feature. For example, the geometric properties include at least one of: a minimum CD of a mask feature that can be manufactured, a minimum curvature of mask feature that can be manufactured, or a minimum space between two features that can be manufactured.
In an embodiment, the determining the portions of the mask features that violate the MRC involves obtaining the detector 901 having geometric properties corresponding to the MRC; aligning the orientation axis with a normal direction of a location on a mask feature; and identifying the MRC violation corresponding to a region of the mask feature that intersects the enclosed area based on the aligned detector and the mask feature.
In an embodiment, the detector 901 is a non-circular. A non-circular detector may be characterized by a shape having a plurality of radius of curvatures. For example, the non-circular detector includes a first curved portion having a first radius of curvature and a second curved portion having a second radius of curvature. The first radius is different from the second radius. In an embodiment, the detector 901 is shaped based on feature size, and a curvature of the mask feature that can be manufactured. As an example, the curved portions of the detector 901 has a shape and size corresponding to a curvature of a tip portion of the mask feature, and a minimum size of the mask feature that can be manufactured.
In an embodiment, obtaining the detector 901 involves receiving (e.g., via a user interface or a database) a single detector configured to determine MRC violations including a curvature violation and a width violation associated with the mask feature. In an embodiment, obtaining the detector 901 comprises receiving (e.g., via a user interface or a database) a single detector configured to determine MRC violations associated with a curvature violation and a space violation between at least two mask features.
In an embodiment, aligning the orientation axis of the detector 901 with a normal axis of the mask feature involves determining a normal axis at the location of the mask feature; contacting an edge of the detector 901 with an edge of the feature at the location; and orienting the orientation axis of the detector 901 with the normal axis at the location of the feature.
In an embodiment, identifying the MRC violation involves determining the MRC violations by sliding the detector 901 along an edge of the mask feature while maintaining the orientation axis of the detector 901 aligned to a normal axis of each location of the mask feature.
In an embodiment, identifying the MRC violation involves (a) aligning the orientation axis of the detector 901 with a first normal axis at a first location of the mask feature; (b) identifying, based on the aligned detector and the mask feature, whether a region of the mask feature around the first location is inside the enclosed area; (c) responsive to the region of the mask feature being inside the enclosed area, flagging the first location as the MRC location; and (d) responsive to the region of the mask feature not being inside the enclosed area, sliding the detector 901 to a second location of the mask feature, and identifying the MRC violation by performing steps (a)-(c) at the second location, for example, using a second normal axis at the second location of the mask feature. An example of steps of aligning, orientating, and identifying of MRC violation are illustrated in
Process P906 involves responsive to the portions violating the MRC, modifying the corresponding portions of the mask features to satisfy the MRC. In an embodiment, modifying the mask features may involve increasing or decreasing a size and/or a curvature of the portions of the mask features to satisfy the MRC using the detector 901. In an embodiment, modifying the mask features is an iterative process. Each iteration may involve executing one or more process models associated with a patterning process using the modified mask features to generate target features to be printed on the semiconductor chip; determining whether the target features satisfy design specification associated with the design layout; and responsive to design specification not being satisfied, modifying the mask features to satisfy the design specification.
Examples of mask optimization process including OPC process are further discussed in detail with respect to
According to present disclosure, the combination and sub-combinations of disclosed elements constitute separate embodiments. For example, a first combination includes obtaining a detector, and determining MRC violations associated with mask features. The sub-combination may include the detector being a particular enclosed shape and size based on the mask feature, where MRC violations occur when a portion of the mask feature is inside the detector. In another sub-combination, the detector may be circular, or a non-circular shape. In another example, the combination includes determining a mask design based on a detector identified MRC violations. The detector having a non-circular shape that detects width, space and/or curvature violations.
In a lithographic process, as an example, a cost function may be expressed as
wherein (z1, z2, . . . , zN) are N design variables or values thereof. fp (z1, z2, . . . , zN) can be a function of the design variables (z1, z2, . . . , zN) such as a difference between an actual value and an intended value of a characteristic at an evaluation point for a set of values of the design variables of (z1, z2, . . . , zN). wp is a weight constant associated with fp (z1, z2, . . . , zN). An evaluation point or pattern more critical than others can be assigned a higher wp value. Patterns and/or evaluation points with larger number of occurrences may be assigned a higher wp value, too. Examples of the evaluation points can be any physical point or pattern on the substrate, any point on a virtual design layout, or resist image, or aerial image, or a combination thereof. CF (z1, z2, . . . , zN) can be a function of the illumination source, a function of a variable that is a function of the illumination source or that affects the illumination source. Of course, CF (z1, z2, . . . , zN) is not limited to the form in Eq. 1. CF(z1, z2, . . . , zN) can be in any other suitable form.
The cost function may represent any one or more suitable characteristics of the lithographic projection apparatus, lithographic process or the substrate, for instance, focus, CD, image shift, image distortion, image rotation, stochastic variation, throughput, local CD variation, process window, or a combination thereof. In one embodiment, the design variables (z1, z2, . . . , zN) comprise one or more selected from dose, global bias of the patterning device, and/or shape of illumination. In one embodiment, the design variables (z1, z2, . . . , zN) comprise the bandwidth of the source. Since it is the resist image that often dictates the pattern on a substrate, the cost function may include a function that represents one or more characteristics of the resist image. For example, fp (z1, z2, . . . , zN) of such an evaluation point can be simply a distance between a point in the resist image to an intended position of that point (i.e., edge placement error EPEp (z1, z2, . . . , zN)). The design variables can include any adjustable parameter such as an adjustable parameter of the source (e.g., the intensity, and shape), the patterning device, the projection optics, dose, focus, etc.
The lithographic apparatus may include components collectively called a “wavefront manipulator” that can be used to adjust the shape of a wavefront and intensity distribution and/or phase shift of a radiation beam. In an embodiment, the lithographic apparatus can adjust a wavefront and intensity distribution at any location along an optical path of the lithographic projection apparatus, such as before the patterning device, near a pupil plane, near an image plane, and/or near a focal plane. The wavefront manipulator can be used to correct or compensate for certain distortions of the wavefront and intensity distribution and/or phase shift caused by, for example, the source, the patterning device, temperature variation in the lithographic projection apparatus, thermal expansion of components of the lithographic projection apparatus, etc. Adjusting the wavefront and intensity distribution and/or phase shift can change values of the evaluation points and the cost function. Such changes can be simulated from a model or actually measured.
The design variables may have constraints, which can be expressed as (z1, z2, . . . , zN)∈Z, where Z is a set of possible values of the design variables. One possible constraint on the design variables may be imposed by a desired throughput of the lithographic projection apparatus. Without such a constraint imposed by the desired throughput, the optimization may yield a set of values of the design variables that are unrealistic. For example, if the dose is a design variable, without such a constraint, the optimization may yield a dose value that makes the throughput economically impossible. However, the usefulness of constraints should not be interpreted as a necessity. For example, the throughput may be affected by the pupil fill ratio. For some illumination designs, a low pupil fill ratio may discard radiation, leading to lower throughput. Throughput may also be affected by the resist chemistry. Slower resist (e.g., a resist that requires higher amount of radiation to be properly exposed) leads to lower throughput. In an embodiment, the constraints on the design variables are such that the design variables cannot have values that change any geometrical characteristics of the patterning device-namely, the patterns on the patterning device will remain unchanged during the optimization.
The optimization process therefore is to find a set of values of the one or more design variables, under the constraints (z1, z2, . . . , zN)∈Z, that optimize the cost function, e.g., to find:
A general method of optimizing, according to an embodiment, is illustrated in
Different subsets of the design variables (e.g., one subset including characteristics of the illumination, one subset including characteristics of patterning device and one subset including characteristics of projection optics) can be optimized alternatively (referred to as Alternative Optimization) or optimized simultaneously (referred to as Simultaneous Optimization). So, two subsets of design variables being optimized “simultaneously” or “jointly” means that the design variables of the two subsets are allowed to change at the same time. Two subsets of design variables being optimized “alternatively” as used herein means that the design variables of the first subset but not the second subset are allowed to change in the first optimization and then the design variables of the second subset but not the first subset are allowed to change in the second optimization.
In
The pattern selection algorithm, as discussed before, may be integrated with the simultaneous or alternative optimization. For example, when an alternative optimization is adopted, first a full-chip SO can be performed, one or more ‘hot spots’ and/or ‘warm spots’ are identified, then a LO is performed. In view of the present disclosure numerous permutations and combinations of sub-optimizations are possible in order to achieve the desired optimization results.
In an exemplary optimization process, no relationship between the design variables (z1, z2, . . . , zN) and fp (z1, z2, . . . , zN) is assumed or approximated, except that fp (z1, z2, . . . , zN) is sufficiently smooth (e.g. first order derivatives
(n=1, 2, . . . N) exist), which is generally valid in a lithographic projection apparatus. An algorithm, such as the Gauss-Newton algorithm, the Levenberg-Marquardt algorithm, the Broyden-Fletcher-Goldfarb-Shanno algorithm, the gradient descent algorithm, the simulated annealing algorithm, the interior point algorithm, and the genetic algorithm, can be applied to find ({tilde over (z)}1, {tilde over (z)}2, . . . , {tilde over (z)}N).
Here, the Gauss-Newton algorithm is used as an example. The Gauss-Newton algorithm is an iterative method applicable to a general non-linear multi-variable optimization problem. In the i-th iteration wherein the design variables (z1, z2, . . . , zN) take values of (z1i, z2i, . . . , zNi), the Gauss-Newton algorithm linearizes fp (z1, z2, . . . , zN) in the vicinity of (z1i, z2i, . . . , zNi), and then calculates values (z1(i+1), z2(i+1), . . . , zN(i+1)) in the vicinity of (z1i, z2i, . . . , zNi) that give a minimum of CF(z1, z2, . . . , zN). The design variables (z1, z2, . . . , zN) take the values of (z1(i+1), z2(i+1), . . . , zN(i+1)) in the (i+1)-th iteration. This iteration continues until convergence (i.e., CF(z1, z2, . . . , zN) does not reduce any further) or a preset number of iterations is reached.
Specifically, in the i-th iteration, in the vicinity of (z1i, z2i, . . . , zNi),
Under the approximation of Eq. 3, the cost function becomes:
which is a quadratic function of the design variables (z1, z2, . . . , zN). Every term is constant except the design variables (z1, z2, . . . , zN).
If the design variables (z1, z2, . . . , zN) are not under any constraints, (z1(i+1), z2(i+1), . . . , zN(i+1)) can be derived by solving N linear equations:
wherein n=1, 2, . . . , N.
If the design variables (z1, z2, . . . , zN) are under constraints in the form of J inequalities (e.g. tuning ranges of (z1, z2, . . . , zN)) Σn=1N Anjzn≤Bj, for j=1, 2, . . . , J; and K equalities (e.g. interdependence between the design variables) Σn=1N Cnkzn≤Dk, for k=1, 2, . . . , K, the optimization process becomes a classic quadratic programming problem, wherein Anj, Bj, Cnk, Dk are constants. Additional constraints can be imposed for each iteration. For example, a “damping factor” ΔD, can be introduced to limit the difference between (z1(i+1), z2(i+1), . . . , zN(i+1)) and (z1i, z2i, . . . , zNi), so that the approximation of Eq. 3 holds. Such constraints can be expressed as zni−ΔD≤zn≤zni+ΔD. (z1(i+1), z2(i+1), . . . , zN(i+1)) can be derived using, for example, methods described in Numerical Optimization (2nd ed.) by Jorge Nocedal and Stephen J. Wright (Berlin New York: Vandenberghe. Cambridge University Press).
Instead of minimizing the RMS of fp (z1, z2, . . . , zN), the optimization process can minimize magnitude of the largest deviation (the worst defect) among the evaluation points to their intended values. In this approach, the cost function can alternatively be expressed as
wherein CLp is the maximum allowed value for fp (z1, z2, . . . , zN). This cost function represents the worst defect among the evaluation points. Optimization using this cost function minimizes magnitude of the worst defect. An iterative greedy algorithm can be used for this optimization.
The cost function of Eq. 5 can be approximated as:
wherein q is an even positive integer such as at least 4, or at least 10. Eq. 6 mimics the behavior of Eq. 5, while allowing the optimization to be executed analytically and accelerated by using methods such as the deepest descent method, the conjugate gradient method, etc.
Minimizing the worst defect size can also be combined with linearizing of fp (z1, z2, . . . , zN). Specifically, fp(z1, z2, . . . , zN) is approximated as in Eq. 3. Then the constraints on worst defect size are written as inequalities ELp≤fp(z1, z2, . . . , zN)≤EUp, wherein ELp and EUp, are two constants specifying the minimum and maximum allowed deviation for the fp (z1, z2, . . . , zN). Plugging Eq. 3 in, these constraints are transformed to, for p=1, . . . P,
Since Eq. 3 is generally valid only in the vicinity of (z1, z2, . . . , zN), in case the desired constraints ELp≤fp(z1, z2, . . . , zN)≤EUp cannot be achieved in such vicinity, which can be determined by any conflict among the inequalities, the constants ELp and EUp can be relaxed until the constraints are achievable. This optimization process minimizes the worst defect size in the vicinity of (z1, z2, . . . , zN), i. Then each step reduces the worst defect size gradually, and each step is executed iteratively until certain terminating conditions are met. This will lead to optimal reduction of the worst defect size.
Another way to minimize the worst defect is to adjust the weight wp in each iteration. For example, after the i-th iteration, if the r-th evaluation point is the worst defect, wr can be increased in the (i+1)-th iteration so that the reduction of that evaluation point's defect size is given higher priority.
In addition, the cost functions in Eq. 4 and Eq. 5 can be modified by introducing a Lagrange multiplier to achieve compromise between the optimization on RMS of the defect size and the optimization on the worst defect size, i.e.,
where λ is a preset constant that specifies the trade-off between the optimization on RMS of the defect size and the optimization on the worst defect size. In particular, if λ=0, then this becomes Eq. 4 and the RMS of the defect size is only minimized; while if λ=1, then this becomes Eq. 5 and the worst defect size is only minimized; if 0<λ<1, then both are taken into consideration in the optimization. Such optimization can be solved using multiple methods. For example, the weighting in each iteration may be adjusted, similar to the one described previously. Alternatively, similar to minimizing the worst defect size from inequalities, the inequalities of Eq. 6′ and 6″ can be viewed as constraints of the design variables during solution of the quadratic programming problem. Then, the bounds on the worst defect size can be relaxed incrementally or increase the weight for the worst defect size incrementally, compute the cost function value for every achievable worst defect size, and choose the design variable values that minimize the total cost function as the initial point for the next step. By doing this iteratively, the minimization of this new cost function can be achieved.
Optimizing a lithographic projection apparatus can expand the process window. A larger process window provides more flexibility in process design and chip design. The process window can be defined as, for example, a set of focus, dose, aberration, laser bandwidth (e.g., E95 or (λ min to λ max) and fare specific to intensity values for which the resist image is within a certain limit of the design target of the resist image. Note that all the methods discussed here may also be extended to a generalized process window definition that can be established by different or additional base parameters than exposure dose and defocus. These may include, but are not limited to, optical settings such as NA, sigma, aberration, polarization, or an optical constant of the resist layer. For example, as described earlier, if the process window (PW) also comprises different patterning device pattern bias (mask bias), then the optimization includes the minimization of Mask Error Enhancement Factor (MEEF), which is defined as the ratio between the substrate edge placement error (EPE) and the induced patterning device pattern edge bias. The process window defined on focus and dose values only serve as an example in this disclosure.
A method of maximizing a process window using, for example, dose and focus as its parameters, according to an embodiment, is described below. In a first step, starting from a known condition (f0, ε0) in the process window, wherein f0 is a nominal focus and ε0 is a nominal dose, minimizing one of the cost functions below in the vicinity (f0±Δf, ε0±ε):
If the nominal focus f0 and nominal dose ε0 are allowed to shift, they can be optimized jointly with the design variables (z1, z2, . . . , zN). In the next step, (f0±Δf, ε0±ε) is accepted as part of the process window, if a set of values of (z1, z2, . . . , zN, f, ε) can be found such that the cost function is within a preset limit.
If the focus and dose are not allowed to shift, the design variables (z1, z2, . . . , zN) are optimized with the focus and dose fixed at the nominal focus f0 and nominal dose ε0. In an alternative embodiment. (f0±Δf, ε0±ε) is accepted as part of the process window, if a set of values of (z1, z2, . . . , zN) can be found such that the cost function is within a preset limit.
The methods described earlier in this disclosure can be used to minimize the respective cost functions of Eqs. 7, 7′, or 7″. If the design variables represent one or more characteristics of the projection optics, such as the Zernike coefficients, then minimizing the cost functions of Eqs. 7, 7′, or 7″ leads to process window maximization based on projection optics optimization, i.e., LO. If the design variables represent one or more characteristics of the illumination and patterning device in addition to those of the projection optics, then minimizing the cost function of Eqs. 7, 7′, or 7″ leads to process window maximizing based on SMLO, as illustrated in
The method starts by defining the pixel groups of the illumination and the patterning device tiles of the patterning device (step S802). Generally, a pixel group or a patterning device tile may also be referred to as a division of a lithographic process component. In one exemplary approach, the illumination is divided into 117 pixel groups, and 94 patterning device tiles are defined for the patterning device, substantially as described above, resulting in a total of 211 divisions.
In step S804, a lithographic model is selected as the basis for lithographic simulation. A lithographic simulation produces results that are used in calculations of one or more lithographic metrics, or responses. A particular lithographic metric is defined to be the performance metric that is to be optimized (step S806). In step S808, the initial (pre-optimization) conditions for the illumination and the patterning device are set up. Initial conditions include initial states for the pixel groups of the illumination and the patterning device tiles of the patterning device such that references may be made to an initial illumination shape and an initial patterning device pattern. Initial conditions may also include patterning device pattern bias (sometimes referred to as mask bias), NA, and/or focus ramp range. Although steps S802, S804, S806, and S808 are depicted as sequential steps, it will be appreciated that in other embodiments, these steps may be performed in other sequences.
In step S810, the pixel groups and patterning device tiles are ranked. Pixel groups and patterning device tiles may be interleaved in the ranking. Various ways of ranking may be employed, including: sequentially (e.g., from pixel group 1 to pixel group 117 and from patterning device tile 1 to patterning device tile 94), randomly, according to the physical locations of the pixel groups and patterning device tiles (e.g., ranking pixel groups closer to the center of the illumination higher), and/or according to how an alteration of the pixel group or patterning device tile affects the performance metric.
Once the pixel groups and patterning device tiles are ranked, the illumination and patterning device are adjusted to improve the performance metric (step S812). In step S812, each of the pixel groups and patterning device tiles are analyzed, in order of ranking, to determine whether an alteration of the pixel group or patterning device tile will result in an improved performance metric. If it is determined that the performance metric will be improved, then the pixel group or patterning device tile is accordingly altered, and the resulting improved performance metric and modified illumination shape or modified patterning device pattern form the baseline for comparison for subsequent analyses of lower-ranked pixel groups and patterning device tiles. In other words, alterations that improve the performance metric are retained. As alterations to the states of pixel groups and patterning device tiles are made and retained, the initial illumination shape and initial patterning device pattern changes accordingly, so that a modified illumination shape and a modified patterning device pattern result from the optimization process in step S812.
In other approaches, patterning device polygon shape adjustments and pairwise polling of pixel groups and/or patterning device tiles are also performed within the optimization process of S812.
In an embodiment, the interleaved simultaneous optimization procedure may include altering a pixel group of the illumination and if an improvement of the performance metric is found, the dose or intensity is stepped up and/or down to look for further improvement. In a further embodiment, the stepping up and/or down of the dose or intensity may be replaced by a bias change of the patterning device pattern to look for further improvement in the simultaneous optimization procedure.
In step S814, a determination is made as to whether the performance metric has converged. The performance metric may be considered to have converged, for example, if little or no improvement to the performance metric has been witnessed in the last several iterations of steps S810 and S812. If the performance metric has not converged, then the steps of S810 and S812 are repeated in the next iteration, where the modified illumination shape and modified patterning device from the current iteration are used as the initial illumination shape and initial patterning device for the next iteration (step S816).
The optimization methods described above may be used to increase the throughput of the lithographic projection apparatus. For example, the cost function may include a fp (z1, z2, . . . , zN) that is a function of the exposure time. In an embodiment, optimization of such a cost function is constrained or influenced by a measure of the bandwidth or other metric.
Computer system 100 may be coupled via bus 102 to a display 112, such as a cathode ray tube (CRT) or flat panel or touch panel display for displaying information to a computer user. An input device 114, including alphanumeric and other keys, is coupled to bus 102 for communicating information and command selections to processor 104. Another type of user input device is cursor control 116, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor 104 and for controlling cursor movement on display 112. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), that allows the device to specify positions in a plane. A touch panel (screen) display may also be used as an input device.
According to one embodiment, portions of the optimization process may be performed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. Such instructions may be read into main memory 106 from another computer-readable medium, such as storage device 110. Execution of the sequences of instructions contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory 106. In an alternative embodiment, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.
The term “computer-readable medium” as used herein refers to any medium that participates in providing instructions to processor 104 for execution. Such a medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 110. Volatile media include dynamic memory, such as main memory 106. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 102. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read.
Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may initially be borne on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system 100 can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to bus 102 can receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries the data to main memory 106, from which processor 104 retrieves and executes the instructions. The instructions received by main memory 106 may optionally be stored on storage device 110 either before or after execution by processor 104.
Computer system 100 may also include a communication interface 118 coupled to bus 102. Communication interface 118 provides a two-way data communication coupling to a network link 120 that is connected to a local network 122. For example, communication interface 118 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 118 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface 118 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.
Network link 120 typically provides data communication through one or more networks to other data devices. For example, network link 120 may provide a connection through local network 122 to a host computer 124 or to data equipment operated by an Internet Service Provider (ISP) 126. ISP 126 in turn provides data communication services through the worldwide packet data communication network, now commonly referred to as the “Internet” 128. Local network 122 and Internet 128 both use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on network link 120 and through communication interface 118, which carry the digital data to and from computer system 100, are exemplary forms of carrier waves transporting the information.
Computer system 100 can send messages and receive data, including program code, through the network(s), network link 120, and communication interface 118. In the Internet example, a server 130 might transmit a requested code for an application program through Internet 128, ISP 126, local network 122 and communication interface 118. One such downloaded application may provide for the illumination optimization of the embodiment, for example. The received code may be executed by processor 104 as it is received, and/or stored in storage device 110, or other non-volatile storage for later execution. In this manner, computer system 100 may obtain application code in the form of a carrier wave.
As depicted herein, the apparatus is of a transmissive type (i.e., has a transmissive patterning device). However, in general, it may also be of a reflective type, for example (with a reflective patterning device). The apparatus may employ a different kind of patterning device to classic mask; examples include a programmable mirror array or LCD matrix.
The source SO (e.g., a mercury lamp or excimer laser, LPP (laser produced plasma) EUV source) produces a beam of radiation. This beam is fed into an illumination system (illuminator) IL, either directly or after having traversed conditioning means, such as a beam expander Ex, for example. The illuminator IL may comprise adjusting means AD for setting the outer and/or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, it will generally comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam B impinging on the patterning device MA has a desired uniformity and intensity distribution in its cross-section.
It should be noted with regard to
The beam PB subsequently intercepts the patterning device MA, which is held on a patterning device table MT. Having traversed the patterning device MA, the beam B passes through the lens PL, which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning means (and interferometric measuring means IF), the substrate table WT can be moved accurately, e.g., so as to position different target portions C in the path of the beam PB. Similarly, the first positioning means can be used to accurately position the patterning device MA with respect to the path of the beam B. e.g., after mechanical retrieval of the patterning device MA from a patterning device library, or during a scan. In general, movement of the object tables MT, WT will be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which are not explicitly depicted in
The depicted tool can be used in two different modes:
The lithographic projection apparatus 1000 comprises:
As here depicted, the apparatus 1000 is of a reflective type (e.g., employing a reflective patterning device). It is to be noted that because most materials are absorptive within the EUV wavelength range, the patterning device may have multilayer reflectors comprising, for example, a multi-stack of Molybdenum and Silicon. In one example, the multi-stack reflector has a 40 layer pairs of Molybdenum and Silicon where the thickness of each layer is a quarter wavelength. Even smaller wavelengths may be produced with X-ray lithography. Since most material is absorptive at EUV and x-ray wavelengths, a thin piece of patterned absorbing material on the patterning device topography (e.g., a TaN absorber on top of the multi-layer reflector) defines where features would print (positive resist) or not print (negative resist).
Referring to
In such cases, the laser is not considered to form part of the lithographic apparatus and the radiation beam is passed from the laser to the source collector module with the aid of a beam delivery system comprising, for example, suitable directing mirrors and/or a beam expander. In other cases, the source may be an integral part of the source collector module, for example when the source is a discharge produced plasma EUV generator, often termed as a DPP source.
The illuminator IL may comprise an adjuster for adjusting the angular intensity distribution of the radiation beam. Generally, at least the outer and/or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator can be adjusted. In addition, the illuminator IL may comprise various other components, such as facetted field and pupil mirror devices. The illuminator may be used to condition the radiation beam, to have a desired uniformity and intensity distribution in its cross section.
The radiation beam B is incident on the patterning device (e.g., mask) MA, which is held on the support structure (e.g., patterning device table) MT, and is patterned by the patterning device. After being reflected from the patterning device (e.g., mask) MA, the radiation beam B passes through the projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of the second positioner PW and position sensor PS2 (e.g., an interferometric device, linear encoder or capacitive sensor), the substrate table WT can be moved accurately, e.g., so as to position different target portions C in the path of the radiation beam B. Similarly, the first positioner PM and another position sensor PS1 can be used to accurately position the patterning device (e.g., mask) MA with respect to the path of the radiation beam B. Patterning device (e.g., mask) MA and substrate W may be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1. P2.
The depicted apparatus 1000 could be used in at least one of the following modes:
The radiation emitted by the hot plasma 210 is passed from a source chamber 211 into a collector chamber 212 via an optional gas barrier or contaminant trap 230 (in some cases also referred to as contaminant barrier or foil trap) which is positioned in or behind an opening in source chamber 211. The contaminant trap 230 may include a channel structure. Contamination trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. The contaminant trap or contaminant barrier 230 further indicated herein at least includes a channel structure, as known in the art.
The collector chamber 211 may include a radiation collector CO which may be a so-called grazing incidence collector. Radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation that traverses collector CO can be reflected off a grating spectral filter 240 to be focused on a virtual source point IF along the optical axis indicated by the dot-dashed line ‘O’. The virtual source point IF is commonly referred to as the intermediate focus, and the source collector module is arranged such that the intermediate focus IF is located at or near an opening 221 in the enclosing structure 220. The virtual source point IF is an image of the radiation emitting plasma 210.
Subsequently the radiation traverses the illumination system IL, which may include a facetted field mirror device 22 and a facetted pupil mirror device 24 arranged to provide a desired angular distribution of the radiation beam 21, at the patterning device MA, as well as a desired uniformity of radiation intensity at the patterning device MA. Upon reflection of the beam of radiation 21 at the patterning device MA, held by the support structure MT, a patterned beam 26 is formed and the patterned beam 26 is imaged by the projection system PS via reflective elements 28, 30 onto a substrate W held by the substrate table WT.
More elements than shown may generally be present in illumination optics unit IL and projection system PS. The grating spectral filter 240 may optionally be present, depending upon the type of lithographic apparatus. Further, there may be more mirrors present than those shown in the figures, for example there may be 1-6 additional reflective elements present in the projection system PS than shown in
Collector optic CO, as illustrated in
Alternatively, the source collector module SO may be part of an LPP radiation system as shown in
The concepts disclosed herein may simulate or mathematically model any generic imaging system for imaging sub wavelength features and may be especially useful with emerging imaging technologies capable of producing increasingly shorter wavelengths. Emerging technologies already in use include EUV (extreme ultra-violet), DUV lithography that is capable of producing a 193 nm wavelength with the use of an ArF laser, and even a 157 nm wavelength with the use of a Fluorine laser. Moreover, EUV lithography is capable of producing wavelengths within a range of 20-5 nm by using a synchrotron or by hitting a material (either solid or a plasma) with high energy electrons in order to produce photons within this range.
Embodiments of the present disclosure can be further described in the following clauses.
While the concepts disclosed herein may be used for imaging on a substrate such as a silicon wafer, it shall be understood that the disclosed concepts may be used with any type of lithographic imaging systems, e.g., those used for imaging on substrates other than silicon wafers.
The descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made as described without departing from the scope of the claims set out below.
This application claims priority of U.S. application 63/192,878 which was filed on May 25, 2021 and which is incorporated herein in its entirety by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/EP2022/062691 | 5/10/2022 | WO |
Number | Date | Country | |
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63192878 | May 2021 | US |