Patent Application
20130059241
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-195210, filed Sep. 7, 2011, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a development processing method and development processing apparatus for subjecting a resist film on which a desired pattern is exposed to a development process.
Recently, attention is paid to EUV lithography using exposure light of a wavelength region (extreme ultraviolet [EUV]) having the wavelength of 13.5 nm at the center thereof. A mask used in the EUV lithography has a structure obtained by forming an absorption pattern on a multi-layered reflecting film (mask blanks) that has two types of layers with different reflectances alternately laminated on a glass substrate.
In order to form an EUV exposure mask, a mask blanks substrate having a light-shielding film (to-be-processed film) as an absorber formed on a multi-layered reflecting film is used. A resist pattern is formed by exposing a resist film coated on the mask blanks substrate in a desired pattern by use of an electron beam and subjecting the same to a development process. Then, the light-shielding film is selectively etched with the resist pattern used as a mask. Therefore, if a fault is present in the resist pattern, a fault will occur in the pattern of the EUV exposure mask.
At the formation time of the EUV exposure mask, an extremely thin poor solubility thin film may occur on the surface of the resist film in some cases. Since the poor solubility thin film is extremely thin, the film may be twisted or broken because of a flow of a developing solution during the development process. The broken poor solubility thin film may move in the developing solution, may be caught on a resist film in a different location and adhered thereto. At this time, the film changes the pattern dimension and degrades line edge roughness (LER). In the worst case, a pattern fault may occur.
In general, according to one embodiment, a monitor pattern is previously exposed together with a device pattern on a resist film, the monitor pattern is developed in a first development condition and a fault occurrence risk is quantified based on a check image obtained by checking the developed monitor pattern. At this time, the range of a second development condition in which the number of faults becomes less than or equal to a permissible value with respect to the quantified fault occurrence risk is determined based on the relationship between fault occurrence risk information and the number of faults for different development conditions previously acquired. Then, a third development condition in which the pattern dimension becomes a desired value in the second development condition is determined and the device pattern is developed in the thus determined third development condition.
It is understood based on the study by the inventor of this application and others that the probability of occurrence of the poor solubility thin film described above varies depending on post-coating delay (PCD, the deferment time after coating), exposure condition dependency including a fogging effect caused by a difference in the optical system of an electron beam (EB) exposure apparatus, a post-exposure baking (PEB) condition of PEB temperature, time and the like and a development condition of development time, temperature and the like.
Further, the following development technique is studied to optimize the development condition. A resist-sensitive monitor pattern is arranged on a region of a to-be-processed substrate surface other than a main pattern region, for example, on an edge portion thereof. Only the monitor pattern portion is previously developed and information related to the resist sensitivity is acquired from the monitor pattern portion. Then, a development condition suitable for the thus acquired resist sensitivity is feed-forwarded. In this method, the dimension can be controlled by quantifying the dimension variation risk such as the resist sensitivity before developing the main pattern. However, it is difficult to previously quantify the risk for a fault that is another large control item.
Based on the experiments by the inventor of this application and others, it is understood that something that becomes a source of the fault is already known in the course of development and it is understood that the fault risk can be measured. In the mask substrate, a region used for wafer exposure is limited and a region in which dimension control and fault control are required and a region in which such control is not required are provided. Therefore, a fault risk determination monitor pattern is arranged in the region in which the dimension control and fault control are required and a pattern obtained by developing the above pattern is checked. As a result, the fault risk can be quantified. The present embodiment is to optimize the development processing condition based on the above fact.
Next, the development processing method and development processing apparatus of this embodiment are explained with reference to the drawings.
In this embodiment, a case wherein an EUV mask is formed is explained as an example.
A multi-layered reflecting film and light-shielding film are formed on the surface of a substrate with the low coefficient of thermal expansion such as glass and a photosensitive thin film (resist film) is coated thereon. The resist film is exposed by means of an electron-beam drawing apparatus. After this, PEB is performed to form a latent image in the resist film. On the edge portion of the substrate, a fault risk determination monitor pattern and resist-sensitive monitor pattern are arranged. In this example, as the fault risk determination monitor pattern, an extraction pattern of 1 mm is used.
As shown in
Next, as shown in
Next, an image of the monitor pattern is acquired by photographing the half-dissolved fault risk determination monitor pattern 30 by means of a CCD camera or the like. Examples of images obtained at this time are shown in
It is considered that the fault occurrence risk varies in proportion to the area of the poor solubility thin film. Therefore, the fault occurrence risk can be quantified with high precision by calculating the area of the poor solubility thin film on the monitor pattern based on the image obtained by means of a CCD camera or the like.
Determination of the normal portion and abnormal portion at this time is performed as follows. That is, a substrate for testing that is the same as a substrate used for actually forming a mask is previously prepared, a fault risk determination monitor pattern 30 is half-dissolved on the above substrate and the luminance of each pixel is calculated. Then, after development of the resist and etching of the substrate, the fault checking process is finally performed on the entire surface of a mask. Thus, correlation data of the area of the abnormal portion or the size of a fault and the number of faults is acquired. The data items are acquired in plural development conditions (development conditions A, B, C). As shown in
The permissible range of the development condition of the device region 21 that requires the dimension control and fault control is determined based on the relationship between the total area of the abnormal portions obtained when the fault risk determination monitor pattern 30 is half-dissolved, information such as permissible fault specifications and the graphs shown in
Next, a third development condition in which desired pattern dimension is obtained is further selected in the range of the second development condition. Specifically, a development processing condition in which the pattern is finished with desired dimension can be attained by determining the state of resist-sensitive monitor pattern and acquiring sensitivity information of the resist film 11 before the development process. The third development condition that satisfies both of the above condition and the second development condition is set. Then, as shown in
The thus obtained pattern is checked and then it can be confirmed that the number of faults is reduced while the absolute value of the dimension of the resist pattern is suppressed within desired specifications.
In the feed-forward development method using the fault risk determination monitor pattern of this embodiment, several desired forms are present. In this embodiment, the extraction pattern is used as the fault risk determination monitor pattern, but other types of patterns of lines-and-spaces, isolated lines, isolated spaces and the like may be used instead of this pattern. Further, this can be attained by adequately selecting the magnification of a CCD camera used for observing the pattern size, monitor pattern and the like.
In the first development condition, the degree of dissolution may be sufficient if all of the resist film is not dissolved. Preferably, the dissolution amount that permits the fault risk to be highly sensitively monitored may be selected by changing the degree of dissolution.
Further, as the method for processing a portion of the substrate on which the resist film is coated, any type of method can be used.
The second development condition may be sufficient if the development condition can be changed by selecting a parameter that can change the dissolving characteristic of the resist film such as the development time, developing solution temperature, substrate temperature and the like.
Further, a mask that has less faults and in which desired lithography likelihood is attained can be formed by selecting a range in which the likelihood at the time of transfer of the mask pattern to the wafer can be attained as the permissible range of the development condition. In order to realize this, it is possible to previously acquire the relationship between the development condition and the pattern dimension and the relationship between the pattern dimension and the lithography likelihood and store the same as an internal table. In this case, the likelihood is the so-called lithography likelihood (the likelihood that causes the pattern dimension to be set in desired pattern dimension on the wafer when the exposure amount, focus or the like is changed).
Thus, according to this embodiment, the fault risk determination monitor pattern 30 is provided in the monitor region 22 formed around the device region 21. Then, the fault risk determination monitor pattern 30 is developed before the original development process and a development condition is set based on the contrast obtained at this time. As a result, the development process in which not only the pattern is controlled to desired dimension but also the fault occurrence can be suppressed can be performed. That is, an attempt can be made to control the resist pattern to the desired dimension and reduce the number of faults. Further, since the fault risk determination monitor pattern 30 is formed in the monitor region 22 that does not require the dimension control and fault control, no bad influence is given to the device region 21 in the process for determining the development condition of the device region 21.
Next, a different example of forming an EUV mask is explained.
Like the first embodiment, a substrate having a multi-layered reflecting film and light-shielding film formed on the surface thereof and a resist film coated thereon is exposed by means of an electron-beam drawing apparatus. Then, PEB is performed to form a latent image in the resist film. Since the process flow diagram is the same as that shown in
First, a partial region on the substrate having a monitor region 22 formed thereon is subjected to a development process in a first development condition in which a resist film 11 is approximately half-dissolved. At this time, the development process for a device region 21 that requires the dimension control and fault control is not performed. Next, an image of the monitor pattern is acquired by photographing a half-dissolved fault risk determination monitor pattern 30 by means of a CCD camera. At this time, since the dissolving speed is different depending on the location in the fault risk determination monitor pattern 30, contrast occurs because of a difference in the resist film thickness. A normal portion and abnormal portion are separated based on the acquired contrast and the total area of the abnormal portion is calculated.
Further, the correlation data of the number of faults and the area (fault risk) of the previously acquired abnormal portion is acquired. The correlated data is acquired in each of plural rinsing conditions (more specifically, rinsing conditions and drying conditions) and the correlated data is formed in a table form or graph form as shown in
Next, after a development condition in which the desired pattern dimension is obtained is selected and the development process for the device region 21 that requires the dimension control and fault control is performed, the rinsing process is performed. In this rinsing process, rinsing condition A in which the number of faults is set to a permissible value is selected based on the calculated area of the abnormal portion and the tables shown in
The thus obtained pattern is checked and then it can be confirmed that the number of faults is reduced while the absolute value of the dimension of the resist pattern is suppressed within desired specifications.
Thus, according to this embodiment, the fault risk determination monitor pattern 30 is provided in the monitor region 22 formed around the device region 21. Then, the fault risk determination monitor pattern is developed before the original development process and the rinsing condition is set based on the contrast obtained at this time. As a result, the rinsing process in which not only the pattern is controlled to desired dimension but also the fault occurrence is reduced can be performed. Therefore, the same effect as that of the first embodiment can be attained.
A substrate 10 that is coated with a resist film and on which a desired pattern is exposed is placed on a stage that is not shown in the drawing. An auxiliary plate 51 used for reducing the step difference of a substrate edge portion is placed on the peripheral portion of the substrate 10. In this state, a nozzle head 60 is scanned on the surface of the substrate 10.
The nozzle head 60 includes a developing solution supply unit 61 used for supplying a developing solution, cleaning solution supply units 62a, 62b used for supplying cleaning solutions and discharge units 63a, 63b used for discharging the developing solution and cleaning solution. The respective units have slit-like openings formed along the lengthwise direction of the nozzle head 60 in the undersurface of the nozzle head 60. That is, the developing solution supply unit 61 is connected to a slit-like developing solution supply port 81 formed in the central portion of the undersurface of the nozzle head 60 and the discharge units 63a, 63b are respectively connected to discharge ports 83a, 83b provided on both sides of the developing solution supply port. Further, the cleaning solution supply units 62a, 62b are respectively connected to slit-like cleaning solution supply ports 82a, 82b provided outside the discharge ports 83a, 83b.
As shown in
In this embodiment, the following three mechanisms 91 to 93 are provided in addition to the above structure. In the first mechanism (quantifying unit) 91, a pattern obtained by selectively developing the monitor region 22 is checked by use of a CCD camera 94 or the like and a fault occurrence risk is quantified based on the check result. The development condition (first development condition) at this time is a condition in which the resist film is half-dissolved. In the second mechanism (second development condition calculation unit) 92, a development condition (second development condition) in which the number of faults becomes less than or equal to a permissible value at the time of the quantified fault occurrence risk is calculated based on the relationship (fault risk table) 95 between the fault occurrence risk information and the number of faults and between the number of faults and the development condition. In the third mechanism (third development condition determination unit) 93, a development condition (third development condition) in which the pattern dimension becomes a desire value in the calculated development condition is determined.
By using this apparatus, the device region 21 and monitor region 22 can be independently subjected to the development process. The fault occurrence risk can be quantified by checking a pattern obtained by selectively developing the monitor region 22 by use of a CCD camera or the like. Then, a development condition in which the number of faults becomes less than or equal to a permissible value with respect to the quantified fault occurrence risk can be calculated based on the relationship between the number of faults and fault occurrence risk information with respect to different development conditions previously formed in the table form. Further, the development process as in the first embodiment described before can be performed by determining a development condition in which the pattern dimension becomes the desired value in the calculated development condition.
Therefore, in this embodiment, the same effect as that of the first embodiment can be attained. Further, in this embodiment, since the nozzle head 60 as shown in
This invention is not limited to the above embodiments. In the above embodiments, the EUV exposure mask is explained as an example, but the mask is not limited to the EUV exposure mask and various masks can be used. Further, the process is not necessarily limited to the mask development process and can be applied to a process if resist formed on the substrate is developed.
Further, the apparatus configuration for performing the development process is not necessarily limited to the configuration shown in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-195210 | Sep 2011 | JP | national |
