Patent Application
20090040082
This application claims foreign priority benefits under 35 U.S.C. § 119 to co-pending German patent application number DE 10 2007 035 018.1-31, filed 26 Jul. 2007. This related patent application is herein incorporated by reference in its entirety.
The invention generally relates to devices for processing binary data, and more particularly, converting serial data bit streams into a parallel format.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Embodiments of the present invention relate to a device for processing binary data, comprising at least one transmission link which or each of which is arranged between a data source and an individually allocated data sink in order to convert a serial data bit stream, supplied by the source, into a sequence of n-bit data words in parallel format and to supply this sequence to the data sink.
Embodiments of the invention provide a transmission of data which are supplied as serial bit streams with a very high data rate (i.e. in the range of one or more Gigabits/second) by a memory controller, to a storage medium, e.g. to an integrated or DRAM chip or to storage modules which in each case contain a number of such chips.
A transmission link between data source, e.g. a controller and data sink, e.g. a DRAM, may exhibit a low latency. In other words, the time between the reception of the serial data at the input of the link and the arrival of the data as serial/parallel converted data words at the data sink should be short.
According to an embodiment, a device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format, and
a serial/parallel converter providing n≧2 successive data bits of the serial bit stream as n-bit data words in the parallel format. The serial/parallel converter comprises a 1-to-n demultiplexer which is constructed and controllable in such a manner that the successive data bits of the serial bit stream appear in succession at intervals equal to a bit period TB cyclically at n data outputs and remain latched at the respective data output until a data bit appears again at the relevant data output and a relatching circuit with latching elements which receive the signals from the data outputs of the demultiplexer at which the first k data bits of each cycle appear and which are enabled in each case at a time which is between the beginning of the latching of the last data bit and the end of the latching of the first data bit of the relevant cycle in the demultiplexer, wherein 1≦k<n.
According to a further embodiment, a device for processing binary data comprising at least one transmission link. The transmission link comprises a serial/parallel converter converting n≧2 successive data bits of a serial bit stream as n-bit data words in the parallel format as frames and a buffer circuit. The buffer circuit comprises a FIFO register and receives at its input the frames of the serial/parallel converter, wherein a write pointer of the buffer circuit is controlled by a first frame clock and a read pointer of the buffer circuit is controlled by a second frame clock, and wherein the FIFO register is bridged by a bypass when the read pointer and the write pointer come close to one another.
According to a further embodiment, a device for processing binary data comprises at least one transmission link having an input for receiving a serial bit stream and an output for forwarding bits in a parallel format and a serial/parallel converter converting n≧2 successive data bits of a serial bit stream as n-bit data words in the parallel format as frames. The transmission link further comprises a delay device, the delay time of which can be varied in increments of in each case one frame period TF.
According to a further embodiment, a device for processing binary data comprises at least two transmission links. Each transmission link has an input for receiving a serial bit stream and an output for forwarding bits in a parallel format and a serial/parallel converter converting n≧2 successive data bits of a serial bit stream as n-bit data words in the parallel format as frames. Further each transmission link is arranged between an individually allocated output of a data source and an individually allocated data sink, wherein the clock signal for the clock control of the data reception at all data sinks is a common clock signal.
In the figures and in the subsequent description, identical and similar elements are in each case designated by the same reference symbols, in most cases together with a following alphanumeric signal (decimal number or small letter) which specifies a sequence number for the more detailed identification of the relevant element, the symbol “i” denoting an arbitrary sequence number. A colon “:” between two numbers is in each case to be read as the word “to”. Depending on context, the “ . . . ” symbol can be read as “to” or “and following”.
In
The transmission link may ensure that successive sections (frames) of in each case n bits of the serial bit stream are applied to the n-bit parallel input of the data sink 300 as successive n-bit words in parallel format, in accordance with a frame clock, the period (frame period) of which is equal to n-times the bit period TB of the serial bit stream. That is to say, the frame clock has the frequency fF=1/(n*TB).
Thus, a serial/parallel conversion may take place in the transmission link 200. In one embodiment, the transmission link may contain a 1-to-n demultiplexer 20 which samples the n successive data bits of each frame of the serial bit stream by means of active edges of an input clock signal CLB and provides n associated output lines of the demultiplexer 20.
The transit time of the bit stream from the source 100 to the input X of the transmission link 200 may be dependent on the physical characteristics of the data line 110. The length, the specific electrical parameters and also the type of installation of the line contribute to these characteristics, as do the respective environmental influences. Since the complex of all line characteristics, and thus also the transit time, cannot be accurately predicted and can also fluctuate within a certain tolerance range during operation, an input circuit 10 may be connected ahead of the demultiplexer 20. As shown, the circuit 10 (a so-called data clock recovery circuit) contains a phase locked loop 11 which receives the input bit stream CBS and the system clock signal CLS and generates at its output the input clock signal CLB and the serial bit stream SBS relative to one another with a phase relationship which is suitable for a reliable sampling of the data bits of the serial bit stream.
The actual serial/parallel conversion in the demultiplexer 20 may be effected by means of a group of n latch elements 22-1, 22-2 . . . 22-n and a write control circuit 23. Each of the latch elements may in each case be allocated to one of the n bits of each frame. In
For the more detailed explanation of the operation of the demultiplexer 20, reference will be made to
The first (top) line in
In the second line, the input clock signal CLB is shown which is derived from the system clock signal CLS by the synchronizing circuit 10. This circuit 10 may generate the input clock signal CLB with such a phase that the active edges, following one another with the period TB, of the input clock signal (in this case the rising edges) in each case appear at a time which remains within the validity period of a respective associated bit in every case, even if the phase of the serial bit stream shifts within certain tolerance limits, and also has a certain minimum distance both from the beginning and from the end of this validity period. Maintenance of these minimum distances may be necessary in view of the nature of the latch elements 22-1:4 because these elements may require a certain setup time τS before the clock edge and a certain holding time τH after the clock edge for their switching operation.
The appropriate setting of the relative phase between the input clock CLB and the serial bit stream SBS can be found during an initialization process via the phase locked loop 11 by incrementally changing the clock phase and monitoring the sampling quality. The steps of an initialization process by means of which other phase adjustments can also be carried out along the transmission link will be described at a later point. In
As shown, the write control circuit 23 receives the input clock signal CLB and has n=4 outputs, each of which is allocated to the enable input EN of an individually allocated latch element of the group 22-1:4. The write control circuit 23 may supply via its four outputs the enable inputs EN of the latch elements 22-1:4 selectively one after the other at the rate of the input clock signal in each case with an enable pulse EN of a certain duration. These enable pulses are shown in the next four lines of
The first bit of each frame, that is to say bit B1, may be sampled in the “first” latch element 22-1 and latched at its data output Q for the duration TF of the frame period. For this purpose, the write control circuit 23 may apply the “first” enable pulse EN1 of each cycle to the element 22-1 with a duration which, at the latest, begins at time tA1−τS and, at the earliest, ends at time tA1+τH, tA1 being the time of the active edge of the clock signal CLB for sampling the first bit B1. The beginning of the pulse EN1, however, may be later than time tA1−TB+τH and the end of the pulse may be earlier than time tA1+TB−τS. When all these conditions are met, it can be ensured that the latching process for bit B1 at data output Q of the latch element 22-1 begins at time tA1.
In the example shown according to
In the same manner as described above, the latching of the subsequent bits B2:4 of the current frame Fi in the latch elements 22-2:4 runs time-graded at intervals of in each case equal to TB with time-graded enabling of these elements by the enabling pulses EN2:4. The signal variations on the output lines DQ2:4 of the latch elements are also shown in the correspondingly designated lines of
The write control circuit 23 can contain a counter which is cyclically incremented with the frequency of the input clock signal CLB in each case over n=4 successive counts. The enabling pulse EN1 may be generated at the associated count output for the duration of the existence of the first count. The enabling pulse EN2 is generated for the duration of the existence of the second count at the associated count output, etc.
When the serial/parallel converter 20 is in normal operation, the cycles of the write control circuit 23 may be synchronized with the frames in such a manner that the first enabling pulse EN1 encounters the first bit of a frame of the serial bit stream SBS. This synchronization can be carried out by means of an initialization decoder 12 which is shown in
After valid latching of the last bit of each frame, that is to say bit B4 on line DQ4, the opportunity arises to sample all bits B1:4 simultaneously on the output lines DQ1:4 in order to forward them as 4-bit word in parallel format. This opportunity may exist during a time window τP, for as long as all n bits B1:4 of the respective same frame are simultaneously valid on the lines DQ1:4. In one embodiment of the invention, a sampling circuit (not shown) can be used for parallel sampling which responds to a frame clock signal which is derived from the input clock signal CLB and has active sampling edges within the time window τP.
The demultiplexer 20 shown in
The abovementioned time window τP for the parallel sampling of the bits B1:4 on lines DQ1:4 is relatively narrow and becomes ever more narrow the higher the frequency fB of the input clock is. The parallel sampling within this narrow window would require latch elements having extremely short setup and holding times; in addition, the latency would increase for the latest bit in each case.
In one embodiment of the invention, it is ensured by means of relatively simple measures that a wider time window is available for the parallel sampling and, nevertheless, the latency remains low. Generally said, this is achieved by relatching the k first bits B1:k (with 1≦k<n) from the output of the demultiplexer 20 within a circuit 30 at a time within a time interval which lies between the beginning of the validity of the k-th bit Bk and the end of the validity of the first bit B1. The bits B1:k then appear simultaneously at the outputs DQ′1:k of the latching circuit 31 from the said time, that is to say later than at the outputs DQ1:k of the demultiplexer 20, but with unchanged validity period. As a result, the time window for the parallel sampling of all n bits B1:n of one frame becomes much wider.
In the example shown, the (falling) trailing edges of the frame clock pulse are triggered by the trailing edge of the respective k-th enabling pulse EN2, they appear delayed by a short reaction time τR as shown in
In the example shown, the (rising) leading edges of the frame clock pulse CLF are triggered by the trailing edge of the respective k-th enabling pulse ENk, that is to say by the trailing edges of the enabling pulses EN2, and also appear delayed by the reaction time τR. This advantageously results in the duty ratio of 1/2 for the frame clock pulses, i.e. the trailing edges appear a half frame clock period later than the rising edges. As shown as example in
To provide a simple illustration of the exemplary case, a frame length of n=4 was described in the text above, and the number k=n/2 was selected for the number of “relatched” bits. In practice, e.g. if it is a matter of data transmission from or to storage modules, n will be much greater in most cases. The number k can also be greater or less than n/2. The advantage of the “relatching” described, namely the widened sampling window τP′ is obtained more or less with each number of 1≦k<n. The choice of k=n/2 is not mandatory but optimal. Naturally, such a choice is possible if n is an integral number which applies in most practical cases; otherwise the number (n+1)/2 or (n−1)/2 would be optimal for k.
Generally said, the k output lines DQ′1:k of the latch register 31 and the n-k output lines DQ(k+1):n of the demultiplexer 20 form a line group DF on which each frame in parallel format can be sampled within a relatively wide time window τP′. For this sampling, the edges, rising in the manner described above, of the frame clock pulse CLF can be used because these edges always appear within the said time window.
The reception of the frames at the data sink 300 may be clocked by a clock signal CLY which may be derived from the system clock signal CLS by a clock generator 310 according to
In practice, the frame clock coming from the demultiplexer 20 may not be synchronous with the frame clocking of the associated data sink 300. That is to say, the phase of the “sink frame clock” CLY can shift with respect to the phase of the “demultiplexer frame clock” CLF in unpredictable manner. For this reason, it may be advantageous to provide between the line group DF and the data input of the data sink a buffer circuit which is drawn as block 40 in
In an embodiment of the invention, the buffer circuit 40 contains a FIFO register which contains a multiplicity of q≧2 storage locations, each of which is designed for receiving the n data bits of a frame. A bypass bridges this FIFO register when the read pointer and the write pointer come close to one another. This allows the additional latency of the buffer circuit 40 in the data path to be reduced.
In an embodiment of the buffer circuit 40 which is shown in
As shown, the diagram according to
The four first lines of the top diagram section of
As shown, the buffer circuit 40 contains a write counter 41 which is controlled by the write clock signal CLF at its clock input C. The write counter 41 counts cyclically over in each case 2q−1=4 counts from 0 to 3 and contains two count decoders (not shown), one for coding these counts in binary number code “00”, “01”, “10”, “11” and one for coding in Gray code “00”, “01”, “11”, “10”. At a first output, the counter 41 supplies a 1-bit signal WRA which only reproduces the least significant bit (LSB, that is to say bit 20) of the binary number code. At a second output, the counter 41 supplies a 2-bit signal WRB which reproduces the two bits of the Gray code in parallel format.
A special feature of the buffer circuit 40 according to
As mentioned, the buffer circuit 40 contains two register stages 43A and 43B, each of which has an n-bit data input D for receiving the n-bit parallel words of the DF frame sequence and has a latch input L. Each of these register stages is of such a nature that it passes the data words received at the data input D to its data output Q as long as a latch signal received at the latch input is active, i.e. has the logic value “1”. As soon as the latch signal goes to its inactive logic value “0”, the currently received data word is latched for the duration of the active state of the latch signal at the data output Q.
The latch signal LTA for the register stage 43A are pulses which are generated in a gate 42A by AND combination of the inverted version of the output signal WRA of the write counter 41 with the frame clock signal CLF. The latch signal LTB for the register stage 43B are pulses which are generated in a gate 42B by AND combination of the output signal WRA of the write counter 41 with the frame clock signal CLF. The latch pulses LTA correspond to the pulses of the frame clock signal CLF which are allocated to the odd-numbered frames . . . Fi−1, Fi+1, Fi+3, . . . (“odd” frames), and the latch pulses LTB correspond to the pulses of the frame clock signal CLF which are allocated to the even-numbered frames . . . Fi−2, Fi, Fi+2, . . . (“even” frames). Thus, a frame sequence DFA which only contains the “odd” frames appears at the data output of register stage 43A and a frame sequence DFB which only contains the “even” frames appears at the data output of register stage 43B. The frame sequences DFA and DFB appear offset with respect to one another by one frame clock period TF and the validity period of the frames in these frame sequences is in each case longer than TF so that even and odd frames overlap in time.
The output signal WRA of the write counter 41, alternating between “0” and “1”, thus forms the write pointer for the two-stage register 43A, 43B via the AND gates 42A, 42B. To operate this register as a FIFO register, a first 2-to-1 multiplexer 44 is provided, the switching state of which is controlled by a read pointer RDA which is synchronized with the frame clock signal CLY of the data sink. Correspondingly, the clock signal CLY will also be called “read clock signal” in the text which follows. A read counter 45 is provided which is of the same configuration as the write counter 41 and is clocked by the rising edges of the read pulses CLY to count cyclically in each case from 0 to 3. The least significant bit of the binary number code of the count forms the read pointer RDA for controlling the multiplexer 44. At a logic value of “0” of the read counter RDA, the multiplexer 44 connects the DFA line group to its output and at a logic value of “1” of the read counter RDA, the multiplexer 44 connects the DFB line group to its output.
The FIFO multiplexer 44 thus supplies on its n-bit output line (line group DFC) a frame sequence DFC in which the individual frames . . . Fi, Fi+1, . . . appear in their original order but at the clock rate of the rising edges of the read clock signal CLY. This functions correctly as long as the read clock (rising edges of the read clock signal CLY) and the write clock (falling edges of the write clock signal CLF) are offset to one another by a minimum distance. Such a state, at which the rising edges of the read clock signal CLY and the falling edges of the write clock signal CLF are offset to one another by at least TF/2 is illustrated in the lines of the second diagram section in
If, however, the phases of write clock and read clock closely approach one another, a point is reached at which read/write operation is no longer possible. This point is defined by the transit time of the data from input DF of the buffer circuit 40 to the input D of the register 48 in relation to the phase relationship of the clock CLY. This transit time can be reduced further, and thus the latency of the buffer circuit 40 can be reduced further with the aid of a special measure. This measure consists in that a bypass is selectively switched in during certain intervals in order to temporarily bridge the FIFO register 43A, 43B in each case.
In the exemplary embodiment according to
The third diagram section of
Naturally, there is a minimum measure for the permissible distance between write clock and read clock. This minimum measure will be undershot as soon as the read clock comes so close to the write clock that it approaches the limit of the time window τP′ of the validity of the associated frame too much. The limit case in which the read clock just reaches the front boundary of the said time window is illustrated in the fourth diagram section of
As shown, the n-bit output signal of the bypass multiplexer 47 appearing on the line group DFD is supplied to the data input of an n-bit latch circuit 48 which is clocked with the rising edges of the read clock signal CLY in order to supply the output frame sequence DFE of the buffer circuit 40. In this sequence, the frames appear in their original order and synchronized with the frame clock CLY provided by the data sink 300.
The “length” of the FIFO register, that is to say the number q of the successively selected register stages can also be greater than 2. Generally it holds true that the write counter and the read counter must cyclically counter over in each case 2q counting steps (that is to say from 0 to 2q−1) and that the write pointer and the read pointer, respectively, are decoded from the counts for the cyclic addressing of the q register stages. The FIFO multiplexer is correspondingly a q-to-1 multiplexer.
By itself, the buffer circuit described can synchronize the frame sequence supplied by the multiplexer 20 in the frame clock CLF with the frame clock CLY of the data sink 300 only if the phase difference between the edges of identical polarity of the two frame clock signals CLF and CLY is no more than one frame clock period TF. This condition may be met in many cases.
However, it may occur that the phase difference between CLF and CLY is greater than TF. Such a situation can occur, e.g. if the transmission link is operated in parallel with other transmission links in order to supply a number of data sinks from the data source 100. The transit times of the data to the various sinks can differ because of different distances from the data source by such an extent that a difference of more than one frame period exists between the longest transit time and the shortest transit time. This difference can be a number of frame periods at very high data rates.
To equalize the said differences, an additional phase control may be carried out. In one embodiment of the invention, this may be achieved by a controllable delay circuit, the delay time of which can be varied in steps of in each case one whole frame period TF. An exemplary embodiment of this is shown in
In one embodiment, the delay circuit 50 according to
The 0 input of each change-over switch 53-i is connected to the data output of the immediately preceding delay element 52-i. The 1-inputs of the m−1 first change-over switch 53-1 to 53-(m−1) receive the frame sequence DFE from the output of the buffer circuit 40 (see
The switching bits S(1:m) for the change-over switches 53-(1:m) are generated by a 1-of-m decoder 55 which receives a delay control signal in the form of a multi-bit code in order to specify whether all m switching bits should have the logic value “0” or which ones of the switching bits should have the logic value “1” (the other switching bits then remain at “0”). Thus, either none of the changeover switches or one selected change-over switch 53-i is placed into its 1-state.
In operation, the delay elements 52-(1:m) are triggered by the rising edges of the frame clock signal CLY. If all change-over switches 53-(1:m) are in the O-state, the chain of delay elements 52-(1:m) operates as m-stage shift register so that the frame sequence DFE at the input end appears at the output of the last change-over switch 53-m with a delay of m frame clock periods. The output sequence DFY is thus delayed by m*TF+τM with respect to the input sequence DFE, where τM is the transit time for this change-over switch (multiplexer transfer time).
If only the first change-over switch 53-1 is in the I-state, the part-chain of the subsequent delay elements 52-(2:m) operates as (m−1)-stage shift register so that the delay is equal to (m−1)*TF+τM. If only the last change-over switch 53-m is in the 1-state, the delay is only equal to τM. Generally it holds true that when i is the ordinal number of the change-over switch located in the 1-state, that is to say only the switching bit Si has the logic value “1”, the delay is (m−i)*TF+τM.
In the embodiment shown in
If the data sinks 300-(1:p) are individual memory chips (e.g. DRAMs) of a storage module (e.g. of a DIMM), the arrangement according to
To increase the memory capacity, a number of similar memory modules can be provided which are connected in such a manner that each module can receive the data supplied by the data source (e.g. of a memory controller) 100 and accepts these data when it is individually addressed.
As shown, each transmission link 200-i shown in
The p transmission links of the “first” group G1 which has the shortest distance to the data source 100 receive at their inputs X the serial bit streams directly from the output lines 110-1:p of the data source 100. In the following groups G2, G3, . . . , each transmission link 200-i receives at its input X the associated serial bit stream, not directly from the associated data line 110-i but via a loop which runs through a part of the i-th transmission link 200-i of the respective preceding group. This loop regenerates the serial bit stream received at the input X and leads through the demultiplexer 20 and from there via a regenerating circuit 60 to a serial output Z of the relevant transmission link. The configuration and the operation of the regenerating loop will be described by means of
As shown, the switches 61-1:4, the read control circuit 63 and the flip flop 62 together form an n-to-I multiplexer. The read control circuit 63 is clocked by the active (e.g. rising) edges of a read clock signal, e.g. the system clock signal CLS which is also supplied to the clock input C of the flip flop 62. On average, this read clock signal has the same frequency fB as the input clock signal CLB of the demultiplexer 20 but its phase can differ from the phase of the clock signal CLB.
That active edge of the read clock signal CLS which appears at the demultiplexer output DQ1 during the validity of the first bit B1 of a frame (compare
As shown, the bit sequence appearing at output Q of the flip flop 62 is supplied to a data transmitter 66 which samples the individual bits with the clock signal and supplies them as “regenerated” serial bit stream to the output Y.
The demultiplexer 20 thus fulfils a dual function in this case. On the one hand, it provides for the serial/parallel conversion in the transmission link leading from input X to the parallel output Y. On the other hand, it simultaneously, together with the regenerating circuit 60, operates as FIFO circuit wherein the latch elements 22-1:4 of the demultiplexer 22 form an n-stage FIFO register, the write pointer of which is formed by the n output signals EN1:4 of the write control circuit 23 and the read pointer of which is formed by the n output signals of the read control circuit 63. By means of this FIFO circuit in each transmission link, the phase of the serial bit stream forwarded via the loop is in each case aligned with the phase of the clock signal CLS.
In the arrangement according to
The basic settings mentioned can be carried out during an initialization process before each activation (and, if desired, also in intervals between operating sections). In the text which follows, an example of a method for carrying out the settings is described.
Firstly, the data source 100 is caused to send the training pattern mentioned above. This pattern can consist, e.g. of n successive n-bit code words, wherein the second to nth code words are identical to one another but different from the first code word. For the exemplary case of n=12, the pattern can be arranged as follows:
wherein the sequence in time of the bits must be read from left to right. From the training pattern, the marking MRK which synchronizes the demultiplexer with the frame boundaries as has been described above in conjunction with
In a second step the uncertainty, moving within one frame period, of the initial state of the buffer circuit in each transmission link 200-i must be eliminated. For this purpose, measures are taken in order to be able to modify the phase of the common frame clock CLY of all data sinks. As shown in
After these initialization steps, two accurate information items are available: firstly an accurate information item about the relative phase angle between the common sink frame clock CLY and the frame clock CLF which determines the write clock of the buffer circuit 40 in the associated transmission link 200-i; secondly an accurate information item about the number of frame periods by which the serial/parallel-converted frames must be individually delayed in each transmission link so that the data arrive in clock synchronism at all sinks. It is thus also known which transmission link is the “latest one”, i.e. in which transmission link the shortest delay must be set.
Correspondingly, a third initialization step follows in which the phase of the common clock signal CLY is set in such a manner that the transit time or latency of the data via the buffer circuit 40 of the “latest” transmission link is minimized. This means that the distance between write pointer and read pointer in this buffer circuit has the just permissible minimum measure. Selection of the “latest” transmission link as reference for this setting ensures that any possible drift of the write clock signal CLF of the transmission link with respect to the common clock signal CLY can be compensated for. The other transmission links may be initialized by setting the delay device 50 in accordance with the previously measured phase differences.
The transit time or latency of the data from the source 100 to all data sinks is thus minimized to the transmit time of the data passing via the “latest” transmission link which, in turn, is minimized to the minimum permissible measure.
In principle, the transmission link necessarily contains a serial/parallel converter which converts the serial bit stream into the serial/parallel converted n-bit words. Each of these data words should reproduce a certain frame of the serial bit stream, i.e. a certain section, consisting of n successive bits, of the serial bit stream. In order to keep the latency of the entire transmission link low, the latency of the demultiplexer should also be as low as possible.
A serial/parallel converter may therefore contain the following: A 1-to-n demultiplexer which is constructed and controllable in such a manner that the successive data bits of the serial bit stream (SBS) appear in succession at intervals equal to a bit period TB of the serial bit stream cyclically at n data outputs and remain latched at the respective data output until a data bit appears again at the relevant data output. A relatching circuit with latching elements which receive the signals from the data outputs of the demultiplexer at which the first k data bits of each cycle appear and which are enabled in each case at a time which is between the beginning of the latching of the last data bit and the end of the latching of the first data bit of the relevant cycle in the demultiplexer, wherein 1≦k<n.
Such a serial/parallel converter has the advantage that its latency is extremely short. At the n parallel data outputs of the 1-to-n demultiplexer, the n data bits of each n-bit data word appear staggered in time at intervals of in each case one bit period TB and in each case for the duration of n bit periods. The first bit of each data word appears virtually immediately after its reception and the nth (that is to say last) bit appears already n−1 bit periods later. Due to the relatching circuit according to the invention, the time window within which all n bits can be sampled in parallel is noticeably enlarged.
Further a buffer circuit and an additional adjustable delay circuit for synchronizing the serial/parallel converted frames with the clock operation of the data sink may be provided. Moreover a number of transmission links for the synchronized transmission of a number of serial bit streams as sequences of serial/parallel converted frames to a number of data sinks operated in parallel, e.g. to the individual DRAM chips of storage modules may be combined. All these embodiments are characterized by the fact that their contribution to the latency of the data transmission is small.
The preceding description describes exemplary embodiments of the invention. The features disclosed therein and the claims and the drawings can, therefore, be useful for realizing the invention in its various embodiments, both individually and in any combination. While the foregoing is directed to embodiments of the invention, other and further embodiments of this invention may be devised without departing from the basic scope of the invention, the scope of the present invention being determined by the claims that follow.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102007035018.1-31 | Jul 2007 | DE | national |
