Patent Application
20160148842
The disclosed is directed to the sawing of low-k wafers so as to minimize side wall damage along active device edges. In particular, the disclosed is directed to the removal any metal residues in the saw lanes between active device edges so as to reduce the risk of side wall cracking.
As integrated circuit devices are tending toward demands for more performance in a smaller space, the search for materials has included the use of materials having a low dielectric constant (k<3.0). Use of materials with a k value lower than that of silicon dioxide (SiO2) has reduced the interconnect structure capacitance. Further, with the replacement of aluminum (Al) interconnects with those of copper (Cu), the structural resistance is reduced. This emerging technology is becoming increasingly relevant in the myriad of systems and products on the market and in development.
The challenge in using the emerging technology impacts the manufacturing processes, especially during the sawing and dicing of low-k wafer substrate containing the fabricated active devices. There is a need for a processing technique that addresses this challenge.
The disclosed embodiments have been found useful in addressing the incidence of sidewall cracking during the sawing and singulation of a low-k wafer substrate having active devices. In some wafer substrates, process control monitor (PCM) circuits are laid out in the saw lanes. These PCM circuits are used to keep track of critical parameters during selected steps in the fabrication of the active devices and are constructed in parallel with the active devices during the photolithography and etching processes. Continual monitoring of the PCM values throughout the process may serve as an indicator of the production line stability and provide data for statistical process control (SPC). Further, if on a particular wafer, PCM values go out of acceptable ranges during a process step, the operator may choose to scrap the wafer rather than processing it further and incurring additional costs that are unnecessary. Like the active devices on the wafer substrate, there is metallization present on the PCM circuits. The sawing and singulation process may be adversely affected by the PCM metallization and contribute to the sidewall cracking.
In an example current process, a wafer's front-side surface has active devices, and PCM circuits in the saw lanes. Through a broad laser grooving, the PCM die are removed, the width of the laser grooving beam (WLG) is close to that of the saw lane. A first blade of a first kerf width (WZ1) which is less than the laser grooving width makes a cut to a depth greater than the depth of the active devices; the first blade is aligned to the center of the laser grooved saw lane. A second blade of a second kerf width (WZ2) which is less than that of the first blade is aligned to the center of the first blade cut and makes a cut to a depth of the wafer substrate thickness; the wafer is singulated into individual devices. The widths of the cutting process follow the relationship of: WLG>WZ1>WZ2.
Through a review of the current process, it is has been determined that the broad laser grooving kerf creates a large heat affected zone (HAZ). Shifts in the alignment of the first and second saw blades, resulting in a cut too close to the laser grooved edge induces sidewall cracking owing to the blades slicing through any remaining PCM metallization (not removed by laser grooving). A saw lane width currently in use is bout 80 μm. The trend is toward narrower saw lanes of about 60 μm or less. Thus, the current process is no longer suitable owing to the tighter alignment tolerances. With smaller saw lanes, the laser grooving width (WLG) is reduced along with the kerf of the saws.
In an example embodiment according to the present disclosure, there is a method for sawing a wafer substrate, the wafer substrate having a front-side surface containing active devices separated by saw lanes and a back-side surface having undergone back grinding, the saw lanes having process control monitor (PCM) devices present therein. The method comprises mounting the wafer substrate onto a carrier tape on the front-side surface. With a blade of a first kerf, the back-side surface is sawed in tracks corresponding to the saw lanes, to a first depth. A carrier tape is applied to the back-side surface of the wafer substrate and the carrier tape is removed from the front-side surface. With the LG laser having a preset beam diameter, the saw lanes are laser grooved (LG), to an LG depth, on the front-side surface of the wafer substrate until PCM devices are substantially removed. With a blade of a second kerf, the second kerf less than the first kerf, the front-side surface of the wafer substrate is sawed about the center of the saw lanes until the active devices are separated from one another.
In another example embodiment, there is a method for sawing a wafer substrate, the wafer substrate having a front-side surface containing active devices separated by saw lanes and a back-side surface having undergone back-grinding, so that the wafer substrate has a back-grind thickness. The method comprises mounting the wafer substrate onto a first flexible foil carrier (FFC) on the front-side surface. With a blade of a first kerf, the back-side surface is sawed in tracks corresponding to the saw lanes, to a first depth, the first depth to at least one third of the back-grind thickness. A second FFC is applied to the back-side surface of the wafer substrate and the first FFC is removed from the front-side surface. Laser grooving (LG) the saw lanes on the front-side surface of the wafer substrate is performed to a depth of the remaining silicon left by first kerf blade; the LG has a second preset beam diameter. The wafer substrate is then separated into individual active device die.
In an example embodiment, there is semiconductor device die prepared by sawing and laser grooving. The semiconductor device die comprises a topside surface and an opposite underside surface. There are four vertical side faces; the four vertical side faces are perpendicular to the topside surface and opposite underside surface. Each of the four vertical side faces includes, a first tooling mark from a first kerf saw blade, a second tooling mark from a second kerf saw blade, and a heat affected zone (HAZ).
The above summaries of the present disclosure are not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follow.
The invention may be more completely understood in consideration of the following detailed description of various embodiments disclosed in connection with the accompanying drawings, in which:
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
The disclosed embodiments have been found useful in reducing the incidence of sidewall cracking and backside chipping active devices on low-k wafer substrates as they are sliced into individual product die. The sidewall cracking may be induced by the heat affected zone (HAZ) from laser grooving prior to sawing with blades, particularly in narrow saw lanes of 80 μm or less and on those wafers whose saw lanes are occupied by process control monitor (PCM) structures whose metallization is not completely removed by the laser grooving.
In an example embodiment according to the disclosure, a wafer substrate is sawed on the backside at predetermined locations in the saw lanes. The saw lanes may be ascertained through infra-red imaging from the back-side surface to the front-side surface of the wafer. In the example embodiment, the saw lane width is about 80 μm; in another example embodiment, the lane may be less; in others, more. During a first cut, with a saw blade of a first kerf (e.g., a “thick blade”), the wafer is sawed through the back side to a depth of about 75% of the post-grind thickness of the wafer. The width of the first kerf blade may be about 40 μm.
Wafer thickness, after back-side grinding, in an example process may be in the range of about 150 μm to about 250 μm. For example, a pre-grinding thickness, of an “eight-inch” wafer (200 mm) is about 725 μm; the pre-grinding thickness for a “six-inch” wafer (150 mm) is about 675 μm.
After the first cut, on the front-side surface of the wafer, about the center of the saw lanes, a laser grooving (L/G) process cuts through the top surface of the saw lanes. If any remaining metal from PCM circuits is present, the laser removes it. For an 80 μm saw lane width, the L/G process defines an opening of about 60 μm as it cuts through the metal and partially through the underlying silicon material.
More details of use of a laser in the dicing process may be found in U.S. patent application Ser. No. 13/687,110 of Sascha Moeller and Martin Lapke titled “Wafer Separation” filed on Nov. 28, 2012, published on May 29, 2014 as US 2014/0145294 A1, and is incorporated by reference in its entirety.
Further information on “low-k grooving” may be found in the product brochure titled, “Laser Application” of DISCO Corporation, Tokyo, Japan.
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In another example embodiment, a second cut Z2 with a blade of narrower kerf than that of the Z1 blade may be used in lieu of laser grooving.
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The present disclosure, in having a larger process window to accommodate the Z2 shift, reduces the likelihood of backside chipping. The second blade lifetime is extended because of the shallower depth required to saw and separate the device die. Further, in that the blade is cutting at a shallower depth, there is less vibration from blade imperfections; the cut is more accurate with less variation. The heat affected zone (HAZ) of the laser grooving can be reduced because the smaller kerf (Z2) of the second blade does not require as large a diameter laser beam to remove undesired material in the saw lanes.
In developing the disclosed technique, the performance of the first and second saw blades and the laser grooving was reviewed and analyzed. Refer to
During the sawing, the first blade (Z1) had exhibited shift as each sample cut was made. There was a maximum shift of about 2.9 μm and a minimum shift of about −1.9 μm about a “zero line” center (i.e., 0 μm of shift). The CPK is about 1.103. Curve 415 is expressed in
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During the laser grooving, the maximum shift was about 2.2 μm and the minimum shift was about −2.2 μm with an average of about −0.236 μm a “zero line” center (i.e., 0 μm of shift). The laser grooving shift is plotted as curve 515 in
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During the sawing, the second blade (Z2) had exhibited shift as each sample cut was made. There was a maximum shift of about 1.9 μm and a minimum shift of about −1.9 μm about a “zero line” center (i.e., 0 μm of shift). The CPK is about 1.232. Curve 615 is plotted in
By performing the sawing with the first cut of Z1 on the back-side surface of the wafer substrate, the maximum shift to which the active devices would be exposed, has been reduced from 2.9 μm to about 1.9 μm. Thus, the smaller kerf of the second cut of Z2, after the laser grooving, with its reduced shift, lessens the probability of the sawing/singulation process damaging active areas of the integrated circuit device die.
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The disclosed embodiments may be useful in devices whose saw lanes are less than 80 μm. For example, the WidthZ1>WidthLG>WidthZ2=60 μm>40 μm>25 μm. However, per the disclosure, the WidthZ1 is no longer constrained. With a narrower saw lane, the Z2 blade with a narrower kerf is more accurate. The depth at which the blade performs its cutting is less than current methods; the lower depth improves cutting accuracy. For example, for a WidthZ2=25 μm, the accuracy of the blade is ±3 μm; owing to blade vibration, the acceptable kerf is about 1.1× blade width. Thus, a 25 μm would have an acceptable kerf of about 27.5 μm.
As discussed in reference to
More detailed information on saw marks in silicon wafers may be found in a paper titled, “Quantitative Classification of Saw Marks of Silicon Wafers,” of A. Lawerenz, S. Dauwe, and F.-W. Schulze. (Pre-Print for the 21st European Photovoltaic Solar Energy Conference and Exhibition, Dresden, Germany, September 2006).
Various exemplary embodiments are described in reference to specific illustrative examples. The illustrative examples are selected to assist a person of ordinary skill in the art to form a clear understanding of, and to practice the various embodiments. However, the scope of systems, structures and devices that may be constructed to have one or more of the embodiments, and the scope of methods that may be implemented according to one or more of the embodiments, are in no way confined to the specific illustrative examples that have been presented. On the contrary, as will be readily recognized by persons of ordinary skill in the relevant arts based on this description, many other configurations, arrangements, and methods according to the various embodiments may be implemented.
To the extent positional designations such as top, bottom, upper, lower have been used in describing this disclosure, it will be appreciated that those designations are given with reference to the corresponding drawings, and that if the orientation of the device changes during manufacturing or operation, other positional relationships may apply instead. As described above, those positional relationships are described for clarity, not limitation.
The present disclosure has been described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto, but rather, is set forth only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, for illustrative purposes, the size of various elements may be exaggerated and not drawn to a particular scale. It is intended that this disclosure encompasses inconsequential variations in the relevant tolerances and properties of components and modes of operation thereof. Imperfect practice of the invention is intended to be covered.
Where the term “comprising” is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun, e.g. “a” “an” or “the”, this includes a plural of that noun unless something otherwise is specifically stated. Hence, the term “comprising” should not be interpreted as being restricted to the items listed thereafter; it does not exclude other elements or steps, and so the scope of the expression “a device comprising items A and B” should not be limited to devices consisting only of components A and B. This expression signifies that, with respect to the present disclosure, the only relevant components of the device are A and B.
Numerous other embodiments of the invention will be apparent to persons skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
