Claims
- 1. An assembly of semiconductor dice comprising:
a first semiconductor die including a plurality of bond pads arranged in an array over an active surface thereof and at least one alignment element associated with said active surface for aligning at least one second semiconductor die relative to said active surface; and said at least one second semiconductor die, including a plurality of bond pads on an active surface thereof, each of said plurality of bond pads of said second semiconductor die alignable with corresponding bond pads of said first semiconductor die in an assembled relationship of said first and second semiconductor dice, said second semiconductor die having a smaller surface area than said first semiconductor die, said active surfaces of said first and second semiconductor dice in said assembled relationship facing one another.
- 2. The assembly of claim 1, wherein said first semiconductor die comprises a microprocessor.
- 3. The assembly of claim 1, wherein said second semiconductor die comprises a memory device.
- 4. The assembly of claim 1, wherein said plurality of bond pads of said second semiconductor die are arranged in an array on said active surface.
- 5. The assembly of claim 1, wherein said first semiconductor die includes outer bond pads that are exposed laterally beyond an outer periphery of said second semiconductor die.
- 6. The assembly of claim 5, wherein said outer bond pads are configured to electrically connect at least one of said first and second semiconductor dice to another semiconductor device component.
- 7. The assembly of claim 1, further comprising conductive structures disposable between corresponding bond pads of said first and second semiconductor dice in said assembled relationship thereof.
- 8. The assembly of claim 7, wherein said conductive structures comprise balls, bumps, pillars, or columns.
- 9. The assembly of claim 7, wherein said conductive structures are formed of a material comprising a metal, an alloy, a conductive epoxy, a conductor-filled epoxy, or a z-axis conductive elastomer.
- 10. The assembly of claim 1, wherein said at least one alignment is configured to guide at least two adjoined edges of said second semiconductor die.
- 11. The assembly of claim 1, wherein said at least one alignment element comprises at least one recess in which at least one bond pad of said plurality of bond pads of said first semiconductor die is located and recessed relative to an unrecessed portion of said active surface of said first semiconductor die.
- 12. The assembly of claim 13, wherein said second semiconductor die comprises conductive structures protruding from each of said plurality of bond pads thereof.
- 13. The assembly of claim 1, wherein at least some of said plurality of bond pads of said second semiconductor die are recessed relative to said active surface thereof.
- 14. The assembly of claim 1, comprising a plurality of second semiconductor dice.
- 15. The assembly of claim 1, wherein said at least one alignment element protrudes from said active surface.
- 16. The assembly of claim 15, wherein said at least one alignment element comprises a plurality of superimposed, contiguous, mutually adhered layers.
- 17. The assembly of claim 16, wherein each of said plurality of superimposed, contiguous, mutually adhered layers comprises photopolymer.
- 18. The assembly of claim 1, wherein at least one bond pad of said plurality of bond pads of said first semiconductor die is exposed laterally beyond said at least one second semiconductor die.
- 19. The assembly of claim 18, further comprising:
a carrier including at least one contact pad that is electrically connected to said at least one bond pad.
- 20. A semiconductor device package, comprising:
a first semiconductor die including a plurality of bond pads arranged in an array on an active surface thereof; at least one second semiconductor die, comprising a plurality of bond pads on an active surface thereof, each of said plurality of bond pads of said second semiconductor die alignable with corresponding bond pads of said first semiconductor die, said active surfaces of said first and second semiconductor dice facing one another, and said bond pads of said second semiconductor die electrically connected to said corresponding bond pads of said first semiconductor die, other bond pads of said first semiconductor die being exposed laterally beyond an outer periphery of said second semiconductor die; and an encapsulant substantially covering peripheral edges and a back side of said first semiconductor die.
- 21. The semiconductor device package of claim 20, further comprising:
a carrier including contacts electrically connected to said other bond pads.
- 22. The semiconductor device package of claim 21, wherein said carrier comprises a carrier substrate with said contacts comprising contact pads formed on a surface of said carrier substrate.
- 23. The semiconductor device package of claim 21, wherein said carrier includes a recess formed in said surface and configured to receive said second semiconductor die.
- 24. The semiconductor device package of claim 21, further comprising:
a thermally conductive material disposed between a backside of said second semiconductor die and said carrier.
- 25. The semiconductor device package of claim 21, wherein said carrier comprises leads.
- 26. The semiconductor device package of claim 20, wherein said first semiconductor die comprises a microprocessor.
- 27. The semiconductor device package of claim 26, wherein said second semiconductor die comprises a memory device.
- 28. The semiconductor device package of claim 20, wherein said second semiconductor die comprises a memory device.
- 29. The semiconductor device package of claim 28, wherein said first semiconductor die comprises a microprocessor.
- 30. The semiconductor device package of claim 20, wherein said plurality of bond pads of said second semiconductor die are arranged in an array on said active surface.
- 31. The semiconductor device package of claim 20, wherein said plurality of bond pads of said second semiconductor die and said corresponding bond pads of said first semiconductor die are electrically connected to one another by way of conductive structures disposed therebetween.
- 32. The semiconductor device package of claim 31, wherein said conductive structures comprise balls, bumps, pillars, or columns.
- 33. The semiconductor device package of claim 31, wherein said conductive structures are formed of a material comprising a metal, an alloy, a conductive epoxy, a conductor-filled epoxy, or a z-axis conductive elastomer.
- 34. The semiconductor device package of claim 21, wherein said contacts of said carrier and said other bond pads of said first semiconductor die are electrically connected by conductive structures.
- 35. The semiconductor device package of claim 34, wherein said conductive structures comprise balls, bumps, pillars, or columns.
- 36. The semiconductor device package of claim 34, wherein said conductive structures are formed from a material comprising a metal, an alloy, a conductive epoxy, a conductor-filled epoxy, or a z-axis conductive elastomer.
- 37. The semiconductor device package of claim 34, wherein each of said conductive structures comprises a plurality of members.
- 38. The semiconductor device package of claim 20, further comprising an encapsulant material at least laterally sealing at least said active surfaces of said first and second semiconductor dice.
- 39. The semiconductor device package of claim 38, wherein said encapsulant material comprises an underfill material.
- 40. The semiconductor device package of claim 20, wherein said encapsulant comprises a glob-top encapsulant.
- 41. The semiconductor device package of claim 20, further comprising:
a molded package encapsulating said first and second semiconductor dice.
- 42. The semiconductor device package of claim 20, further comprising at least one alignment element associated with said active surface of said first semiconductor die.
- 43. The semiconductor device package of claim 42, wherein said at least one alignment element is configured to align said at least one second semiconductor die relative to said active surface of said first semiconductor die.
- 44. The semiconductor device package of claim 42, wherein said at least one alignment element comprises at least one recess in said active surface of said first semiconductor die within which at least one of said plurality of bond pads of said first semiconductor die is located and recessed relative to an unrecessed portion of said active surface of said first semiconductor die.
- 45. The semiconductor device package of claim 42, wherein said at least one alignment element protrudes from said active surface of said first semiconductor die.
- 46. The semiconductor device package of claim 20, comprising a plurality of second semiconductor dice.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of application Ser. No. 09/944,487, filed Aug. 30, 2001, pending, which is a divisional of application Ser. No. 09/615,009, filed Jul. 12, 2000, now U.S. Pat. No. 6,525,413 B1, issued Feb. 25, 2003.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09615009 |
Jul 2000 |
US |
Child |
09944487 |
Aug 2001 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09944487 |
Aug 2001 |
US |
Child |
10382025 |
Mar 2003 |
US |