Claims
- 1. A method for forming a conductive element of an integrated circuit, comprising:providing a substrate having a trench formed therein; forming a conductive diffusion barrier over the substrate to line the trench; implanting a diffusion barrier enhancing material into the substrate at an angle with respect to a broad surface of the substrate such that a bottom portion of the diffusion barrier is protected from the implantation; and forming an inlaid conductive element in the trench.
- 2. The method claimed in claim 1, wherein the diffusion barrier is titanium nitride (TiN) and the diffusion barrier enhancing material is silicon (Si).
- 3. The method claimed in claim 1, wherein the conductive element is copper (Cu).
- 4. The method claimed in claim 1, wherein said implanting comprises rotating the substrate continuously for a period during said implanting.
- 5. The method claimed in claim 1, wherein said implanting comprises rotating the substrate among a plurality of stationary positions during said implanting.
- 6. The method claimed in claim 1, wherein the conductive element is a via.
- 7. The method claimed in claim 1, wherein the conductive element is an interconnect.
- 8. The method claimed in claim 1, wherein the conductive element is a dual damascene structure.
RELATED APPLICATIONS
This application claims priority under 35 U.S.C. § 119(e) from U.S. Provisional Patent Application Serial No. 60/400,283, filed Jul. 31, 2002.
US Referenced Citations (4)
Number |
Name |
Date |
Kind |
5118636 |
Hosaka |
Jun 1992 |
A |
5278438 |
Kim et al. |
Jan 1994 |
A |
5498564 |
Geissler et al. |
Mar 1996 |
A |
6107153 |
Huang et al. |
Aug 2000 |
A |
Foreign Referenced Citations (1)
Number |
Date |
Country |
03087023 |
Apr 1991 |
JP |
Provisional Applications (1)
|
Number |
Date |
Country |
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60/400283 |
Jul 2002 |
US |