Patent Grant
9853118
This patent application relates to semiconductor diodes made from compound semiconductors or other lattice mismatched semiconductors on silicon wafers, as well as methods of fabricating such semiconductor diodes, and more particularly, for photonic applications such as light emitting diodes (LEDs), lasers, photovoltaics, and other optoelectronic uses.
This section provides background information and introduces information related to various aspects of the disclosures that are described and/or claimed below. These background statements are not admissions of prior art.
The majority of chip manufacturing takes advantage of silicon processing on high-quality, large-area, low-cost silicon wafers. Commercial manufacturers of devices made from compound semiconductors such as gallium arsenide and indium phosphide generally have been unable to take advantage of silicon wafers. They typically build light emitting diodes (LEDs), multi junction solar cells, and other compound semiconductor devices on small, expensive wafers made of materials such as sapphire, germanium, gallium arsenide, or silicon carbide.
The challenge of making compound semiconductor devices on inexpensive substrates has widespread economic implications. Compound semiconductors are an important component of our communications infrastructure because they can emit and detect light. They are the materials in the lasers that transmit signals through optical fibers, the sensors that receive those signals, the amplifiers in cellular telephones, the amplifiers in cell phone base stations, and the circuits that transmit and receive microwave signals.
Light emitting diodes typically consist of gallium nitride films deposited onto sapphire or silicon carbide wafers. These exotic substrates contribute to the high cost of LEDs. A sapphire wafer 4 inches in diameter typically costs around $130, and a 2-inch silicon carbide wafer can cost about $2000. By contrast, an 8-inch silicon wafer, which provides four times as much surface area as a 4-inch wafer and 16 times as much surface area as a 2-inch wafer, typically costs less than $100.
High-efficiency multi junction solar cells typically contain layers of germanium, gallium arsenide, and indium gallium phosphide deposited onto germanium wafers. As is the case with wafers for LEDs, germanium wafers similarly are smaller and significantly more expensive than silicon wafers.
The ability to create compound semiconductor devices on silicon wafers facilitates market growth in several key industries.
Two key technical barriers have prevented the fabrication of compound semiconductor devices on silicon wafers: the mismatch of lattice constants and the mismatch of thermal expansion coefficients.
Lattice Mismatch: In a crystal, the atoms sit in a regular periodic array known as a lattice. The distance between the atoms, known as the “lattice constant,” is typically a few ångstroms (1 ångstrom=10−10 meter). Silicon has a smaller lattice constant than many compound semiconductors. When compound semiconductors grow on silicon, crystalline imperfections known as misfit dislocations appear at the interface. The misfit dislocations create other crystalline defects known as threading dislocations, which propagate upward from the interface. Threading dislocations diminish the performance and the reliability of compound semiconductor devices such as lasers, solar cells, light-emitting diodes, etc.
Thermal Contraction Mismatch: Compound semiconductors typically grow at high temperatures, which can exceed 1000° C. When the wafer cools, the compound semiconductor film may contract more than the silicon wafer. As a result, the wafer may bow in a concave manner, stressing and ultimately cracking the film.
Until recently, the most promising previous efforts to grow high-quality compound semiconductors onto silicon substrates have relied on three approaches: graded buffer layers, wafer bonding, or selective growth on mesas. None of these approaches has achieved commercial success.
In graded buffer layers, the composition of the material changes gradually from substantially pure silicon to a pure compound semiconductor. Since the lattice constant also changes gradually, crystalline defects are less likely to form at the interface. Unfortunately, the graded buffer layers have to be relatively thick (about ten microns for a 4% lattice mismatch). The thick buffer layer increases both the costs and the likelihood of cracking.
Wafer bonding involves growing devices on expensive substrates, then lifting off the devices and bonding them to a silicon wafer. This approach rules out modem silicon processing as a route to cost reduction. Furthermore, bonding typically requires temperatures above 300° C. When the materials cool, the compound semiconductors may crack because they contract more than the silicon wafer.
Selective growth on a mesa exploits the mobility of some dislocations. The strategy is to deposit compound semiconductors in small regions (10 to 100 microns in length), thereby providing a short path where mobile dislocations can glide to the edge of the region and remove themselves from the device. However, structures created by this technique typically have a high density of threading dislocations (more than 100 million per square centimeter). This technique cannot remove immobile dislocations, which predominate when the lattice mismatch exceeds 2%.
Aspect Ratio Trapping (J. S. Park et al., APL 90, 052113 (2007), hereby incorporated by reference in its entirety) is a recently developed technology that makes it possible to deposit high quality compound semiconductors, germanium or other lattice mismatched materials on silicon wafers.
A trench is etched in the dielectric material, and then deposit a non-lattice-matched semiconductor 30 such as germanium or a compound semiconductor in the trench. The threading dislocations 40, shown as dotted lines, propagate upward, typically at approximately a 45 degree angle from the interface, then intersect the sidewalls of the trench, where they terminate. Threading dislocations 40 cannot propagate down the length of the trench because crystal facets guide them to the sidewalls. Reference is made to the region in the trench where the sidewalls trap threading dislocations as the “trapping region” 50. The upper region of the non-lattice-matched semiconductor 30, above the trapping region 50, is a relatively defect-free region 60.
ART addresses the issue of cracking caused from mismatch of thermal expansion coefficients for these reasons: (1) the stresses are small because the epitaxial layers are thin; (2) the material can elastically accommodate the stresses arising from thermal expansion mismatch because dimensions of the ART openings are small; and (3) the SiO2 pedestals, which are more compliant than the semiconductor materials, may deform to accommodate the stress.
For a more complete understanding of embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The exemplary diode structures are generally discussed in the context of a single diode, although semiconductor engineers and others skilled in the art will understand that most applications require multiple diodes, typically integrated on a single chip.
In general, semiconductor diodes disclosed in this document have the generic structure illustrated in
The bottom diode region 102 and the top diode region 104 have opposite doping types. For example, if the bottom diode region 102 is predominantly n-type doped (with an electron donor such phosphorous, arsenic, or antimony), then the top diode region 104 will be predominantly p-type doped (with an electron acceptor such as boron or aluminum), and vice versa. Heavy doping in both the bottom diode region 102 and the top diode region 104 provides a low-resistance pathway for current to enter and leave the device. Typical doping levels of the top and bottom regions would be in the range of 1017-1020 cm−3. Typical doping level of the active region would be below 1017 cm−3. Note that the use of “top” and “bottom” for designating regions is a matter of convenience and in some frames of reference a top region can be located above a bottom region. For example, consider a diode formed above a substrate with its top region formed above its bottom region. If the diode is flip-chip bonded to a handle wafer and then the substrate is removed, the frame of reference for viewing the diode typically is flipped. In this case the top region will be viewed as being below the bottom region.
The substrate 101 is typically a silicon wafer, although in different embodiments a variety of other substrates including sapphire and silicon carbide are suitable. At least some portion of the substrate 101 will have the same predominant doping type (either n or p) as the bottom diode region 102. As a result, it will be possible to make good electrical contact between the bottom diode region 102 and the substrate 101.
The detailed structure of the active diode region 103 may depend upon numerous factors, including the intended application. In one form, the active diode region 103 is formed by the junction of the top diode region 104 and the bottom diode region 104. In this case, it can be desirable to vary the doping of the top and bottom regions near the junction. In an LED, the active diode region 103 may contain many layers that include both doped layers and thin undoped quantum wells where electrons and holes can recombine and generate photons. In another example of a solar cell, the active diode region 103 may consist of a single layer of moderately n-doped or moderately p-doped semiconductor material to absorb incident photons and generate an electron-hole pair.
The materials used to form the diode regions are well known to those of skill in the art. Typical examples of useful semiconductor materials are: Group IV materials, such as Si, C, or Ge, or alloys of these such as SiC or SiGe; Group II-VI compounds (including binary, ternary, and quaternary forms), e.g., compounds formed from Group II materials such as Zn, Mg, Be or Cd and Group VI materials such as Te, Se or S, such as ZnSe, ZnSTe, or ZnMgSTe; and Group III-V compounds (including binary, ternary, and quaternary forms), e.g., compounds formed from Group III materials such as In, Al, or Ga and group V materials such as As, P, Sb or N, such as InP, GaAs, GaN, InAlAs, AlGaN, InAlGaAs, etc. Examples of III-N compounds include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), and their ternary and quaternary compounds. Thus, the semiconductor material may include at least one of a group IV element or compound, a III-V or III-N compound, or a II-VI compound. Those of skill in the art understand how to select and process these materials based desired properties such as bandgaps, lattice constants, doping levels, etc.
To prepare the diode of
A trench or trenches 165 are patterned with substantially vertical sidewalls in the layer of dielectric material 160, thereby exposing a portion of the surface of the silicon substrate 155, as shown in
In some cases, it may be advantageous to clean the surface of the silicon substrate 155 at the bottom of the trenches 165 by standard techniques to prepare for epitaxial growth of the bottom diode region. See, e.g., (Park et al., APL 90, 052113 [2007]).
Another step is to grow the bottom diode region 170, thereby creating the structure shown in
It is possible to dope the bottom diode region 170 in situ during epitaxial growth or to dope it ex situ by ion implantation. (As a general matter, it is generally preferable to dope the bottom diode regions, active diode regions, and top diode regions mentioned in this disclosure, and it is possible to dope them either in situ during epitaxial growth or ex situ by ion implantation.)
In
The lower region of the fin, which is surrounded by the vertical sidewalls of the dielectric material 160, may be called the “trapping region” 175 because it traps dislocations including the threading dislocations 180. Threading dislocations originate at the interface between the fin-shaped bottom diode region 170 and the substrate 155, and they propagate upward at angles of approximately 45 degrees.
In this embodiment and other embodiments, it is preferred that the active diode region 185 and the top diode region 190 have approximately the same lattice constants as the bottom diode region, although the lattice constants do not have to be approximately the same. As a result of having approximately the same lattice constants, few if any defects will form at the interfaces between the diode regions.
As is further shown in
In
When engineering a solar cell from the architecture shown in
One feature of the architecture shown in
The additional semiconductor material in the common top diode region 195 of
The structures shown in both
Further, structures shown in both
The following are examples of process parameters to form the bottom, active, and top diode regions according to embodiments in this disclosure. First, a substrate and a patterned dielectric layer as known in the art are provided. Process parameters for bottom, active, and top diode regions, of a GaAs and AlGaAs-based LED, according to the first embodiment are as follows.
In this example, the bottom diode region can be a pillar or fin (central pillar or fin) of GaAs having height dimensions greater than width or radial dimensions (e.g., 1 micron in height and 100 nm in width). Growth conditions (e.g., CVD) include i) pressure: 0.1 atm ii) precursors: TMG (Trimethylgallium) and 20% AsH3 (Arsine), diluted in H2, iii) temperature: 750 C and iv) dopant: n-type. To make the bottom diode region N-type, one dopant is silicon. To highly enhance vertical growth, the partial pressure of AsH3 may be relatively low for this step, compared to what would normally be used for GaAs growth as understood by those well versed in the art. For example, the partial pressure of AsH3 could be 5-10× lower than normal. Because this is a reactor-dependent value, no absolute value is given here.
Further in this example, the active diode region can include a plurality of layers being a first confinement layer, a quantum well layer and a second confinement layer at the bottom diode layer.
Growth conditions for an AlGaAs layer for carrier confinement (e.g., 15 nm thick) include i) pressure: 0.1 atm, ii) precursors: TMG, TMA (Trimethylaluminium), and 20% arsine, diluted in H2, iii) temperature: 850 C and iv) dopant: N-type dopant is silicon.
Growth conditions for a GaAs quantum well layer for emission (e.g., 10 nm thick) include i) pressure: 0.1 aim, ii) precursors: TMG and 20% arsine, diluted in H2, iii) temperature: 720 C and iv) dopant: no doping.
Growth conditions for an AlGaAs layer for carrier confinement (e.g., 15 nm thick) include i) pressure: 0.1 atm, ii) precursors: TMG, TMA (Trimethylaluminium), and 20% arsine, diluted in H2, iii) temperature: 850 C and iv) dopant: P-type dopant with zinc.
Continuing in this example, the top diode region is at or on the active diode layer (e.g., 0.5 micron thick). Growth conditions for a layer of GaAs include i) pressure: 0.1 atm, ii) precursors: TMG and 20% arsine, diluted in H2, iii) temperature: 720 C and iv) dopant: P-type dopant is zinc.
The embodiment shown in
In another embodiment shown in
In a further alternative embodiment, a method takes into consideration the fact that the technique for growing free-standing vertical structures as described by Noborisaka and his colleagues may not work under all conditions. For example, it will not generally be possible to grow free-standing vertical structures if the silicon substrate has a (100) crystal surface.
This method begins with an appropriately doped silicon substrate 155, as shown in
A second dielectric layer 215 is grown on top of the first dielectric layer 210. In some embodiments, the preferred material for this second dielectric layer is silicon dioxide (SiO2).
Trenches 220 are patterned with substantially vertical sidewalls through both dielectric layers 210 and 215, exposing a portion of the surface of the silicon substrate 155. An optional step is to clean the surface of the silicon substrate 155 at the bottom of the trenches 220, such as by the cleaning method described above.
The bottom diode region 170 is grown by filling the trenches with a semiconductor material, as shown in
The second dielectric layer 215 is removed with a process such as a wet etch with hydrofluoric acid and water. This process will selectively remove the second (SiO2) dielectric layer 215 without attacking either the first (SiNx) dielectric layer 210 or any of the semiconductor materials that may comprise the bottom diode region 225. The resultant structure appears in
This method continues as described above and illustrated in
A hole 250 is patterned with substantially vertical sidewalls in the dielectric material 160 by standard photolithographic or etch techniques. To enable the hole 250 to trap substantially all threading dislocations, the ratio of the depth of the hole 250 to the diameter of the hole 250 is preferably equal to or greater than 1. The hole exposes the surface of the silicon substrate 155.
Growth conditions (such as the pressure and the composition of the precursor gases and the temperature of the substrate) are selected that favor growth perpendicular to the plane of the silicon substrate 155 and suppress growth parallel to the plane of the silicon substrate 155, as described in the Noborisaka paper cited above. An appropriately doped semiconductor material is grown that fills the holes and forms free-standing columns above the holes to create the bottom diode region 260, as shown in
Again, because there is a lattice mismatch between silicon the semiconductor diode material, misfit dislocations may occur at the interface between the bottom diode region 260 and the silicon substrate 155. Threading dislocations may propagate upward from the interface and intersect the curved sidewalls of hole in the dielectric layer 160 and terminate. The trapping region in which the threading dislocations originate and terminate may remain substantially within the hole 250 in the dielectric layer and therefore may not be visible in
(For the special case in which the bottom diode region 260 is a column with very small diameter, well below 100 manometers, the semiconductor material in the bottom diode region 260 can undergo complete elastic relaxation without the formation of any lattice mismatch defects. In this case, there may be no threading dislocations for the sidewalls of the dielectric layer to trap, and the diode may not contain a “trapping region.”)
The growth conditions are adjusted so that the material or materials for the active diode region 265 will grow at approximately equal rates on the top and on the sides of the bottom diode region 260. Semiconductor material is conformally grown on the top and the sides of the bottom diode region 260 to create the active diode region 265 shown in
Semiconductor material is conformally grown on the top and sides of the active diode region 265 to create the top diode region 270, as shown in
The top electrical contact 280 is grown on the exposed surface of the top diode region 275, and the bottom electrical contact 285 is grown below the silicon substrate 155, as shown in
The diode shown in
The following methods are two exemplary methods of fabricating the embodiment shown in
Another method does not depend on the ability to grow a free-standing bottom diode region in the shape of a column. It begins with an appropriately doped silicon substrate 155, as shown in
A second dielectric layer 215 is grown on top of the first dielectric layer 210. In some embodiments, the preferred material for this second dielectric layer 215 is silicon dioxide SiO2.
A hole 300 is patterned with substantially vertical sidewalls through both dielectric layers 210 and 215, exposing the surface of the silicon substrate 155. It is possible to pattern the hole 300 by various techniques such as standard photolithography or reactive ion etch processes.
The thickness of the first dielectric layer 210 may be greater than or equal to than the diameter of the hole 300. Under these conditions, the curved sidewalls of the first dielectric layer 210 may trap substantially all of the threading dislocations.
The surface of the silicon substrate 155 at the bottom of the hole 300 may be cleaned by the cleaning method referred to earlier.
The bottom diode region 260 is grown by filling the hole 300 with a semiconductor material, as shown in
Misfit dislocations may form at the interface between the silicon substrate 155 and the bottom diode region 260. Threading dislocations may propagate upward and intersect the sidewalls of the first dielectric layer 210, and may terminate within trapping regions, which reside at the bottom of the filled holes 300 and therefore are not visible in
The remaining portions of the second dielectric layer 215 (e.g., the SiO2 layer) are removed by means of a wet etch with hydrofluoric acid and water. This process may selectively remove the second (e.g., SiO2) dielectric layer 215 without attacking either the first (e.g., SiNx) dielectric layer 210 or any of the semiconductor materials that may comprise the bottom diode region 260.
The resultant structure appears in
Some semiconductor materials demonstrate unique behavior when deposited into the round holes 250 and subsequently grow free-standing bottom diode regions 260. Specifically, the free-standing columns can grow out of the round holes to form hexagonal columns; e.g., the columns (element 260 in
The hexagonal columns may be advantageously used to increase the packing density of the semiconductor diodes by configuring them in a hexagonal array rather than a square array.
The diode structure shown in
The deposition conditions are adjusted in the reactor to favor vertical growth and to suppress horizontal growth, as described above. The bottom diode region 365 is grown in the shape of a free-standing fin, as shown in
The deposition conditions are adjusted in the reactor so that vertical growth and horizontal growth occur at approximately the same rates. A semiconductor material is conformally grown around the top and sides of the bottom diode region 365 to create the active diode region 380, as shown in
Since the dielectric layer is so thin, the aspect ratio of the trenches (the ratio of height to width) 355 is less than 1. As a result, the sidewalls of the dielectric layer 350 may not be able to trap substantially all of the threading dislocations 375. The threading dislocations 375 may continue to propagate into the active diode region 380. Note that electron-hole pairs can recombine when they contact the threading dislocations 375 and reduce the efficiency of the solar cell. However, the structure mitigates this effect because the photons will pass through what a primary light absorption region 390, which resides in the upper portion of the diode, before they can reach the threading dislocations 375. The primary light absorption region 390 may absorb most of the photons because it is relatively large compared with the region occupied by the threading dislocations 375. Recombination of electron-hole pairs at the threading dislocations 375 may therefore be a secondary effect and not significantly reduce solar cell efficiency.
A semiconductor material is conformally grown around the top and sides of the active diode region 380 to create the top diode region 395. Again, coalescence defects 400 may appear in the top diode region 395 where the growth fronts from adjacent fins merge.
A top electrical contact 410 is grown onto the top surface of the top diode region 395 and a bottom electrical contact 415 is grown onto the bottom of the silicon substrate 155. In a solar cell, the influence of the coalescence defects 400 can be mitigated by covering them with the top electrical contact 410.
The embodiment shown in
In some applications, the presence of the silicon substrate can degrade the performance of the device. For example, for light-emitting diodes emitting in certain wavelength ranges, the silicon may absorb the light. An exemplary device architecture that can remove the silicon substrate is shown in
A “handle” substrate or surface 430 is bonded to the top diode region 195, as shown in
The handle substrate 430 may be electrically conductive, or it may contain conductor elements which will serve as contacts for the top diode region 195. Bonding methods are well known in the art, including methods used in flip-chip bonding where the “top” portion of an LED is bonded to a surface that is part of an LED package.
The initial silicon substrate 155 is removed by one or more methods such as grinding, etching with a chemical such as tetramethyl ammonium hydroxide, or laser ablation, all of which are well known to those skilled in the art.
As shown in
It may be useful to select reflective materials for the contacts 435 and 440 in order to induce light to exit the LED in the most favorable direction.
The embodiment shown in
One example of an alternate method of creating the embodiment of
An alternative way to reduce or minimize absorption of light by the silicon substrate is to incorporate a reflector above the silicon substrate. The embodiment shown in
To build this structure, a substrate 500 made from a material such as (111)-surface silicon, doped either p-type or n-type, depending on the configuration of the diode device, is provided, as shown in
A trench is patterned in the structure by photolithography and/or reactive ion etch.
Dielectric spacers 550 are created on the sidewalls of the trench by conventional methods. In the spacer process, all exposed surfaces (sidewalls of the second layer of dielectric material 530, the refractory metal 520, and the first layer of dielectric material 510, and the exposed surface of the silicon substrate 500 at the bottom of the trench) are conformally coated with a layer of dielectric material, such as SiO2. The dielectric material is subjected to a brief anisotropic reactive ion etch, which selectively removes all the SiO2 coating horizontal surfaces but leaves intact the SiO2 coating vertical surfaces. This process yields dielectric spacers 550. It leaves no metal exposed.
Optionally, the exposed surface of the silicon substrate 500 at the bottom of the trench may be cleaned by methods described above.
Growth conditions which favor growth perpendicular to the plane of the silicon substrate 500 and suppress growth parallel to the plane of the silicon substrate 500 are selected, as described in the paper by Noborisaka and his colleagues cited above. A semiconductor material is grown to form a free-standing bottom diode region 570 which fills the trench and extends upward in the shape of a fin. The growth of the semiconductor material may be performed using MOCVD. The process window (e.g., the conditions of temperature and pressure) for this growth step may be narrow because the semiconductor material for the bottom diode region cannot be allowed to nucleate on either the dielectric spacers 550 or the second dielectric layer 530.
Threading dislocations 560 may propagate upward, e.g., at a 45 degree angle from the interface between the bottom diode region 570 and the silicon substrate 500, intersect the dielectric spacers 550, and terminate within a trapping region 555. In order to trap substantially all of the threading dislocations, it is preferred that the aspect ratio of the trapping region (the ratio of the height of the dielectric spacers 550 to the width of the trench between the spacers 550) be greater than or equal to 1.
Growth conditions are selected so that the semiconductor material for the active diode region 580 will grow at approximately equal rates on the side of the fin and on the top of the fin. A semiconductor material is conformally grown around the top and sides of the bottom diode region to create an active diode region 580.
The sample is removed from the reactor, such as a MOCVD reactor if MOCVD is used, and the second layer of dielectric material 530 is removed from the structure by a wet selective etch. For example, if the dielectric material is silicon nitride, then hot phosphoric acid can be a good etchant.
The structure is returned to the reactor. Growth conditions are selected so that the semiconductor material for the top diode region 590, as shown in
Optionally, it can be advantageous to cover the top diode region 590 and the horizontal layer of semiconductor material 595 with a third layer of dielectric material 600 such as silicon dioxide.
Standard techniques are employed to create a via 605 through the third layer of dielectric material 600 and through the horizontal layer of semiconductor material 595, as shown in
Finally, the via 605 is filled by depositing a suitable material 620, such as a plug of tungsten or another suitable material such as would be known in the art, terminating in the top electrical contact 630, as shown in
In the illustrated embodiment of the structure shown in
One example of an alternative to the embodiment illustrated in
The embodiment shown in
A semiconductor material is grown to create the bottom diode region 730, as shown in
As in other embodiments, the ratio of the depth to the hole 720 to the diameter of the hole 720 is preferably greater than or equal to 1 in order for the structure to be able to trap threading dislocations. Threading dislocations 740 may form at the interface between the bottom diode region 730 and the silicon substrate 700. These threading dislocations may propagate upward at an angle, intersect the sidewalls of the dielectric layer 710, and terminate within the trapping region 750, such that there may be relatively defect-free gallium nitride in the upper portion of the bottom diode region 730.
A semiconductor material is conformally grown around the pyramidal bottom diode region 730 to form the active diode region 760.
A semiconductor material is conformally grown around the pyramidal active diode region 760 to create the top diode region 770. As an option, it may be possible to grow the semiconductor material for the top diode region 770 in such a way that the top diode regions 770 on adjacent diodes merge. The advantage of this strategy may be that a single strip of metal serving as a top electrical contact 780 provides current for multiple diodes because current can flow through the top diode region 770 from one diode to the next.
Finally, top electrical contact 780 and a bottom electrical contact 790 are created. The top electrical contact 780 can be, for example, a strip of metal or a film of transparent conductor such as indium tin oxide. It may be useful to reduce or minimize the area devoted to the top electrical contact 780 because the top electrical contact 780 blocks the light emitted by the device. Even a “transparent” contact typically will not be 100% transmissive.
The structure shown in
As an alternate architecture, the embodiment illustrated in
Following are examples of process parameters to form the bottom, active, and top diode regions according to embodiments in this disclosure. First, a substrate and a patterned dielectric layer as known in the art are provided. Exemplary process parameters of growth conditions (e.g., CVD) for bottom, active, and top diode regions, for a GaN and InGaN-based LED, according to the embodiment of
The embodiment shown in.
The embodiment shown in
A III-nitride semiconductor material is conformally grown around the top and sides of the bottom diode region 730 to create an active diode region 760.
A III-nitride semiconductor material is conformally grown around the top and sides of the active diode region 760 to form a top diode region 800. In this case, the top diode region 800 continues to grow until the growth fronts from adjacent diodes coalesce. An optional step is to planarize the resultant surface of the top diode region 800, which can be preferable depending on the quality of that surface.
The structure is inverted, and a handle substrate 810 is bonded to the surface of the top diode region 800 (which is now on the bottom of the structure), as shown in
The initial silicon substrate 700 is removed by one or more methods such as grinding, etching with a chemical such as tetramethyl ammonium hydroxide, or laser ablation.
Top electrical contact 820 and bottom electrical contact 830 are created to generate the completed structure shown in
The embodiment of
The embodiment shown in
Embodiments of the disclosure provide novel and useful architectures for diodes made from compound semiconductors or other non-lattice-matched semiconductors deposited on silicon substrates by Aspect Ratio Trapping. The semiconductor diode is the fundamental building block of solar cells, light-emitting diodes, resonant tunneling diodes, semiconductor lasers, and other devices.
One aspect of the present disclosure is to reduce the costs of solar cells, light-emitting diodes, and other compound semiconductor devices by creating them on high-quality, large-area, low-cost silicon wafers instead of smaller, more expensive substrates.
Another aspect of the present disclosure is to improve the extraction efficiency and the internal quantum efficiency of light-emitting diodes by exploiting non-polar planes of III-nitride semiconductors.
As such, one embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material disposed in and above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The substrate may be a single crystal silicon wafer, and may have a crystal orientation of (111) or (100). The dielectric material may comprise silicon dioxide or silicon nitride. The semiconductor material may comprise a Group III-V compound, a Group II-VI compound, a Group IV alloy, or combinations thereof.
The active diode region may comprise a p-n junction formed by a junction of the top and bottom diode materials. The active diode region may comprise a material different from the top and bottom diode materials, and the active diode region may form an intrinsic region of a p-i-n junction formed between the top and bottom diode materials. The active diode region may comprise multiple quantum wells formed between the top and bottom diode materials.
The opening may be a trench or may be a hole having an aspect ratio of at least 1 in two perpendicular axes.
The bottom diode material may include an n-type dopant, and the top diode material may include a p-type dopant.
The upper region of the bottom diode material may form a fin above the opening. The upper region of the bottom diode material may form a pillar above the opening.
The diode may further comprises a contact formed over the top diode region. The contact may comprise a transparent conductor. The diode may further comprise a second contact formed adjacent the substrate.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric material including an opening that exposes a portion of the substrate, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the lower region including a plurality of misfit dislocations that terminate below the upper region, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active light emitting diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
The active light emitting diode region may comprise a p-n junction formed by a junction of the top and bottom diode materials. The active light emitting diode region may comprise a material different from the top and bottom diode materials, and the active light emitting diode region may form an intrinsic region of a p-i-n junction formed between the top and bottom diode materials. The active light emitting diode region may comprise multiple quantum wells formed between the top and bottom diode materials.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The substrate may be a single crystal silicon wafer. The single crystal silicon wafer may have a crystal orientation of (111) or (100). The dielectric material may comprise silicon dioxide or silicon nitride. The semiconductor material may comprise a Group III-V compound, a Group II-VI compound, a Group IV alloy, or combinations thereof.
The opening may be a trench or may be a hole having an aspect ratio of at least 1 in two perpendicular axes.
The bottom diode material may include an n-type dopant and the top diode material includes a p-type dopant. The upper region of the bottom diode material may form a fin above the opening. The upper region of the bottom diode material may form a pillar above the opening.
The diode may further comprises a contact formed over the top diode region. The contact may comprises a transparent conductor. The diode may further comprise a second contact formed adjacent the substrate.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric layer having a thickness of no more than about 20 nm above the substrate, the dielectric layer including an opening that exposes a portion of the substrate, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
The active diode region may comprise a p-n junction formed by a junction of the top and bottom diode materials. The active diode region may comprise a material different from the top and bottom diode materials, and the active diode region may form an intrinsic region of a p-i-n junction formed between the top and bottom diode materials. The active diode region may comprise multiple quantum wells formed between the top and bottom diode materials.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The substrate may be a single crystal silicon wafer. The single crystal silicon wafer may have a crystal orientation of (111) or (100). The dielectric material may comprise silicon dioxide or silicon nitride. The semiconductor material may comprise a Group III-V compound, a Group II-VI compound, a Group IV alloy, or combinations thereof.
The opening may be a trench or may be a hole having an aspect ratio of at least 1 in two perpendicular axes.
The bottom diode material may include an n-type dopant and the top diode material may include a p-type dopant. The upper region of the bottom diode material may form a fin above the opening. The upper region of the bottom diode material may form a pillar above the opening.
The diode may further comprise a contact formed over the top diode region. The contact may comprise a transparent conductor. The diode may further comprise a second contact formed adjacent the substrate.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric material disposed above the substrate, the dielectric material including a plurality of openings that each expose a portion of the substrate, a plurality of bottom diode sections comprising a bottom diode material, each section including a lower region disposed in an opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a contiguous top diode section proximate the upper regions of the bottom diode section, the top diode section comprising a top diode material, and a plurality of active diode regions between the top and bottom diode materials, the active diode regions each including a surface extending away from the top surface of the substrate.
The plurality of active diode regions may comprise a p-n junction formed by a junction of the contiguous top and plurality of bottom diode materials. The plurality of active diode regions may comprise a material different from the contiguous top and plurality of bottom diode materials, and the plurality of active diode regions may form an intrinsic region of a p-i-n junction formed between the contiguous top and plurality of bottom diode materials. The plurality of active diode regions may comprise multiple quantum wells formed between the contiguous top and plurality of bottom diode materials.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The substrate may be a single crystal silicon wafer. The single crystal silicon wafer may have a crystal orientation of (111) or (100). The dielectric material may comprise silicon dioxide or silicon nitride. The semiconductor material may comprise a Group III-V compound, a Group II-VI compound, a Group IV alloy, or combinations thereof.
The opening may be a trench or may be a hole having an aspect ratio of at least 1 in two perpendicular axes.
The bottom diode material may include an n-type dopant and the top diode material may include a p-type dopant. The upper regions of the plurality of bottom diode materials may form a fin above the opening. The upper regions of the plurality of bottom diode materials may form a pillar above the opening.
The diode may further comprise a contact formed over the contiguous top diode region. The contact may comprise a transparent conductor. The diode may further comprise a second contact formed adjacent the substrate.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a bottom diode material that is lattice mismatched to the substrate extending above the top surface and including a bottom diode section having a width across the top surface and a height above the top surface, the height being greater than the width, a top diode material proximate the bottom diode material, and an active light emitting diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
The active light emitting diode region may comprise a p-n junction formed by a junction of the top and bottom diode materials. The active light emitting diode region may comprise a material different from the top and bottom diode materials, and the active light emitting diode region may form an intrinsic region of a p-i-n junction formed between the top and bottom diode materials. The active light emitting diode region may comprise multiple quantum wells formed between the top and bottom diode materials.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The substrate may be a single crystal silicon wafer. The single crystal silicon wafer may have a crystal orientation of (111) or (100). The dielectric material may comprise silicon dioxide or silicon nitride.
The bottom diode material may include an n-type dopant and the top diode material may include a p-type dopant.
The diode may further comprise a contact formed over the top diode region. The contact may comprise a transparent conductor. The diode may further comprise a second contact formed adjacent the substrate.
Another embodiment of the present disclosure is directed to a method of making a diode, the method comprising depositing a layer of a dielectric material onto a substrate, patterning first and second openings in the dielectric material to expose portions of the substrate, each of the openings having an aspect ratio of at least 1, forming a first bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in and above the first opening, forming a second bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in and above the second opening, forming a first active diode region adjacent the first bottom diode region, forming a second active diode region adjacent the second bottom diode region, and forming a single top diode region adjacent the first active diode region and the second active diode region.
The first and second active diode regions may contain multiple quantum wells.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The substrate may be a single crystal silicon wafer. The substrate may have a crystal orientation of (111) or (100). The dielectric material may comprise silicon dioxide or silicon nitride.
The first and second openings may be trenches or may be holes. The semiconductor material may comprise a Group III-V compound, a Group II-VI compound, a Group IV alloy, or combinations thereof.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric material above the substrate, the dielectric material including an array of openings, a plurality of bottom diode sections formed in and above the array of openings, each bottom diode section including at least one sidewall that extends away from the dielectric material, the bottom diode sections comprising a semiconductor material that is lattice mismatched to the substrate, a plurality of top diode sections proximate the bottom diode sections, and a plurality of active diode regions between the top and bottom diode sections, the active diode regions each including a surface extending away from the top surface of the substrate.
Each opening may have an aspect ratio of at least 0.5, at least 1, at least 2 or greater than 3. Each bottom diode section may include at least one sidewall that extends substantially vertically upward above the dielectric material. Each bottom diode section may have an hexagonal cross-section. The openings may be arranged in an hexagonal array. The top diode sections may be formed from a single, contiguous layer of material. The diode may be a light emitting diode.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a first dielectric layer above the substrate, a layer of a refractory metal above the first dielectric layer, an opening through the first dielectric layer and the layer of refractory metal, the opening having dielectric sidewalls, a bottom diode region comprising a compound semiconductor material that is lattice mismatched to the substrate, the bottom diode region disposed in and above the opening, a top diode region proximate the bottom diode region, and an active diode region between the top diode region and a top portion of the bottom diode region.
The opening may have an aspect ratio of at least 1, and may be a trench. The diode may further comprise a second dielectric layer covering at least a portion of the top diode region. The diode may further comprise a second opening extending through the second dielectric layer and a first contact comprising a metal plug, the metal plug filling the second opening and contacting the layer of refractory metal. The diode may further comprise a second contact at the bottom of the substrate.
Another embodiment of the present disclosure is directed to a method of making a diode, the method comprising depositing a first layer of dielectric material above a substrate, depositing a layer of a refractory metal above the first layer of dielectric material, depositing a second layer of dielectric material above the layer of refractory material, forming a first opening defined by sidewalls extending through the first layer of dielectric material, layer of refractory metal, and second layer of dielectric material to expose a surface of the substrate, forming a layer of dielectric material on the sidewalls of the opening, forming a bottom diode region by growing a compound semiconductor material that is lattice mismatched to the substrate in and above the opening, removing the second dielectric layer, forming an active diode region adjacent a portion of the bottom diode region, and forming a top diode region that adjacent the active diode region.
The method may further comprise depositing a third layer of dielectric material on the top diode region that conformally covers the active diode region and the refractory metal, creating a via through the third layer of dielectric material and a portion of the top diode region that covers the refractory metal, filling the via with a plug a metal such that the plug is in contact with the layer of refractory metal, and fabricating a bottom electrical contact.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric layer above the substrate, the dielectric layer including an opening having an aspect ratio of at least 1, a bottom diode region disposed in and above the opening, the bottom diode region comprising a compound semiconductor material having an hexagonal crystal lattice, the bottom diode region including sidewalls defined by non-polar planes of the compound semiconductor material, a top diode region proximate the bottom diode region, and an active diode region between the top and bottom diode regions.
The substrate may be a crystalline substrate having a cubic lattice. The non-polar plane may be an a-plane or may be an m-plane. The opening may be a trench or may be a hole.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric layer above the substrate including an opening, a semiconductor material that is lattice mismatched to the substrate disposed in the opening, and a pyramidal diode comprising a pyramidal p-n junction disposed above the opening.
The pyramidal diode may further include a top diode material, an active diode material, and a bottom diode material. The pyramidal diode may have a height of greater than about 3 microns or may have a height of greater than about 5 microns. The pyramidal diode may include a top contact layer having a thickness of less than about 2 microns, or a top contact layer having a thickness of less than about 0.5 microns. The pyramidal diode may include a bottom contact layer.
The diode may further comprise multiple pyramidal diodes having the respective top diode materials coalesced together. The diode may further include a transparent top contact layer. The diode may further include a handle substrate.
The substrate may be selected from the group consisting of silicon, sapphire, and silicon carbide. The semiconductor material may be selected from the group consisting of a Group III-V compound, a Group II-VI compound, and a Group IV alloy.
Another embodiment of the present disclosure is directed to a method of forming a diode comprising providing a substrate, providing a dielectric including an opening having an aspect ratio of at least 1 above the substrate, forming a compound semiconductor material that is lattice mismatched to the substrate in the opening, forming a diode comprising a p-n junction above the opening, forming a dielectric material having a substantially planar surface above the diode, bonding a handle wafer to the substantially planar surface, and removing the substrate.
The opening may be a trench or may be a hole. The diode may include a top diode region, a bottom diode region, and an active diode region. The diode may include a plurality of top diode regions, a plurality of bottom diode regions, and a plurality of active diode regions. The plurality of top diode regions may be coalesced together.
Another embodiment of the present disclosure is directed to a diode comprising a substrate, a dielectric layer above the substrate including an array of openings, the openings having a width less than 100 nm, a plurality of nanostructures comprising a semiconductor material that is lattice mismatched to the substrate disposed in and above the array of openings, the nanostructures having a substantially uniform height extending at least 100 nm above the dielectric layer, and a plurality of diode junctions formed on the nanostructures, the diode junctions including active regions using the nanostructure sidewalls.
The nanostructures may be in the form of a fin or pillar. The width of the nanostructure may be selected from the group consisting of about 5 nm, about 10 nm, about 20 nm, and about 50 nm. The height of the nanostructure may be selected from the group consisting of about 100 nm, about 200 nm, about 500 nm, and about 1000 nm.
Another embodiment of the present disclosure is directed to a diode comprising a first diode material comprising a substantially planar bottom surface and a top surface having a plurality of cavities, a second diode material comprising a substantially planar top surface and a bottom surface extending into the plurality of cavities in the first diode material, and an active diode region between the first and second diode materials.
The diode may further comprise a substrate having a substantially planar surface adjacent the bottom surface of the first diode material or the top surface of the second diode material.
The active diode region may comprise a p-n junction formed by a junction of the first and second diode materials. The active diode region may comprise a material different from the first and second diode materials, and the active diode region may form an intrinsic region of a p-i-n junction formed between the first and second diode materials. The active diode region may comprise multiple quantum wells formed between the first and second diode materials.
A first diode material may comprise a III-V material. The first diode material may comprise GaN. The cavities may include a polar GaN surface.
The cavities may define trenches or may define holes having an aspect ratio of at least 1. The surface area of the cavities may exceed the surface area of the bottom surface of the first diode material. The surface area of the cavities may be at least 150% of the surface area of the bottom surface of the first diode material, or may be at least 200% of the surface area of the bottom surface of the first diode material.
Embodiments of the application provide methods, structures or apparatus described with respect to “fin” configured structures based on growth control from trench orientations. As would be recognized by one skilled in the art based on the disclosure herein, the trench orientation could be another shaped opening such as a hole, recess, square or ring, for example, which would result in other three-dimensional semiconductor structures or apparatus.
Embodiments of the application provide methods, structures or apparatus that may use and/or form by epitaxial growth or the like. For example, exemplary suitable epitaxial growth systems may be a single-wafer or multiple-wafer batch reactor. Various CVD techniques may be used. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or EPSILON single-wafer epitaxial reactors available from ASM International based in Bilthoven, The Netherlands.
Any reference in this specification to “one embodiment,” “an embodiment,” “example embodiment,” “another embodiment,” “other embodiments,” etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to affect such feature, structure, or characteristic in connection with other ones of the embodiments. Furthermore, for ease of understanding, certain method procedures may have been delineated as separate procedures; however, these separately delineated procedures should not be construed as necessarily order dependent in their performance. That is, some procedures may be able to be performed in an alternative ordering, simultaneously, etc. In addition, exemplary diagrams illustrate various methods in accordance with embodiments of the present disclosure. Such exemplary method embodiments are described herein using and can be applied to corresponding apparatus embodiments, however, the method embodiments are not intended to be limited thereby.
Although few embodiments of the present invention have been illustrated and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. As used in this disclosure, the term “preferably” is non-exclusive and means “preferably, but not limited to.” Terms in the claims should be given their broadest interpretation consistent with the general inventive concept as set forth in this description. For example, the terms “coupled” and “connect” (and derivations thereof) are used to connote both direct and indirect connections/couplings. As another example, “having” and “including”, derivatives thereof and similar transitional terms or phrases are used synonymously with “comprising” (i.e., all are considered “open ended” terms)—only the phrases “consisting of” and “consisting essentially of” should be considered as “close ended”. Claims are not intended to be interpreted under 112 sixth paragraph unless the phrase “means for” and an associated function appear in a claim and the claim fails to recite sufficient structure to perform such function.
This application is a divisional of U.S. patent application Ser. No. 14/983,138, filed Dec. 29, 2015, entitled “DIODE-BASED DEVICES AND METHODS FOR MAKING THE SAME,” which is a divisional of U.S. patent application Ser. No. 14/675,277, filed on Mar. 31, 2015, (now U.S. Pat. No. 9,231,073, issued Jan. 5, 2016), entitled “DIODE-BASED DEVICES AND METHODS FOR MAKING THE SAME,” which is a divisional of U.S. patent application Ser. No. 13/554,516, filed on Jul. 20, 2012, (now U.S. Pat. No. 9,040,331 issued on May 26, 2015), entitled “DIODE-BASED DEVICES AND METHODS FOR MAKING THE SAME,” which is a divisional of U.S. patent application Ser. No. 12/684,797, filed on Jan. 8, 2010, (now U.S. Pat. No. 8,237,151 issued on Aug. 7, 2012) entitled “DIODE-BASED DEVICES AND METHODS FOR MAKING THE SAME,” which claims the benefit of U.S. Provisional Application No. 61/143,589, filed on Jan. 9, 2009, entitled “DIODE-BASED DEVICES AND METHODS FOR MAKING THE SAME,” the above applications are hereby incorporated herein by reference in their entireties. This application relates to the following co-pending and commonly assigned patent applications: U.S. patent application Ser. No. 12/100,131, filed Apr. 9, 2008, (now U.S. Pat. No. 9,508,890, Issued Nov. 29, 2016) entitled “PHOTOVOLTAICS ON SILICON,” which claims priority to U.S. Provisional Application No. 60/922,533, filed Apr. 9, 2007, entitled “PHOTOVOLTAICS ON SILICON,” which applications are both hereby incorporated by reference in their entirety; and U.S. patent application Ser. No. 12/684,499, filed Jan. 8, 2010, (now U.S. Pat. No. 8,304,805, Issued Nov. 6, 2012) entitled “Semiconductor Diodes Fabricated by Aspect Ratio Trapping with Coalesced Films,” which claims priority to U.S. Provisional Application No. 61/143,602, filed Jan. 9, 2009, entitled “Semiconductor Diodes Fabricated by Aspect Ratio Trapping with Coalesced Films,” which applications are hereby incorporated herein by reference in their entirety.
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