Patent Application
20230299195
A reduced surface field (RESURF) has been used to fabricate high-voltage linear devices such as for example lateral double-diffused metal-oxide-semiconductor (LDMOS). It is desirable to have a high-voltage linear device that has a high breakdown voltage and has a low on-resistance.
In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.
In another aspect, a method includes forming a double-diffused metal oxide semiconductor. The forming includes depositing a first silicon nitride on a well, depositing a first photoresist on the first silicon nitride, using a first photolithographic process to remove portions of the first photoresist to expose at least one portion of the first silicon nitride, performing a first etching of the first silicon nitride and the well depositing a first dielectric on a portion of the well etched by the first etching, removing the first silicon nitride, depositing a second silicon nitride on the well and an epitaxial layer, depositing a second photoresist on the second silicon nitride, using a second photolithographic process to remove portions of the second photoresist to expose at least one portion of the second silicon nitride, performing a second etching of the second silicon nitride, the well and the epitaxial layer, and depositing a second dielectric on a portion of the well and the epitaxial layer etched by the second etching. The second dielectric is in direct contact with the first dielectric.
The foregoing features may be more fully understood from the following description of the drawings. The drawings aid in explaining and understanding the disclosed technology. Since it is often impractical or impossible to illustrate and describe every possible embodiment, the provided figures depict one or more illustrative embodiments. Accordingly, the figures are not intended to limit the scope of the broad concepts, systems and techniques described herein. Like numbers in the figures denote like elements.
Described herein are techniques to fabricate a double-diffused metal-oxide-semiconductor (DMOS) transistor that includes a recessed dielectric and a non-recessed dielectric that is not recessed. In one example, the recessed dielectric enables a shorter electron path, which decreases an on-resistance of the DMOS transistor. In one example, the non-recessed dielectric provides an increased breakdown voltage by withstanding high voltage that may be applied to a drain of the DMOS transistor. In one example, the techniques described herein enable fabrication of a DMOS transistor that requires low Rsp (specific resistance) by reducing a width of a dielectric. The techniques described herein also enable the fabrication of a DMOS transistor that includes three reduced surface fields (RESURFs) to also increase a breakdown voltage of the DMOS and lower a Rsp of the DMOS.
Referring to
The dielectric 106 includes a dielectric 106a and a dielectric 106b. In one example, the dielectric 106a and the dielectric 106b are the same material. In one example the dielectric 106a and the dielectric 106b are silicon dioxide. In other examples, the dielectric 106a and the dielectric 106b are different materials.
The dielectric 106a extends a distance d1 in the Y-direction, and the dielectric 106b extends a distance d2 in the Y-direction. d1 corresponds to a thickness of the dielectric 106a and d2 corresponds to a thickness of the dielectric 106b. With d1>d2, the dielectric 106b is recessed or thinner with respect to the dielectric 106a.
The dielectric 106a is thick enough to protect the gate 104 from high voltage that may come from the drain 116 resulting from, for example, electrostatic discharge (ESD). By having the dielectric 106b thinner than the dielectric 106a, electrons that are activated during a high voltage event have a shorter path to traverse from the drain 116 to the source 110 than if the dielectric 106b was as thick as the dielectric 106a. A width of the dielectric 106a in the X-direction is shorter than traditional DMOS transistors and therefore the DMOS transistor 100 has a lower on-resistance than traditional DMOS transistors.
The deep n-type well 118 extends into the n-type epitaxial layer 124 at least 10,000 Angstroms ±2,000 Angstroms. In one example, the deep n-type well 118 is linearly doped.
The DMOS transistor 100 includes a reduced surface field (RESURF). The RESURF is formed by the polysilicon gate 104, the dielectric 106, and the n-type well 132.
Referring to
Process 200 deposits a first oxide layer (202). In one example, the first oxide layer is silicon dioxide. In one example, the first oxide layer is 200 Angstrom thick ±20 Angstroms. In one example, the first oxide layer is deposited on the deep n-type well 118 and the n-type well 132 (
Process 200 deposits a first silicon nitride (204). For example, a first silicon nitride layer is deposited on the first oxide layer, the deep n-type well 118 and the n-type well 132 (
Process 200 deposits a first photoresist (206) and uses a first a photolithographic process to remove at least a portion of the first photoresist (208). For example, a first photoresist is deposited on the first silicon nitride, and the photolithographic process is used to remove at least a portion of the first photoresist to expose at least a portion of the first silicon nitride and/or the first oxide layer that will be etched.
Process 200 performs a first etching (210). For example, the at least exposed portion of the first silicon nitride and/or first oxide layer is etched, and the deep n-type well 118 and the n-type well 132 (
Process 200 deposits a first dielectric (212). For example, a high-density-plasma (HDP) chemical vapor deposition (CVD) process is used to deposit the dielectric 106a (
Process 200 performs a first planarization (214). In one example, the first dielectric is planarized using a chemical-mechanical planarization (CMP) process. In one example, the first oxide layer applied in processing block 202 is also removed.
Process 200 removes the first silicon nitride (216). For example, the first silicon nitride is removed by phosphoric acid. In one example, the first photoresist is also removed.
Process 200 deposits a second oxide layer (218). In one example, the second oxide layer is silicon dioxide. In one example, the second oxide layer is 200 Angstrom thick ±20 Angstroms.
Process 200 deposits a second silicon nitride (220). For example, a second silicon nitride layer is deposited on the second oxide layer, the n-type epitaxial layer 124 and the n-well 132 (
Process 200 deposits a second photoresist (222) and uses a second a photolithographic process to remove at least a portion of the second photoresist (224). For example, a second photoresist is deposited on the second silicon nitride, and the photolithographic process is used to remove at least a portion of the second photoresist to expose at least a portion of the second silicon nitride and/or the second oxide layer that will be etched.
Process 200 performs a second etching (226). For example, the at least exposed portion of the second silicon nitride and/or the second oxide is etched, and the n-type epitaxial layer 124 and the n-type well 132 (
Process 200 deposits a second dielectric (228). For example, a HDP CVD process is used to deposit the dielectric 106b next to and in contact with the dielectric 106a (
Process 200 performs a second planarization (230). In one example, the second dielectric is planarized using a CMP process. In one example, the second oxide layer applied in processing block 218 is also removed.
Referring to
The DMOS transistor 300 includes a p-type region 302; a polysilicon gate 304a; dielectric 306; a source 310; a drain 316; a deep n-type well 318; n-epitaxial layer 324, which includes a first portion 324a, a second portion 324b and a third portion 324c; a n-type buried layer 328; a p-type substrate 330; a n-type well 332; a p-type well 336; a gate oxide 348 between the polysilicon gate 304 and the dielectric 106; and spacers 352a, 352 on each side of the polysilicon gate 304.
The DMOS transistor 300 also includes a via 362 connected to the source 310; a metal layer 364 connected to the via 362; a P+ region 342 disposed between the p-type well 336 and the source 310; and a N+ region 344 next to the P+ region 342 and disposed between the p-type well 336 and the source 310.
The DMOS transistor 300 has three RESURFs or a triple RESURF. The three RESURFs include the n-type epitaxial layer 324c, n-type well 332, the deep n-type well 318, the p-type well 336, the p-type region 302 and the n-type buried layer 328. The n-type epitaxial layer 324c, the n-type well 332 and the deep n-type well 318 are linearly doped in the drift region resulting in a double RESURF. The p-type well 336, the p-type region 302 and the n-type buried layer 328 form the triple RESURF by completely depleting the p-type region 302 because of the high doping (e.g., on the order of 1×1019/cm3) of the n-type buried layer 328. The n-type buried layer 328 also isolates the p-type well 336 and the p-type region 302 from the p-type substrate 330 by preventing minority carrier flowing into p-type substrate 330.
In addition, the DMOS transistor 300 is configured to provide a decrease in on-resistance compared to traditional devices. For example, the p-type well 336 provides a very shallow channel length of about 0.1 microns that decreases on-resistance by 10 to 20% from a nominal Rsp with a longer channel such as 0.3 um.
The processes described herein are not limited to the specific examples described. For example, the process 200 is not limited to the specific processing order of
Having described embodiments, which serve to illustrate various concepts, structures, and techniques, which are the subject of this patent, it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts, structures and techniques may be used.
Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
