1. Field of Invention
This invention relates to a dynamic random access memory (DRAM) structure with buried word lines and a process of fabricating the same, and to an integrated circuit (IC) structure and a process of fabricating the same.
2. Description of Related Art
A conventional DRAM cell includes a transistor and a capacitor coupled thereto. When the integration degree of DRAM increases beyond a certain level, the channel length of a traditional planar transistor is reduced to cause the short channel effects that include the drain-induced barrier lowering (DIBL) and so forth. The shrinking of the device size also reduces the distance between word lines and bit lines, and eventually induces parasitic capacitance to build up between such word lines and bit lines.
A buried word line (buried-WL) DRAM structure having word lines buried in the substrate is one approach to deal with the problem.
The isolation word lines 120b are applied with a voltage independent from the voltage on the cell word lines 120a to reduce the static and dynamic coupling between adjacent cells. However, when the structure is further scaled down, the conventional design of isolation word lines is insufficient in the isolation effect.
On the other hand, there are certain other IC structures with conductors buried in the substrate. The buried conductors are usually separated from the substrate by an insulator when the material of the substrate is not insulating.
Accordingly, this invention provides a DRAM structure with buried word lines.
This invention also provides a fabricating process of the DRAM structure.
This invention further provides an integrated circuit (IC) structure with buried conductors that covers the DRAM structure in scope, and a fabricating process thereof.
The DRAM structure of this invention includes a semiconductor substrate, a plurality of cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and a plurality of isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.
In an embodiment, the top surfaces of the isolation word lines are substantially coplanar with those of the cell word lines. In anther embodiment, the top surfaces of the isolation word lines are lower than the top surfaces of the cell word lines but higher than the bottom surfaces of the cell word lines. In still another embodiment, the top surfaces of the isolation word lines are substantially coplanar with the bottom surfaces of the cell word lines, or are even lower than the bottom surfaces of the cell word lines. Usually, the cell word lines are divided into a plurality of pairs of cell word lines, and each pair is separated from a neighboring pair by an isolation word line.
The fabricating process of a DRAM structure with buried word lines of this invention is described as follows. A plurality of first trenches and a plurality of second trenches deeper than the first trenches are formed in a semiconductor substrate. A gate dielectric layer is formed in each of the first and the second trenches. Cell word lines are formed in the first trenches and isolation word lines formed in the second trenches.
In an embodiment, the first trenches and the second trenches with two different depths are defined by two lithography processes. A first mask layer having therein patterns of the first trenches and patterns of the second trenches is formed over the substrate. A second mask layer is formed covering the patterns of the first trenches. The substrate is etched using the first and the second mask layers as a mask to form the second trenches. After the second mask layer is removed, the substrate is etched using the first mask layer as a mask to form the first trenches and deepen the second trenches.
In another embodiment, the first trenches and the second trenches with different depths are defined by one lithography process. A plurality of mask patterns is formed over the substrate. A first spacer is formed on the sidewalls of each mask pattern. A second spacer is formed on the sidewall of each first spacer. The substrate is etched using the mask patterns, the first spacers and the second spacers as a mask to form the second trenches. Top portions of the mask patterns, top portions of the first spacers and top portions of the second spacers are removed. The remaining first spacers are removed. The substrate is etched using the remaining mask patterns and the remaining second spacers as a mask to form the first trenches and deepen the second trenches.
Since the bottom surfaces of the isolation word lines are lower than those of the cell word lines, the isolation effect between adjacent cells is improved. Further, when the top surfaces of the isolation word lines are lower than those of the cell word lines, the parasitic capacitance between the isolation word lines and the cell word lines and that between the isolation word lines and the bit lines are both decreased.
The IC structure with buried conductors of this invention includes a substrate, a plurality of first conductors buried in the substrate, and a plurality of second conductors buried in the substrate. The bottom surfaces of the second conductors are lower than those of the first conductors.
The fabricating process of an IC structure of this invention is described below. A plurality of first trenches and a plurality of second trenches deeper than the first trenches are formed in a substrate. A plurality of first conductors is formed in the first trenches and a plurality of second conductors formed in the second trenches. The first trenches and the second trenches may be defined by one or two lithography processes as mentioned above.
In order to make the aforementioned and other objects, features and advantages of this invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
This invention is further explained with the following embodiments referring to the accompanying drawings, which are not intended to limit the scope of this invention. Specifically, although the following embodiments all relate to DRAM structures with buried lines and their fabrications, this invention can be readily applied to various other IC structures with buried conductors and their fabrications based on the teachings of the following descriptions for the embodiments.
Referring to
The top surfaces 222a of the cell word lines 220a and the top surfaces 222b of the isolation word lines 220b are lower than the top surface 202 of the substrate 200. The bottom surfaces 224b of the isolation word lines 220b are lower than the bottom surfaces 224a of the cell word lines 220a. The common source regions 240a and the drain regions 240b are formed in portions of the substrate 200 between the trenches 210a/b.
Each isolation word line 220b is disposed between two cell word lines 220a. The cell word lines 220a are divided into a plurality of pairs of cell word lines, and each pair is separated from a neighboring pair by an isolation word line 220b.
The drain region 240b, a common source region 240a, a portion of a cell word line 220a between them, the gate dielectric layer 230 and the channel 226 beside the portion of the cell word line 220a constitute a MOSFET transistor 228. Each common source regions 240a is shared by a pair of neighboring memory cells. It is noted that the capacitors coupled to the drain regions 240b and the bit lines coupled to the common source regions 240a are omitted in the figure for simplicity, as in the case of
In this embodiment, the top surfaces 222b of the isolation word lines 220b are substantially coplanar with the top surfaces 222a of the cell word lines 220a. The cell word lines 220a and the isolation word lines 220b may both include a metallic material, such as titanium nitride (TiN), tantalum nitride (TaN), W or poly-Si, for reducing the electrical resistance. The gate dielectric layers 230 may include silicon dioxide (SiO2) or SiN.
The distance between the top surface of each word line 220a/b and the top surface 202 of the substrate 200 ranges from 700 to 800 angstroms, and the thickness of each cell word line 220a ranges from 700 to 800 angstroms. It is feasible that the bottom surfaces 224b of the isolation word lines 220b are lower than the bottom surfaces 224a of the cell word lines 220a by no more than 800 angstroms.
Though in the first embodiment the top surfaces 222b of the isolation word lines 220b are substantially coplanar with the top surfaces 222a of the cell word lines 220a, the top surfaces of the isolation word lines may alternatively be lower than those of the cell word lines to reduce the overlap area between them and the cell word lines as well as to increase the distance between them and the bit lines. As a result, the parasitic capacitance between the isolation word lines and the cell word lines and that between the isolation word lines and the bit lines both can be reduced to improve the performance of the DRAM. Two such cases are described below, as second and third embodiments of this invention.
Referring to
Nevertheless, the second trenches 210c may alternatively be formed deeper than the second trenches 210b formed in the first embodiment to maintain the thickness of the isolation word lines 220c and the electrical conductivity of the same.
Referring to
In such embodiment, there is substantially no overlap area between the isolation word lines 220d and the cell word lines 220a, so that the parasitic capacitance between the isolation word lines 220d and the cell word lines 220a is minimized.
On the other hand, the fabricating process of a buried-WL DRAM structure of this invention features the formation of two groups of trenches with two different depths, wherein the shallower trenches are for forming the cell word lines and the deeper ones for forming the isolation word line. The first and the second trenches with different depths can be defined by one or two lithography processes, as exemplified below.
Referring to
The DARC 508 and the TC/AC layer 506 are then etched in sequence using the spacer patterns 510 as a mask to form a first mask layer 512, which has therein trench patterns 514a for defining the trenches of the cell word lines and trench patterns 514b for defining the trenches of the isolation word lines.
The conductor layer 502 is for the formation of periphery devices (not shown), and may include doped poly-Si or undoped poly-Si. The hard mask layer 504 may include silicon nitride (SiN) or SiO2. The TC/AC layer 506 is for the etching of the hard mask layer 504. The DARC 508 may include SiON. The spacer patterns 510 may include silicon oxide or SiN.
It is noted that though the first mask layer 512 includes three layers (506, 508 and 510) in this embodiment, the first mask layer may alternatively consists of a single layer or two layers. For example, the first mask layer may consist of a single layer of spacer patterns formed in a similar way as in the case of the above spacer patterns 510.
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The cell word lines 524a and the isolation word lines 524b may be formed by forming a conductive layer (not shown) filling up all the trenches 518 and 520 and then etching back the conductive layer to a predetermined level.
When the cell word lines 524a and the isolation word lines 524b are designed to have coplanar top surfaces as shown in
It is noted that the subsequent process of forming source/drain (S/D) regions and the bit lines and storage capacitors coupled to the S/D regions is not illustrated in the drawings, because it is well known to a person of ordinary skill in the art.
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The materials of the first spacers 608 and the second spacers 610 depend on that of the hard mask patterns 604a, wherein the material of the first spacers 608 requires a much higher etching selectivity than those of the hard mask patterns 604a and second spacers 610 in a certain etchant so that the first spacers 608 can be removed by wet etching without loss of the hard mask patterns 604a and the second spacers 610. For example, when the mask patterns 604a include SiN, it is feasible that the first spacers 608 include silicon oxide and the second spacers 610 include. SiN.
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Thereafter, a gate dielectric layer, cell word lines and isolation word lines, and a trench-sealing insulator are formed (not shown) as in the fourth embodiment, possibly in a manner similar to the manner in which the gate dielectric layer 520, the cell word lines 524a, the isolation word lines 524b and the trench-sealing insulator 526 are formed as described in the paragraphs relating to
In a case of this embodiment, the ratio of the distance between two neighboring hard mask patterns 604a to the width of each hard mask pattern 604a is equal to 5 (
The subsequent process of forming S/D regions, bit lines and capacitors is either not illustrated here since it is well known to a person of ordinary skill in the art.
It is also noted that although a conductive layer (502 or 602) is formed on the substrate before the hard mask layer (504 or 604) is formed in the above embodiments for etch stopping in patterning the hard mask layer 504/604 and for the gate electrodes of periphery devices, the conductive layer may alternatively be omitted when the gate electrodes of the periphery devices are formed after the buried WLs are defined.
Since the bottom surfaces of the isolation word lines are lower than those of the cell word lines in the buried-WL DRAM structure of this invention, the isolation effect between adjacent cells is improved as compared to the prior art where the bottom surfaces of the isolation word lines are coplanar with those of the cell word lines.
Moreover, when the top surfaces of the isolation word lines are lower than those of the cell word lines, the parasitic capacitance between the isolation word lines and the cell word lines and that between the isolation word lines and the bit lines are both decreased. Consequently, the performance of the DRAM can be further improved.
It is also noted that though the above fabricating process is for forming cell word lines and deeper isolation word lines buried in the substrate for a DRAM structure, it can also be applied to the fabrication of other IC structures with buried conductors to form trenches with different depths and thereby make different depths for the buried conductors.
This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.
This application is a divisional of and claims priority benefit of an application Ser. No. 13/109,002, filed on May 17, 2011, now pending. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
Number | Date | Country | |
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Parent | 13109002 | May 2011 | US |
Child | 14047018 | US |