Patent Application
20120153975
1. Field of the Invention
The present invention relates to a driver circuit configured to output a signal via a transmission line.
2. Description of the Related Art
In order to evaluate and test a semiconductor device (DUT: device under test), a semiconductor test apparatus (which will simply be referred to as the “test apparatus”) is employed. The test apparatus is configured to apply a test signal to a DUT, and, while controlling the state of the DUT, to compare an output signal of the DUT with an expected value, so as to judge the quality of the DUT. Such a test apparatus mounts a driver circuit configured to output a test signal to such a DUT.
There is a demand for such a driver mounted on a test apparatus to have a function for adjusting a positive edge (slope) transition time (rising time) Tr and a negative edge transition time (falling time) Tf.
A frontend comprising such a driver and a comparator included in a test apparatus (which is also referred to as “pin electronics”) is integrated using the CMOS process. However, such driver circuits described in Patent documents 1 through 4 are each configured to adjust the rising time Tr and the falling time Tf, which requires the driver circuit to include capacitors and diodes as additional components. This leads to low compatibility with the CMOS process, resulting in a problem of an increase in the circuit scale.
The present invention has been made in view of such a situation. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a driver circuit configured to be capable of adjusting at least one from among the waveform of a positive edge and the waveform of a negative edge.
An embodiment of the present invention relates to a driver circuit configured to output a signal to a transmission line. The driver circuit comprises: a branch circuit configured to branch a signal to be transmitted into multiple paths; multiple timing adjustment circuits, respectively provided to the multiple paths, which are each configured to apply a delay to at least one from among a positive edge and a negative edge of the signal to be transmitted thus branched into a corresponding path; and a combining output circuit configured to combine output signals of the multiple timing adjustment circuits, and to output the combined signal to the transmission line.
Such an embodiment is capable of controlling the waveform of the combined signal according to the amounts of delay applied by the respective timing adjustment circuits. Thus, such an arrangement is capable of controlling the transition time Tr and/or Tf.
Also, the combining output circuit may comprise: a voltage source configured to generate a predetermined voltage; a first resistor configured to receive the predetermined voltage via its first terminal; a second resistor configured to receive the predetermined voltage via its first terminal; multiple differential pairs, provided to the multiple respective paths, which each comprise a first transistor arranged such that its first terminal is connected to a second terminal of the first resistor, and a second transistor arranged such that its first terminal is connected to a second terminal of the second resistor and its second terminal is connected to a second terminal of the first transistor so as to form a common second terminal; a constant current circuit configured to supply a tail current to the multiple differential pairs; and multiple differential conversion circuits, provided to the multiple respective paths, which are each configured to convert an output signal of the corresponding timing adjustment circuit into a differential signal, to output one component of the differential signal to a control terminal of the first transistor that forms the corresponding differential pair, and to output the other component of the differential signal to a control terminal of the second transistor that forms the corresponding differential pair.
By providing the output stage of the driver having a CML (Current Mode Logic) type configuration, by providing a differential pair for each path, and by combining the currents that flow through the respective differential pairs, such an arrangement is capable of appropriately combining the output signals of the multiple timing adjustment circuits. Such a configuration has an advantage of very high compatibility with the CMOS process.
Also, the constant current circuit may comprise a single constant current source that is shared by the multiple differential pairs.
Also, the constant current circuit may comprise multiple constant current sources, provided to the multiple respective differential pairs, which are each configured to supply a predetermined tail current to the corresponding differential pair.
Also, the combining output circuit may be configured to output, to the transmission line, a signal that is output from the second terminal of the second resistor. That is to say, such an arrangement may have a single-ended output configuration.
Also, the combining output circuit may be configured to output, to a differential transmission line, a signal that is output from the second terminal of the second resistor and a signal that is output from the second terminal of the first resistor. That is to say, such an arrangement may have a differential output configuration.
Also, the combining output circuit may comprise: multiple buffer circuits, provided to the multiple respective paths, which are each configured to receive an output signal of the corresponding timing adjustment circuit; multiple combining resistors, provided to the multiple respective paths, which are each arranged such that an output signal of the corresponding buffer circuit is received via a first terminal of the corresponding combining resistor, and such that their second terminals are connected together so as to form a common second terminal; and an output buffer configured to receive a signal output via the common second terminal obtained by connecting together the second terminals of the multiple combining resistors, and to output the signal thus received to the transmission line.
With such an embodiment, the signals are combined using resistors. Thus, such an arrangement provides high compatibility with the CMOS process.
Also, the timing adjustment circuit may comprise a delay circuit configured to delay an input signal.
Such an arrangement allows the driver circuit to output a signal having a positive edge waveform and a negative edge waveform that are symmetrical.
Also, the timing adjustment circuit may comprise a pulse width adjustment circuit configured to apply separate respective delays to a positive edge and a negative edge of the input signal, thereby adjusting the pulse width.
Such an arrangement is capable of independently controlling the positive edge waveform and the negative edge waveform of the output signal of the driver circuit.
Also, the timing adjustment circuits may each comprise: a delay circuit configured to delay an input signal; and a pulse width adjustment circuit configured to apply separate delays to a positive edge and a negative edge of the input signal, thereby adjusting the pulse width of the signal. With such an arrangement, the delay circuit and the pulse width adjustment circuit of each timing adjustment circuit may be arranged in series on the corresponding path.
Such an arrangement provides an improved degree of freedom in controlling the positive edge waveform and the negative edge waveform of the output signal of the driver circuit.
Another embodiment of the present invention relates to a test apparatus configured to test a device under test. The test apparatus comprises a driver circuit according to any one of the aforementioned embodiments, configured to output a signal that corresponds to a test pattern to the device under test via a transmission line.
Such an embodiment is capable of changing the waveform of a test signal to be supplied to a device under test. Thus, such an arrangement allows various kinds of tests to be performed.
It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments.
Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.
Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:
The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.
In the present specification, the state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B. Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.
The driver circuit 100 mainly includes a branch circuit 10, multiple timing adjustment circuits 20, and a combining output circuit 30.
The branch circuit 10 branches the input signal SIN to be transmitted into multiple paths 121 through 12n. Here, “n” represents an integer of 2 or more, and represents the number of paths.
The multiple timing adjustment circuits 201 through 20n are respectively provided to the multiple paths 121 through 12n. The i-th timing adjustment circuit 20i (1≦i≦n) applies a delay to at least one from among a positive edge and a negative edge of the corresponding input signal Sai that has been branched into the corresponding path 12i.
For example, the timing adjustment circuit 20 may include a delay circuit VD configured to delay its input signal. The delay circuit VD is preferably configured as a variable delay circuit which is capable of adjusting the amount of delay. The delay circuit applies the same delay to the overall waveform of the input signal. That is to say, such an arrangement applies the same delay to the positive edge and the negative edge of the input signal Sa that has been branched. As such a delay circuit, such an arrangement may employ a circuit described in the pamphlet International Publication WO 2006/025285, etc. Also, delay circuits having different configurations may be employed.
The combining output circuit 30 combines the output signals Sb1 through Sbn of the multiple timing adjustment circuits 201 through 20n, and outputs the signal SOUT that has been combined to the transmission line 3.
The above is the basic configuration of the driver circuit 100. Next, description will be made regarding the operation thereof.
As described above, with the driver circuit 100 shown in
Furthermore, the resolution of the waveform control is determined according to the number n of paths that are branched. In other words, the number of paths may preferably be determined according to the required resolution.
Similar processing is performed for the negative edge of the input signal SIN, thereby controlling the waveform of the negative edge of the output signal SOUT, i.e., the transition time Tf. Furthermore, in a case in which the timing adjustment circuits 20 are each configured as a delay circuit, such an arrangement can provide the output signal SOUT in which the waveforms of the positive edge and the negative edge are symmetrical.
When the input signal SIN and the output signal SOUT transit at high speed, the output stage of the driver circuit 100 preferably has a CML-type configuration. Description will be made regarding a specific example configuration of the combining output circuit 30 having such a CML-type configuration.
The combining output circuit 30a includes a voltage source 32, a constant current circuit 34a, multiple differential pairs 36, multiple differential conversion circuits 38, a first resistor R1, and a second resistor R2.
The voltage source 32 is configured to generate a predetermined voltage VH. The voltage VH thus generated is applied to each of the first terminals of the first resistor R1 and the second resistor R2. The multiple differential pairs 361 through 36n are respectively provided to the multiple paths 121 through 12n. The i-th differential pair 36, includes a first transistor Mi1 and a second transistor Mi2. The first terminal (e.g., drain) of the first transistor Mi1 is connected to the second terminal of the first resistor R1. The first terminal (drain) of the second transistor Mi2 is connected to the second terminal of the second resistor R2. The second terminal (source) of the second transistor Mi2 is connected to the second terminal (source) of the corresponding first transistor Mi1. The first transistor Mi1 and the second transistor M12, which belong to the same differential pair 36, are designed to have the same transistor size.
The constant current circuit 34a is configured to supply a tail current I to the multiple differential pairs 361 through 36n. In
The multiple differential conversion circuits 381 through 38n are respectively provided to the multiple paths 121 through 12n. The i-th differential conversion circuit 38, is configured to convert the output signal Sbi of the corresponding timing adjustment circuit 20i into a differential signal PATi and PATix, to output one component the differential signal, i.e., PATi, to the control terminal (gate) of the first transistor Mi1 of the corresponding differential pair 36i, and to output the other component of the differential signal, i.e., PATix, to the control terminal (gate) of the second transistor Mi2 of the corresponding differential pair 36i.
The combining output circuit 30a shown in
A modification may be made in which the combining output circuit 30a has a differential configuration. In this case, the combining output circuit 30a may output a pair composed of a signal output via the second terminal of the second resistor R2 and a signal output via the second terminal of the first resistor R1 as a differential output signal.
With the driver circuit 100a shown in
Furthermore, in a case in which the transistor sizes of the respective differential pairs 361 through 36n are weighted, such an arrangement is capable of changing the coefficients for when the signals Sb1 through Sbn are to be combined, according to the weighting factors. It should be noted that all the differential pairs 361 through 36i may have the same transistor size.
Such a configuration shown in
Moreover, the tail currents I1 through In may have the same magnitude. Alternatively, the magnitudes of the tail currents I1 through In may be weighted. By weighting the currents, such an arrangement is capable of changing the coefficients for when the multiple signals Sb1 through Sbn are combined.
Description will be made below regarding several modifications.
Description has been made regarding an arrangement in which each timing adjustment circuit 20 includes a variable delay circuit VD. However, the present invention is not restricted to such an arrangement.
With the driver circuit 100d shown in
Returning to
By configuring each timing adjustment circuit 20 as a combination of the variable delay circuit VD and the pulse width adjustment circuit PW, such an arrangement provides more flexible waveform control.
Furthermore, an arrangement may be made in which the timing adjustment circuits 20 assigned to certain paths are each configured as such a variable delay circuit VD, and the timing adjustment circuits 20 assigned to the other paths are each configured as such a pulse width adjustment circuit PW.
The multiple buffer circuits BF1 through BFn are respectively provided to the multiple paths 121 through 12n (not shown). The i-th buffer circuit BFi is configured to receive an output signal Sbi of the corresponding timing adjustment circuit 20i. The multiple buffer circuits BF1 through BFn may each have the same gain, or may have different respective gains. The gains of the buffer circuits BF determine the coefficients for the combination of the signals.
The multiple combining resistors Ro1 through Ron are respectively provided to the multiple paths 121 through 12n. The i-th combining resistor Roi receives, via its first terminal, an output signal of the corresponding buffer circuit BFi. The second terminals of the respective multiple combining resistors Ro1 through Ron are connected together so as to form a common second terminal. The output buffer BFo is configured to receive a signal SOUT′ output via the common second terminal thus obtained by connecting together the second terminals of the respective multiple combining resistors Ro1 through Ron, and to output the corresponding output signal SOUT to the transmission line 3. The multiple combining resistors Ro1 through Ron may each have the same resistance, or may have different respective resistances.
With the combining output circuit 30c shown in
(Sb1×g1−SOUT′)/Ro1+(Sb2×g2−SOUT′)/Ro2+ . . . =Σi−1:n{(Sbi×gi−SOUT′)/Roi}=0 (1)
Expression (1) is solved with respect to SOUT′, thereby obtaining the following Expression (2).
Σi=1:n(Sbi×gi/Roi)=Σi=1:n(SOUT′/Roi)
S
OUT′=Σi=1:n(Sbi×gi/Roi)/Σi=1:nRoi (2)
That is to say, according to the combining resistors Ro1 through Ron and the gains g1 through gn, such an arrangement is capable of adjusting the coefficients for when the signals Sbi through Sbn are combined.
Lastly, description will be made regarding an application of the driver circuit according to the first embodiment or the second embodiment.
The test apparatus 2 mainly includes a pattern generator PG, a timing generator TG, a waveform shaper FC, a driver DR, a timing comparator TC, and a logical comparator DC.
The pattern generator PG is configured to generate pattern data DP which determines a test pattern to be supplied to a DUT 1. For each predetermined period (which will be referred to as the “rate period TRATE” hereafter), the timing generator TG generates timing setting data TP for setting a positive edge timing and a negative edge timing of a signal VOUT to be supplied to the DUT 1 according to the pattern data DP.
The waveform shaper FC receives the pattern data DP and the timing setting data TP, and generate an output signal FP having a value that changes at a timing that corresponds to the pattern data DP and the timing setting data TP thus received. The driver DR is configured as such a driver circuit 100 according to the aforementioned embodiment, and is configured to output, to the DUT 1, a voltage Vout having a level that corresponds to the signal FP received from the waveform shaper FC.
The timing comparator TC is configured to receive a signal S2 output from the DUT 1, and to latch the value of the signal S2 at a predetermined timing. For each test cycle, the logical comparator DC digitally compares the output values of the timing comparator TC with respective corresponding expected values EXP, and generates a pass/fail signal PASS/FAIL which indicates whether or not each output value agrees or disagrees with the corresponding expected value EXP. The pass/fail signal is stored in fail memory FM.
The above is an example configuration of the test apparatus 2. By mounting the driver circuit 100 according to the embodiment on such a test apparatus 2, such an arrangement is capable of adjusting the waveform of a signal supplied to the DUT 1 as desired according to the kind of DUT 1 and the test item.
While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-279738 | Dec 2010 | JP | national |
