Patent Application
20130170307
1. Technical Field
The present disclosure relates to electronic devices and, more particularly, to an electronic device for testing endurance of a memory and a method adapted for the electronic device.
2. Description of Related Art
Memories such as hard disks need to pass an endurance test before being put on the market. The endurance test involves actions such as repeatedly writing data into the hard disks and then deleting the data from the hard disk to test the ability of the hard disk to withstand repeated programming and erasing cycles (P/E cycles).
However, in order to improve the endurance of the hard disk, the P/E cycles are implemented sometimes up to 10,000,000,000 times or even more, and such mass number of cycle times thus prolongs the testing time of the endurance test of the hard disk.
Therefore, what is needed is a means to solve the problem described above.
Many aspects of the present disclosure should be better understood with reference to the following drawings. The units in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
The interface 10 connects the memory 200 to the electronic device 100.
The storage unit 20 stores a variety of test packages for different storage capacities of memories 200 and at least one test option associated with each test package, and the test option defines a predetermined capacity of the associated memory 200 to be tested. Take a hard disk having 2 megabytes of storage capacity for an example, almost 250,000 blocks are included. Two test options are stored in the storage unit 20 associated with the test package of 2 megabytes, for example, a first test option corresponding to a selection of 0.5 megabytes of the memory 200, and a second test option corresponding to a selection of 1 megabyte of the memory 200.
The obtaining unit 30 obtains the storage capacity of the memory 200 connected to the electronic device 100 via the interface 10.
The control unit 40 determines the at least one associated test option of the test package corresponding to the obtained storage capacity. If the test package corresponding to the obtained storage capacity associates only one test option, then the control unit 40 selects a number of blocks according to the predetermined capacity of the test option, assigns corresponding logical addresses to the selected blocks, and then implements the P/E cycles to test the endurance of the selected blocks. If the test package corresponding to the obtained storage capacity associates more than one test option, the control unit 40 selects one of the test options, selects a number of blocks according to the predetermined capacity of the selected test option, assigns the corresponding logical addresses to the selected blocks, and then implements the P/E cycles to test the endurance of the selected blocks.
It is well known that the memory 200 is usually divided into a number of segments, and each segment includes a number of blocks serving as the smallest programming and erasing unit. In the embodiment, the control unit 40 selects the blocks to be tested equally from each segment so as to satisfy the reliability of the endurance of the whole memory 200, and the selected blocks from all segments are equivalent to the predetermined capacity of the test option. Furthermore, the selected blocks from each segment are continuous blocks, thus the control unit 40 can assign sequential logical addresses to the selected blocks to allow the time for the endurance test of the selected blocks to be reduced.
Since only a part of blocks of the memory 200 is tested, the time for the endurance test of the memory 200 is reduced. As mentioned above in the example, the time for the endurance test of the hard disk is 10 days if all of the 250,000 blocks are tested. But if only 625,000 blocks equivalent to 0.5 megabytes are selected to be tested, the time for the endurance test of the hard disk is nearly 2.5 days. Thus, the time for the endurance test of the hard disk is reduced. However, it is notable that although less time is needed with less blocks to be tested in the endurance test, the minimum tested blocks are limited so as to satisfy the reliability of the endurance of the whole memory 200.
In the embodiment, the electronic device 100 further includes a display unit 50 and an input unit 60. The display unit 50 displays the test options when the test package corresponding to the obtained storage capacity associates two or more test options. The input unit 60 is for a user to select one displayed test option. The control unit 40 further responds to the user input to obtain the corresponding test option selected by the user. In an alternative embodiment, each test option may be assigned with a priority level. In this case, the control unit 40 selects a test option with a highest priority level.
In the embodiment, the electronic device 100 further includes a calculating unit 70, and the calculating unit 70 is configured to calculate the time for the endurance test of the selected blocks.
In step S21, through the interface 10, the memory 200 is connected to the electronic device 100.
In step S22, the obtaining unit 30 obtains the storage capacity of the memory 200 connected to the electronic device 100 via the interface 10.
In step S23, the control unit 40 determines the at least one associated test option of the test package corresponding to the obtained storage capacity stored in the storage unit 20, and the test option defines a predetermined capacity of the associated memory 200 to be tested.
In step S24, the control unit 40 determines whether the test package corresponding to the obtained storage capacity associates only one test option. If yes, the procedure goes to step S25; otherwise, the procedure goes back to step S26.
In step S25, the control unit 40 selects a number of blocks according to the predetermined capacity of the test option, and assigns the corresponding logical addresses to the selected blocks.
In step S26, the control unit 40 responds to the user input through the input unit 60 and obtains one test option selected by the user, selects a number of blocks according to the predetermined capacity of the selected test option, and assigns the corresponding logical addresses to the selected blocks.
In step S27, the control unit 40 tests the endurance of the selected blocks, and the calculating unit 70 calculates the time for the endurance test of the selected blocks.
Although the present disclosure has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present disclosure. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201110451947.0 | Dec 2011 | CN | national |
