Patent Application
20160293512
The present disclosure relates to the field of integrated circuit devices, and, more particularly, to packaging of integrated circuit devices and related methods.
In electronic devices with integrated circuits (ICs), the ICs are typically mounted onto circuit boards. In order to electrically couple connections between the circuit board and the IC, the IC is typically “packaged.” The IC packaging usually provides a small encasement for physically protecting the IC and provides contact pads for coupling to the circuit board. In some applications, the packaged IC may be coupled to the circuit board via solder bumps.
Referring to
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Generally speaking, an electronic device may include a substrate, an active IC die above the substrate, and a dummy IC die above the active IC die. The electronic device may comprise a first adhesive layer between the active IC die and the dummy IC die, and a heat sink layer above the dummy IC die and extending laterally outwardly therefrom to define a gap between the substrate and opposing portions of the heat sink layer.
Additionally, the electronic device may further comprise an underfill layer between the active IC die and the substrate. The heat sink layer may comprise a raised hat portion above the dummy IC die. For example, the gap has an L shape. The substrate may have a rectangular shape larger than the active IC die, and the active IC die may be positioned at a corner of the substrate.
In some embodiments, the electronic device may further comprise a thermal interface layer between the heat sink layer and the dummy IC die. The electronic device may further comprise at least one component in the gap and carried by the substrate. The active IC die and the dummy IC die may have a same shape. For example, the active IC die and dummy IC die may each comprise silicon. The electronic device may also comprise a second adhesive layer between the substrate and the heat sink layer.
Another aspect is directed to a method for making an electronic device. The method may include mounting an active IC die above a substrate, and mounting a dummy IC die above the active IC die using a first adhesive layer between the active IC die and the dummy IC die. The method may include mounting a heat sink layer above the dummy IC die and extending laterally outwardly therefrom to define a gap between the substrate and opposing portions of the heat sink layer.
The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments of the invention are shown. This present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like numbers refer to like elements throughout.
Referring now to
The electronic device 10 illustratively includes an active IC die 17 above the substrate 14, a dummy IC die 19 above the active IC die (shown with dashed lines in
Also, the active IC die 17 may comprise circuitry, and a plurality of electrically conductive bond pads. The dummy IC die 19 may also comprise non-functional circuitry, and a plurality of electrically conductive bond pads, or in some embodiments, the dummy IC die 19 may comprise a bare semiconductor substrate. Additionally, the electronic device 10 illustratively includes an underfill layer 15 between the active IC die 17 and the substrate 14.
The first adhesive layer 18 may include a low stress adhesive material, i.e. a stress absorbing material having a low modulus of elasticity and superior elongation properties. The active IC die 17 and the dummy IC die 19 may have a same shape, in the illustrated embodiment, a square shape.
The electronic device 10 illustratively includes a heat sink layer 11 above the dummy IC die 19 and extending laterally outwardly therefrom to define a gap 21a-21b between the substrate 14 and opposing portions of the heat sink layer. The heat sink layer 11 may comprise copper, for example, or any effective thermally conductive material. In the illustrated embodiment, the electronic device 10 illustratively includes a thermal interface layer 20 between the heat sink layer 11 and the dummy IC die 19, and an electronic component (e.g. a capacitor or a resistor) 23 in the gap 21a-21b and carried by the substrate 14.
As perhaps best seen in
Also, the substrate 14 has a rectangular shape larger than the active IC die 17, and the active IC die is be positioned at a corner of the substrate. The active IC and dummy IC dies 17, 19 illustratively have square shapes aligned with the corner of the substrate 14. The gap 21a-21b extends along the edges of the active IC and dummy IC dies 17, 19 opposite the outer edges aligned with the corner of the substrate 14.
In some embodiments, the electronic device 10 may include a housing or encapsulation material surrounding the substrate 14. The housing may comprise a plastic or metallic container, for example.
Another aspect is directed to a method for making an electronic device 10. The method may include mounting an active IC die 17 above a substrate 14, and mounting a dummy IC die 19 above the active IC die using a first adhesive layer 18 between the active IC die and the dummy IC die. The method may include positioning a heat sink layer 11 above the dummy IC die 19 and extending laterally outwardly therefrom to define a gap 21a-21b between the substrate 14 and opposing portions of the heat sink layer.
In the prior art devices of
On the other hand, the electronic device 200 (
Advantageously, the electronic device 10 may provide a cost effective approach that provides similar performance to the dual cavity flat approach. Also, the electronic device 10 allows used of a thinner active IC die 17 and the standard passive devices/electronic components 23. Indeed, a simulation shows that the electronic device's 10 performance is comparable to that of the dual cavity lid approach in terms of the warping and stress (See Table 1).
Also, since the electronic device 10 may include a thinned down active IC die 17, the potential for warping and reduced BLR is mitigated. This is because of the CTE mismatch reduction due to reduced thickness. Nevertheless, in the prior art approaches, the addition of passive electronic components reduces the ability to thin the IC. The electronic device 10 disclosed herein provides an approach that allows for both the thinned active IC die 17 and passive electronic components 23. Also, by leveraging the dummy IC die 19 and the low stress first adhesive layer 18, the level of CTE mismatch in the electronic device 10 is reduced, particularly adjacent the active IC die 17.
Many modifications and other embodiments of the present disclosure will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the present disclosure is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.
