The present disclosure generally relates to an electronic device, and more particularly to an electronic device including an electromagnetic interference (EMI) shielding structure.
To meet characteristic impedance requirements and prevent interference to an electronic device that transmits a signal with a relatively high frequency (e.g., radio frequency (RF) signal) or an input/output signal, an electromagnetic interference (EMI) shielding layer is utilized. However, in some situations, the arrangement of an EMI shielding layer presents manufacturing challenges. For example, when a metal lid is used to function as an EMI shielding layer, it is difficult to fill a molding material within said metal lid, which forms undesired voids and thus degrades the performance of an electronic device. Therefore, a new electronic device is required.
In some embodiments, an electronic device includes a substrate, an electronic component, a circuit structure, and a shielding layer. The electronic component is disposed under the substrate. The circuit structure is disposed under the substrate. The shielding layer is disposed under the substrate and covers the electronic component and connected to the circuit structure. The circuit structure and the shielding layer are collectively configured to block the electronic component from electromagnetic interference.
In some embodiments, an electronic device includes an electronic component, a circuit structure, an encapsulant, and an EMI shielding layer. The circuit structure is adjacent to the electronic component. The circuit structure has a bottom side configured to provide the electronic device with an external connection. The encapsulant encapsulates the electronic component. The EMI shielding layer is disposed on a lower surface of the encapsulant and at least partially disposed on the bottom side of the circuit structure.
In some embodiments, an electronic device includes an electronic component, a circuit structure, an encapsulant, and an EMI shielding layer. The circuit structure is adjacent to the electronic component and includes a conductive pad. The encapsulant encapsulates the electronic component. The encapsulant and the circuit structure collectively define a step. The EMI shielding layer covers the electronic component. A portion of the EMI shielding layer is disposed on the step and connected to the conductive pad.
Aspects of some embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In some embodiments, the substrate 10 (or carrier) may be or include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. In this disclosure, the substrate 10 may also be referred to as a substrate. The substrate 10 may have a surface 10s1 (or a lower surface), a surface 10s2 (or an upper surface) opposite to the surface 10s1, and a surface 10s3 (or a lateral surface) extending between the surface 10s1 and the surface 10s2. In some embodiments, the substrate 10 may include a conductive pad(s), trace(s), via(s), layer(s), or other interconnection(s). For example, the substrate 10 may include one or more transmission lines (e.g., communications cables) and one or more grounding lines and/or grounding planes. For example, the substrate 10 may include one or more conductive pads (not shown in the figures) in proximity to, adjacent to, or embedded in and exposed by the surface 10s1 and/or the surface 10s2 of the substrate 10. The substrate 10 may include a solder resist (not shown in the figures) on the surface 10s1 and/or the surface 10s2 to fully expose or expose at least a portion of the conductive pads for electrical connections. The substrate 10 may include a ground trace 10g. The ground trace 10g may electrically connected to ground.
The electronic components 22 and 24 may be disposed on or below the surface 10s1 of the substrate 10. Each of the electronic components 22 and 24 may be electrically connected to the substrate 10. Each of the electronic components 22 and 24 may include a logic die (e.g., an application-specific IC (ASIC), application processor (AP), system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies) or other active components. In some embodiments, each of the electronic components 22 and 24 may include a passive device, such as an inductor, a resistor, and/or a capacitor.
The electronic component 30 may be disposed on or over the surface 10s2 of the substrate 10. The electronic component 30 may be electrically connected to the substrate 10. The electronic component 30 may include a logic die (e.g., an application-specific IC, application processor, system-on-a-chip, central processing unit, graphics processing unit, microcontroller, etc.), a memory die (e.g., dynamic random access memory die, static random access memory die, etc.), a power management die (e.g., power management integrated circuit die), a radio frequency die, a sensor die, a micro-electro-mechanical-system die, a signal processing die (e.g., digital signal processing die), a front-end die (e.g., analog front-end dies) or other active components.
The electronic component 32 may be disposed on or over the surface 10s2 of the substrate 10. The electronic component 32 may be electrically connected to the substrate 10. The electronic component 32 may include a passive device, such as a capacitor, an inductor, or other suitable passive devices.
In some embodiments, the circuit structure 40 (or interposer) may be disposed on or below the surface 10s1 of the substrate 10. In some embodiments, the circuit structure 40 may disposed at a peripheral region of the substrate 10. In some embodiments, the circuit structure 40 may be configured to receive and/or transmit a non-ground signal (e.g., an input/out (I/O) signal). In some embodiments, the circuit structure 40 may be configured to receive and/or transmit a ground signal to reduce electromagnetic interference (EMI) between components and/or traces. The circuit structure 40 may have a surface 40s1 (or a lower surface), a surface 40s2 (or an upper surface) opposite to the surface 40s1, a surface 40s3 (or an inner lateral surface) facing the electronic component 22 (or electronic component 24), and a surface 40s4 (or an outer lateral surface) opposite to the surface 40s3. In some embodiments, the circuit structure 40 may include a substrate 41, conductive elements 42a (or element), conductive elements 42b (or element), as well as dielectric layers 43a and 43b.
The substrate 41 (or a core substrate) may encapsulate the conductive elements 42a and conductive elements 42b. The substrate 41 may include or be composed of multiple dielectric layers. The substrate 41 may include, for example, polyimide (PI), polyimide-isoindoloquinazolinedione (PIQ), polybenzoxazole (PBO), benzocyclobutene (BCB), or other suitable materials.
In some embodiments, the conductive element 42a may be disposed within the substrate 41 of the circuit structure 40. The conductive element 42a may include a conductive via that at least partially penetrates the substrate 41. In some embodiments, the conductive element 42a may be disposed between the conductive element 42b and the electronic component 22 (or electronic component 24). The conductive elements 42a may be disposed on opposite two sides of the electronic component 22 (or electronic component 24) or surround the electronic component 22 (or electronic component 24). In some embodiments, the conductive element 42a is closer to the surface 40s3 than the conductive element 42b is. In some embodiments, the conductive element 42a may be electrically connected to ground or configured to transmit a ground signal, leading to a decrease of EMI interference between the conductive element 42b and the electronic component 22 (or electronic component 24). The electronic components 22 and 24 may be sensitive to the EMI from external devices (e.g., RF devices). The conductive element 42a may block (or shield) the electronic components 22 and 24 from external EMI.
The conductive element 42b may be disposed within the substrate 41 of the circuit structure 40. The conductive element 42b may include a conductive via that at least partially penetrates the substrate 41. In some embodiments, the conductive element 42b may be spaced apart from the electronic component 22 (or electronic component 24) by the conductive element 42a. In some embodiments, the conductive element 42 may be configured to transmit a non-ground signal, such as an I/O signal. The conductive element 42b may function as a part of a signal delivery structure. In some embodiments, each of the conductive element 42a and conductive element 42b may include a seed layer (not shown) and a conductive material (not shown) formed on the seed layer. The seed layer may include titanium, titanium nitride, or other suitable materials. The conductive material may include copper, silver, aluminum, or other suitable materials.
Referring back to
The electronic device 1a may include electrical connectors 45 (or electrical contacts). The electrical connector 45 may be disposed on or below the surface 40s1 of the circuit structure 40. The electrical connector 45 may be configured to electrically connect the electronic device 1a to an external device (not shown). The electrical connector may include a soldering material (or soldering element), such as alloys of gold and tin solder or alloys of silver and tin solder.
The electronic device 1a may include electrical connectors 46 (or electrical contacts). The electrical connector 46 may be disposed on or over the surface 40s2 of the circuit structure 40. The electrical connector 46 may be configured to electrically connect the circuit structure 40 and the substrate 10. The electrical connector 46 may include a solder material (or solder element), such as alloys of gold and tin solder or alloys of silver and tin solder. In some embodiments, the quantity of the electrical connectors 46 may be different from that of the electrical connectors 45. In some embodiments, the quantity of the electrical connectors 46 may be different from that of the electrical connectors 45 in a cross-sectional view. In some embodiments, the quantity of the electrical connectors 46 may be greater than that of the electrical connectors 45. In some embodiments, the quantity of the electrical connectors 46 may be greater than that of the electrical connectors 45 in a cross-sectional view.
In some embodiments, the encapsulant 52 may be disposed on or below the surface 10s1 of the substrate 10. In some embodiments, the encapsulant 52 may encapsulate the electronic component 22 and the electronic component 24. In some embodiments, the encapsulant 52 may encapsulate the electrical connectors 46. The encapsulant 52 may cover the surface 40s1 of the circuit structure 40. The encapsulant 52 may cover the surface 40s2 of the circuit structure 40. In some embodiments, the encapsulant 52 may be in contact with the surface 40s3 of the circuit structure 40. In some embodiments, the encapsulant 52 may be spaced apart from the surface 40s4 of the circuit structure 40. The encapsulant 52 may include a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable material. Suitable fillers may also be included, such as powdered SiO2. The encapsulant 52 may have a surface 52s1 (or a lower surface) and a surface 52s2 (or a lateral surface). In some embodiments, the surface 52s2 of the encapsulant 52 may be substantially aligned with the surface 10s3 of the substrate 10. In some embodiments, the surface 52s2 of the encapsulant 52 may be substantially aligned with the surface 40s4 of the circuit structure 40. The electrical connector 45 may be exposed by the surface 52s1 of the encapsulant 52.
In some embodiments, the encapsulant 54 may be disposed on or over the surface 10s2 of the substrate 10. In some embodiments, the encapsulant 54 may encapsulate the electronic component 30. The encapsulant 54 may be spaced apart from the encapsulant 52 by the substrate 10. The encapsulant 54 may include a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable material. Suitable fillers may also be included, such as powdered SiO2. The encapsulant 54 may have a surface 54s1 (or an upper surface) and a surface 54s2 (or a lateral surface). In some embodiments, the surface 54s2 of the encapsulant 54 may be substantially aligned with the surface 10s3 of the substrate 10.
In some embodiments, the EMI shielding layer 60 (or a grounding layer) may be disposed on or below the surface 52s1 of the encapsulant 52. In some embodiments, the EMI shielding layer 60 may be electrically connected to ground. In some embodiments, the EMI shielding layer 60 may be electrically connected to the ground trace 10g. In some embodiments, the EMI shielding layer 60 may be configured to receive and/or transmit a ground signal. In some embodiments, the EMI shielding layer 60 may cover or vertically overlap the electronic component 22 and the electronic component 24 to prevent EMI from a component below the electronic device 1a. In some embodiments, the EMI shielding layer 60 may be electrically connected to the conductive element 42a of the circuit structure 40 through the terminal 44a. In some embodiments, the EMI shielding layer 60 may be electrically isolated from the conductive element 42b of the circuit structure 40.
In some embodiments, the encapsulant 52 and the circuit structure 40 may collectively define a step 40t. The lower surface of the substrate 41 and the surfaces 52s1 and 52s3 of the encapsulant 52 define the step 40t. The step 40t may expose a portion of the terminal 44a. The EMI shielding layer 60 may be disposed on the step 40t.
In some embodiments, the EMI shielding layer 60 may include portions 61, 62, and 63. The portion 61 may be disposed on or below the surface 52s1 of the encapsulant 52. In some embodiments, the portion 61 may be in contact with the encapsulant 52.
In some embodiments, the portion 62 (or a connecting portion) may be disposed on the surface 52s3 of the encapsulant 52. The portion 62 may connect the portions 61 and 63. In some embodiments, the portion 62 may be disposed within the recess 52r1 of the encapsulant 52. In some embodiments, the portion 62 may be in contact with the encapsulant 52.
In some embodiments, the portion 63 may be disposed on or below the terminal 44a. In some embodiments, the portion 63 may be disposed within the recess 52r1. In some embodiments, the portion 63 may be spaced apart from the encapsulant 52 by the dielectric layer 43a.
In some embodiments, the surface 52s4 may be exposed by the EMI shielding layer 60. That is, a portion of the lateral surface that defines the recess 52r1 is exposed by the EMI shielding layer 60.
In some embodiments, the EMI shielding layer 60 may have an uneven thickness. The portion 61 may have a thickness T1, which may be defined as a minimum distance between an outer surface of the portion 61 of the EMI shielding layer 60 and the encapsulant 52. The portion 62 may have a thickness T2, which may be defined as a minimum distance between an outer surface of the portion 62 of the EMI shielding layer 60 and the encapsulant 52. The portion 63 may have a thickness T3, which may be defined as a minimum distance between an outer surface of the portion 63 of the EMI shielding layer 60 and the terminal 44a. In some embodiments, the thickness T1 may be greater than the thickness T2. In some embodiments, the thickness T1 may be greater than the thickness T3. In some embodiments, the thickness T3 may be equal to or greater than the thickness T2. In some embodiments, the ratio of the thickness T1 to the thickness T2 may range from about 1.1 to about 1.5, such as 1.1, 1.2, 1.3, 1.4, or 1.5.
In some embodiments, the portion 61 may be regarded as a substantial horizontal part ES1 of an EMI shielding structure ES. In some embodiments, the portion 63, the terminal 44a, and the conductive element 42a may collectively be regarded as a substantial vertical part ES2 of the EMI shielding structure ES. The substantial horizontal part ES1 may be substantially orthogonal to the substantial vertical part ES2. In some embodiments, the substantial horizontal part ES1 of the EMI shielding structure ES may be in contact with the encapsulant 52. In some embodiments, the substantial horizontal part ES2 of the EMI shielding structure ES may be spaced apart from the encapsulant 52. The substantial horizontal part ES2 may be connected to the substantial horizontal part ES1 by the portion 62 of the EMI shielding layer 60. The portion 62 may be slanted with respect to the substantial horizontal part ES1. The portion 62 may be slanted with respect to the substantial vertical part ES2.
In some embodiments, a gap 52g may be defined between the lower surface 43as1 of the dielectric layer 43a and the surface 52s1 of the encapsulant 52. In some embodiments, the lower surface 43as1 of the dielectric layer 43a may have an elevation lower than the elevation of the lower surface (not annotated) of the portion 63 of the EMI shielding layer 60. In some embodiments, the surface 60s1 (or lower surface) of the EMI shielding layer 60 may have an elevation lower than that of the bottom of the electrical connector 45.
Referring back to
As shown in
In a comparative example, a metal lid is utilized to function as an EMI shielding layer. The metal lid may include a top plate with an opening and four sidewalls connected to the top plate. In some conditions, after the four sidewalls of the metal lid are attached to a carrier, a molding material is filled into the inner space of the metal lid through the opening of the top plate. Since the size of the opening should be relatively small to ensure shielding performance, it is difficult to fill the molding material within the metal lid through such small opening, leading to voids formed within the molding material. As a result, the reliability of an electronic device is degraded. In some embodiments of the present disclosure, the metal lid is replaced with the conductive elements 42a of the circuit structure 40 and the EMI shielding layer 60. The EMI shielding layer 60 is formed after the formation of the encapsulant 52. Further, the conductive elements 42a and the EMI shielding layer 60 are not formed in one piece. Therefore, the aforesaid issues of the comparative example are avoided, leading to an improvement of the reliability of the electronic device 1a.
In some embodiments, the EMI shielding layer 60 may extend between the recesses 52r1 and 52r2. The EMI shielding layer 60 may include portions 64 and 65. The portion 64 may be disposed on the surface 52s4. The portion 64 may extend between the portions 63 and 65. The portion 64 may be spaced apart from the portion 62 in a cross-sectional view. The portion 65 may be disposed on a part of the surface 52s5 that is located between the recesses 52r1 and 52r2. The portion 65 may be spaced apart from the portion 61 in a cross-sectional view. In some embodiments, the thickness (not annotated) of the portion 65 may be substantially the same as that of the portion 61. In some embodiments, the thickness of the portion 64 (not annotated) may be substantially the same as that of the portion 62. In this embodiment, the EMI shielding layer 60 further includes the portion 65. The portion 65 may completely cover an exposed portion of the terminal 44a, which thereby enhances the EMI shielding performance. The formation of the portion 65 will be described in
In some embodiments, the electronic device 1c may include a compartment structure 72. In some embodiments, the compartment structure 72 may be disposed between the electronic components 22 and 24. In some embodiments, the compartment structure 72 may penetrate the encapsulant 52. In some embodiments, the compartment structure 72 may extend between the surface 10s1 of the substrate 10 and the EMI shielding layer 60. In some embodiments, the compartment structure 72 may be electrically connected to the substrate 10. In some embodiments, the compartment structure 72 may be electrically connected to the ground trace 10g. In some embodiments, the compartment structure 72 may be electrically connected to the EMI shielding layer 60. In some embodiments, the compartment structure 72 may be configured to reduce the EMI between the electronic components 22 and 24. In some embodiments, the compartment structure 72 may include a seed layer (e.g., titanium, titanium nitride, or other suitable materials) and a conductive material (e.g., copper or other suitable materials).
In some embodiments, the electronic device 1d may include an electronic component 26. The electronic component 26 may be disposed on or below the surface 10s1 of the substrate 10. The electronic component 26 may be electrically connected to the substrate 10. The electronic component 26 may include a logic die (e.g., an application-specific IC, application processor, system-on-a-chip, central processing unit, graphics processing unit, microcontroller, etc.), a memory die (e.g., dynamic random access memory die, static random access memory die, etc.), a power management die (e.g., power management integrated circuit die), a radio frequency die, a sensor die, a micro-electro-mechanical-system die, a signal processing die (e.g., digital signal processing die), a front-end die (e.g., analog front-end dies) or other active components. In some embodiments, the lower surface (not annotated) of the electronic component 26 may be exposed by the surface 52s1 of the encapsulant 52. In some embodiments, the electronic component 26 may be in contact with the EMI shielding layer 60′. In some embodiments, the adhesion metal layer, intervening metal layer(s), and protection metal layer of the EMI shielding layer 60′ may include or be composed titanium, copper, and titanium, respectively.
In some embodiments, the conductive elements 42a may be replaced with a conductive element 47. In some embodiments, the conductive element 47 may be embedded within the substrate 41 of the circuit structure 40. The conductive element 47 may be configured to receive or transmit a ground signal. In some embodiments, the conductive element 47 may include a ring-shaped profile. In some embodiments, the surface 40s3 may be completely spaced apart from the surface 40s4 by the conductive element 47 in a top view. In some embodiments, the conductive element 47 may define a completely closed ring, leading to an improvement of an EMI shielding performance.
In some embodiments, the circuit structure 40 may include conductive elements 42a1 and conductive elements 42a2. In some embodiments, each of the conductive elements 42a1 and conductive elements 42a2 may be configured to receive or transmit a ground signal. The conductive elements 42a1 may surround the conductive elements 42a2. In some embodiments, the conductive elements 42a1 and conductive elements 42a2 may have a staggered arrangement. For example, the conductive elements 42a1 may be misaligned with the conductive elements 42a2 along a horizontal direction and a longitudinal direction. In some embodiments, the conductive element 42a2 is closer to the surface 40s3 than the conductive element 42a1 is. By such arrangements, EMI shielding performance is enhanced.
In some embodiments, the electronic device 1g may include electronic components 27 and 28. The electronic components 27 and 28 may be disposed below a circuit structure (e.g., the substrate 10 as shown in
In some embodiments, the EMI shielding layer 60 may have a cross-shaped profile. In some embodiments, a portion of the conductive elements 42b (e.g., conductive element 42b1) may be aligned with the conductive elements 42a along both a first direction (e.g., a horizontal direction) and a second direction (e.g., a longitudinal direction).
In some embodiments, no conductive element 42a is disposed at some of the sides of the surface 40s3. For example, the surface 40s3-1 only faces the conductive elements 42b. No conductive element 42a is disposed between the conductive element 42b and the surface 40s3-1. In some embodiments, some of the sides of the surface 40s3 may face both the conductive elements 42a and conductive elements 42b. For example, the surface 40s3-2 may face both the conductive elements 42a and conductive elements 42b. In some embodiments, the EMI shielding layer 60 may not encroach the surface 40s3-1 of the circuit structure 40 in a bottom or a top view.
In some conditions, the conductive elements 42b at the left side of the surface 40s3-1 of the circuit structure 40 may be configured to transmit a signal with a smaller frequency. Such smaller frequency may have a relatively small interference with the signals from the electronic components 27 and 28. In this case, the conductive elements 42b at the left side of the surface 40s3-1 of the circuit structure 40 may be free of being connected to the ground trace (e.g., 10g). As a result, the conductive elements 42b at the left side of the surface 40s3-1 may be connected to electrical connectors (e.g., soldering elements), which allows the circuit structures 40 to have more input/output terminals.
In some embodiments, a portion of the conductive elements 42a may be replaced by the conductive element 42b. For example, the conductive elements 42a at the left side of
The electronic device 1j shows a scanning electron microscope (SEM) image. In some embodiments, the electronic device 1j may include a circuit structure 81, a circuit structure 82, an encapsulant 83, an encapsulant 84, an EMI shielding layer 85, an EMI shielding layer 86, electrical connectors 87 and electrical connectors 88.
The circuit structure 81 may be or include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The circuit structure 81 may have a surface 81s1 (or a lower surface) and a surface 81s2 (or an upper surface) opposite to the surface 81s1. The circuit structure 81 may include one or more transmission lines (e.g., communications cables) and one or more grounding lines and/or grounding planes. For example, the circuit structure 81 may include one or more conductive pads in proximity to, adjacent to, or embedded in and exposed by the surface 81s1 and/or the surface 81s2 of the circuit structure 81.
In some embodiments, the circuit structure 82 may be disposed on or below the surface 81s1 of the circuit structure 81. In some embodiments, the circuit structure 82 may disposed at a peripheral region of the circuit structure 81. In some embodiments, the circuit structure 82 may include a substrate 82d1, a dielectric layer 82d2, a conductive element 82v1, a conductive element 82v2, a terminal 82p1, and a terminal 82p2.
The substrate 82d1 may encapsulate the conductive element 82v1 and conductive element 82v2. The substrate 82d1 may include or be composed of multiple dielectric layers. The substrate 82d1 may include, for example, polyimide, polyimide-isoindoloquinazolinedione, polybenzoxazole, benzocyclobutene, or other suitable materials.
In some embodiments, the conductive element 82v1 may be disposed within the substrate 82d1 of the circuit structure 82. In some embodiments, the conductive element 82v1 may be electrically connected to ground or be configured to transmit a ground signal, leading to a decrease of EMI interference between the conductive element 82v2 and an electronic component (not shown).
The conductive element 82v2 may be disposed within the substrate 82d1 of the circuit structure 82. In some embodiments, the conductive element 82v2 may be configured to transmit a non-ground signal, such as an I/O signal.
In some embodiments, each of the conductive element 82v1 and the conductive element 82v2 may include a seed layer (not annotated) and a conductive material (not annotated). The seed layer may include titanium, titanium nitride, or other suitable materials. The conductive material may include copper, silver, aluminum, or other suitable materials. In some embodiments, the conductive element 82v1 and/or 82v2 may have an X-shaped profile. For example, the conductive element 82v1 and/or 82v2 have an upper portion and a lower portion tapered toward each other. The upper portion and the lower portion may be formed by individual laser drilling steps.
The dielectric layer 82d2 may cover the substrate 82d1. The dielectric layer 82d2 may include a solder resist, which defines a space exposing terminal 82p1 and terminal 82p2.
The terminal 82p1 may be electrically connected to the conductive element 82v1. The terminal 82p2 may be electrically connected to the conductive element 82v2.
In some embodiments, the encapsulant 83 may be disposed on or below the surface 81s1 of the circuit structure 81. The encapsulant 83 may cover the upper surface and lower surface (not annotated) of the circuit structure 82. The encapsulant 83 may include a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable material. Suitable fillers may also be included, such as powdered SiO2. The encapsulant 83 may have a surface 83s1 (or a lower surface). In some embodiments, the electrical connector 88 may be exposed by the surface 83s1 of the encapsulant 83.
In some embodiments, the encapsulant 84 may be disposed on or over the surface 81s2 of the circuit structure 81. The encapsulant 84 may be spaced apart from the encapsulant 83 by the circuit structure 81. The encapsulant 84 may include a novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable material. Suitable fillers may also be included, such as powdered SiO2.
In some embodiments, the EMI shielding layer 85 may cover the encapsulant 84. The EMI shielding layer 85 may cover the lateral surface (not annotated) of the circuit structure 81. The EMI shielding layer 85 may cover the lateral surface (not annotated) of the circuit structure 82. The EMI shielding layer 85 may cover the lateral surface (not annotated) of the encapsulant 83. The EMI shielding layer 85 may cover the lateral surface (not annotated) of the encapsulant 84.
In some embodiments, the EMI shielding layer 86 may be disposed on or below the surface 81s1 of the circuit structure 81. In some embodiments, the EMI shielding layer 86 may be electrically connected to ground. In some embodiments, the EMI shielding layer 86 may be electrically connected to the conductive element 82v1 of the circuit structure 82 through the terminal 82p1. In some embodiments, the EMI shielding layer 86 may be electrically isolated from the conductive element 82v2 of the circuit structure 82.
The electrical connector 87 may be electrically connected between the conductive element 82v1 (or conductive element 82v2) and the circuit structure 81. The electrical connector 88 may be electrically connected to the conductive element 82v2. Each of the electrical connector 87 and electrical connector 88 may include a solder material, such as alloys of gold and tin solder or alloys of silver and tin solder. In some embodiments, the terminal 82p1 may be free of solder-joints. In some embodiments, a conductive structure including the conductive element 82v1 and terminal 82p1 is free of solder-joints at a side far from the circuit structure 81.
Referring to
In some embodiments, the EMI shielding layer 86 may include portions 86p1, 86p2, 86p3, 86p4, and 86p5. The portion 86p1 may be disposed on or below the surface 83s1 of the encapsulant 83. In some embodiments, the portion 86p1 may be in contact with the encapsulant 83. In some embodiments, the portion 86p2 may be disposed on the surface 83s2 of the encapsulant 83. In some embodiments, the portion 86p2 may be disposed within the recess 83r of the encapsulant 83. In some embodiments, the portion 86p3 may be in contact with the terminal 82p1. In some embodiments, the portion 86p3 may be disposed within the recess 83r. In some embodiments, the portion 86p3 may be spaced apart from the encapsulant 83. The portion 86p2 may connect the portions 86p1 and 86p3. The portion 86p4 may be disposed on the surface 83s3 of the encapsulant 83. The portion 86p5 may be disposed on or below the surface 83s1 of the encapsulant 83. The portion 86p4 may connect the portions 86p3 and 86p5. In some embodiments, the thickness of the portion 86p1 may be greater than that of the portion 86p2. In some embodiments, the thickness of the portion 86p1 may be greater than that of the portion 86p3.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
In some embodiments, an electronic device includes an electronic component, an interposer, and an electromagnetic interference (EMI) shielding layer. The interposer is adjacent to the electronic component and includes a first conductive element and a second conductive element. The EMI shielding layer covers the electronic component and is electrically connected to the second conductive element.
In some embodiments, the second conductive element is disposed on opposite two sides of the electronic component.
In some embodiments, the second conductive element surrounds the electronic component
In some embodiments, the first conductive element includes a first group of conductive vias, the second conductive element includes a second group of conductive vias, and a density of the first group of conductive vias is less than a density of the second group of conductive vias.
In some embodiments, a plurality of electrical contacts are electrically connected to the first group of conductive vias and electrically isolated from the second group of conductive vias
In some embodiments, an encapsulant covers the electronic component and the interposer. The encapsulant defines a first recess exposing the second conductive element, and the EMI shielding layer extends into the first recess.
In some embodiments, the encapsulant has a lateral surface defining the first recess, and the EMI shielding layer is disposed on two opposite sides of the lateral surface of the recess in a cross-sectional view
In some embodiments, the encapsulant defines a second recess exposing the first conductive element and accommodating an electrical contact.
In some embodiments, the encapsulant defines a second recess exposing the first conductive element, and the EMI shielding layer covers a portion of the encapsulant located between the first conductive element and the second conductive element
In some embodiments, the EMI shielding layer has a first portion on a bottom surface of the encapsulant and a second portion on a lateral surface of the encapsulant, and a thickness of the first portion is greater than a thickness of the second portion
In some embodiments, the EMI shielding layer covers a bottom surface of the encapsulant located between the first conductive element and the second conductive element
In some embodiments, the second conductive element is free of a solder joint at a side abutting the EMI shielding layer.
In some embodiments, a compartment structure penetrates the encapsulating and is electrically connected to the EMI shielding layer
In some embodiments, an encapsulant encapsulates the electronic component. The interposer has an inner lateral surface facing the electronic component and an outer lateral surface opposite to the inner surface, and the outer lateral surface is exposed by the encapsulant.
In some embodiments, an electronic device includes an electronic component, an interposer, and an electromagnetic interference (EMI) shielding layer. The interposer is adjacent to the electronic component and includes a first conductive element and a second conductive element. The EMI shielding layer covers the electronic component and is electrically connected to the second conductive element.
In some embodiments, the EMI shielding structure includes a connecting portion connecting the vertical portion and the horizontal portion, and the connecting portion is slanted with respect to the vertical portion and the horizontal portion.
In some embodiments, a thickness of the connecting portion is less than a thickness of the horizontal portion.
In some embodiments, a composition of the horizontal portion is different from a composition of the vertical portion.
In some embodiments, a signal delivery structure is spaced apart from the electronic component by the vertical portion of the EMI shielding structure.
In some embodiments, the signal delivery structure includes conductive vias surrounding the vertical portion of the EMI shielding structure.
In some embodiments, an electronic device includes an electronic component, an interposer, and an electromagnetic interference (EMI) shielding layer. The interposer is adjacent to the electronic component and includes a first conductive element and a second conductive element. The EMI shielding layer covers the electronic component and is electrically connected to the second conductive element.
In some embodiments, an encapsulant encapsulates the first electronic component and is spaced apart from the second conductive element by a dielectric structure of the interposer.
In some embodiments, a grounding layer is spaced disposed on a lower surface of the encapsulant and electrically connected to the second conductive element.
In some embodiments, the grounding layer vertically overlaps the second conductive element.
In some embodiments, the grounding layer is free from vertically overlapping the first conductive element.
In some embodiments, a second electronic component is disposed adjacent to the first electronic component. A compartment structure is disposed between the first electronic component and the second electronic component. The compartment structure is connected to the grounding layer.
In some embodiments, the encapsulant has a first lateral surface connected to the lower surface and defining a first recess exposing the second conductive element, and the grounding layer completely covers the first lateral surface of the encapsulant.
In some embodiments, the encapsulant has a second lateral surface connected to the lower surface and defining a second recess exposing the first conductive element, and the grounding layer is spaced apart from the second lateral surface of the encapsulant.
In some embodiments, a portion of the grounding layer extends from the first lateral surface toward the second lateral surface.
In some embodiments, the grounding layer has an uneven thickness.
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to =0.1%, or less than or equal to =0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.
Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
As used herein, the term “a distance between A and B” may refer to a length from an edge of the A to an edge of the B or to a length from a center of the A to a center of the B.
As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.