Patent Application
20110062239
1. Field of the Invention
The present invention relates to magnetic data card manufacturing, and in particular to devices and methods for fabricating payments cards with magnetic stripes that can autonomously reprogram some of the magnetic data bits recorded.
2. Description of Related Art
Common everyday use credit cards, debit cards, and access cards, are all now including electronics and batteries to support security and anti-fraud functions. The electronics and batteries integrated inside are up-to the challenges of years of service in the pockets and purses of their users, but the high heats and pressures briefly reached in mass producing plastics can be too much.
So instead of conventional high temperature, high pressure lamination processes, these electronic payment cards are made with reaction injection molded (RIM) methods that limit the temperatures and pressures suffered by the electronics embedded in the payment cards. The two-part plastics encapsulate the components and integrates everything together when the mixture cures.
The familiar magnetic stripes on the backs of credit cards and debit cards is ordinarily recorded once by the manufacturer and provided to the consumers as a fixed, static, permanent data recording. Such recording includes the users' identification and account numbers, and therein lies the problem. QSecure (Los Altos, Calif.) embeds an electronic device, the QChip or QStrip, within the magnetic data stripe of payment cards so that critical bits of the user account number and/or identification are dynamic and not fixed. These can produce use-once account numbers, and simple copying of the payment card's magnetic data will not enable a clone to be used in fraudulent transactions.
The dynamic magnetic data bits of the QChip or QStrip, and the static magnetic data bits in the surrounding magnetic stripe, must be seamlessly meshed together. Gaps in the magnetic recording as the reader transitions along between the magnetic stripe to the QChip and back must be kept to insignificant levels. This requires new methods of manufacturing and device technology that are answered by the embodiments of the present invention.
Briefly, a magnetic device (QChip) embodiment of the present invention comprises an array of bit striplines with relatively low coercivity magnetic material. The bit striplines are able to produce magnetic fields sufficient to individually write several dynamic magnetic data bits into the magnetic material. The device edges physically nearest the leading and trailing dynamic magnetic data bits are trimmed very closely and precisely by scoring the tops by reactive ion etching to produce deep trenches, and then back-grinding up from underneath to the trench bottoms. After being fabricated, each magnetic device can be connected to an application specific integrated circuit (ASIC) either by way of chip-on-chip or chip-on-flexible substrate using a variety of readily available bonding techniques. After attaching a battery to the flex subassembly, the magnetic device can then be inserted into a high precision die or laser cut opening in the magnetic stripe in a payment card. The locations of the static magnetic bits in the magnetic stripe are recorded during card personalization after electronically sensing the exact position of the magnetic device's dynamic magnetic data bits.
An advantage of the present invention is that a manufacturing process is provided for a payment card that has a magnetic device in its magnetic stripe to make that portion of the recorded magnetic data reprogrammable by the internal electronics.
The above and still further objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.
A manufacturing process embodiment of the present invention, herein referred to by the general reference numeral 400, is used to manufacture the sub-assemblies, and fully finished payment cards illustrated in
Discrete components from feeder 402 are soldered to flex-circuits from feeder 401 in a soldering step 420. Microprocessor feeder 403 passes to step 424 for topside under-bump metallization (UBM) and bumping, step 426 for dicing, and step 429 for pick and flip. UBM, for most applications, is the first step in bumping the integrated circuit (IC) bond pad and is critical to the overall success of the bump process. The main functions of a UBM stack include an adhesion layer with a low contact resistance between metal pads; a barrier layer to prevent the diffusion between the various bonding metals. A step 430 uses anisotropic conductive film (ACF) with thermo-compression (TC) bonding methods to bond the microprocessors to the flex-circuits. Alternative methods use anisotropic conductive paste (ACP), normal solder methods, and typical thermosonic bonding methods.
Application specific integrated circuits (ASIC's) from feeder 404 are similarly treated, step 432 provides for topside UBM and bumping, step 434 for dicing, and step 436 for pick and flip. A step 438 uses ACF or TC bonding methods to bond the ASIC's to the flex-circuits.
The details of the QChip referred to herein are described in U.S. patent application Ser. No. 11/479,897, filed Jun. 30, 2006, and titled, Q-CHIP MEMS MAGNETIC DEVICE. Such is incorporated herein by reference in full.
QChip magnetic devices in feeder 405 are given through-chip vias in step 440. Such through-chip vias enables backside connection either by chip stacking or chip to flex bonding and avoids exposing wire or other interconnects to the active side of the QChip that wears against merchant card readers in ordinary use over the service life. A step 442 builds up the magnetic device. A step 444 uses deep reactive-ion etching (DRIE) to create deep, steep-sided trenches laterally across the leading and trailing edges of the active magnetic bits on the QChips. A step 446 backgrinds the QChip, and chemical mechanical planarization (CMP) is used to smooth out the grinding. A step 448 provides for bottom passivation. A step 450 provides top UBM and bumping. A step 451 bottom-saws the devices up to the respective DRIE trenches to complete singulation of chips with the precision edges needed for seamless magnetic bit gaps to mate with, e.g., the magnetic stripe 308 (
The details of the QStrip referred to herein are described in U.S. patent application Ser. No. 11/955,365, filed Dec. 12, 2007, and titled, STRIPLINE MAGNETIC WRITING OF DYNAMIC MAGNETIC DATA BITS IN SURROUNDING REGIONS OF STATIC MAGNETIC DATA BITS. Such is incorporated herein by reference in full.
QStrip feeder 406 begins with a step 452 to put the device build on flex. A step 453 singulates by laser or sawing. A step 454 uses pick and place for a step 456 that uses ACF TC bonding methods to bond the QChip or Qstrip to the flex-circuits. The display feeder 407 passes to a step 458 for pick and place, and a step 460 that uses ACF TC bonding methods to bond the digital display to the flex-circuits. The switch feeder 408 (
The details of the front and back prelaminates, and of injection molding referred to herein, are all described in U.S. patent application Ser. No. 11/871,797, filed Oct. 12, 2007, and titled, PAYMENT CARD MANUFACTURING TECHNOLOGY. Such is incorporated herein by reference in full.
The back prelaminate feeder 410 begins with a plasma treating step 476 that prepares the surfaces to better adhere to the injection plastics and glues. A step 478 cuts the alignment pin holes in the prelaminate sheets. A step 480 cuts the rectangular holes in the magnetic stripe areas for the QChips. A step 482 bonds these to the flex-circuit subassemblies.
The front prelaminate feeder 411 begins with a plasma treating step 484 that prepares the surfaces to better adhere to the injection plastics and glues. A step 486 cuts the alignment pin holes in the prelaminate sheets so the back and front will align properly in a step 488. A step 490 injection molds the polyurethane in feeder 412. A step 492 punches or otherwise singulates the payment cards, and a step 494 personalizes them with account numbers, names, etc.
The back-end processes 514 include die definition using DRIE, back grinding, CMP, saw or laser singulation, solder balls, gold or nickel plated bumps, gold studs, and chip stack technologies.
A flexible PCB level begins with a flexible PCB preparation 520, attaching discrete electronic components 522, attaching chips in step 524 provided from step 514, and attaching the battery 526.
Chip attach step 524 includes local solder reflow, thermocompression, thermosonic, and/or wire bonding the circuit connections. The battery attach step 526 uses ultrasonic welding, conductive epoxy, thermocompression, and/or soldering.
A sheet and card level for process 500 begins with incoming prelaminate sheet inspection and quality assurance step 530, preparation of the sheets step 532, a step 534 for attaching the flexible PCB assembly from step 526, a step 536 for preparing the sheet pairs, a step 538 for injecting the plastic, a step 540 for singulating the cards, and a step 542 for personalizing the cards.
The incoming prelaminate sheet inspection and quality assurance step 530 looks at the surface roughness, thickness, plastic vendor, and other properties. The sheet preparation 532 die or laser cuts or laser cuts the holes, and prepares the surface, e.g., with plasma treatments. Step 534 for attaching the flexible PCB assembly includes elastomer and adhesive dispensing, and adhesive stenciling.
As seen best in
The substrate 602 is typically two hundred microns (um) in vertical (z-axis) thickness, and coils 604 are 25-30 microns in vertical height.
The switch contact studs 710 seen so well in
Applications that require very high tolerance die singulation cannot accommodate the wide tolerances associated with blade dicing or laser dicing. Here, die edge tolerances must be fifteen microns or less to minimize loss of magnetic information in the payment card's magnetic stripe and to maintain a seamless interface (buttability). The requirement can be met by defining the edge of a QChip or QStrip die using an optically precise, photolithographic-based definition technique. U.S. Pat. No. 7,335,576, issued Feb. 26, 2008, to David Ludwig, et al., is informative. Such describes two etching processes, reactive ion etching (RIE) and deep reactive ion etching (DRIE).
Reactive ion etching involves the conversion of an etch gas into a plasma. An electrode is used to accelerate the ions in such a manner as to etch a semiconductor substrate using chemical and physical reactions. Reactive ion etching exhibits some undesirable isotropic etching characteristics, e.g., vertical and lateral etching under a photomask. Making RIE not suitable where highly orthogonal sidewalls are desired. Deep reactive ion etching is a variant of RIE that permits very high aspect ratio features to be fabricated with substantially orthogonal sidewalls because it is an anisotropic process. DRIE is well-suited for bulk silicon etching, but not for etching through silicon oxide/dielectric features in the layers contained in integrated circuit die. Any anisotropic etching process capable of vertical sidewall etching in the substrate may be used in the present invention.
In embodiments of the present invention, two sided buttability is critical, but all four edges can be fabricated using DRIE to be highly orthogonal to one another and the rectangular hole cut for the QChip and QStrip in the back prelaminate sheets.
Once a white card or blank payment card has been fabricated and is ready for personalization, conventional signature panel stamping systems may have problems with electronic type payment cards from the additional surface topography induced by the embedded items. Conventional signature panel stamping has been designed and built for very flat cards, and oven-cured high-pressure processes. A new method is needed to overcome a problem associated with stamping a signature panel onto a plastic payment card that may have slight topographical perturbations.
In
Pressure pad 902 would be appropriately sized for the signature panel and be mounted onto an aluminum screw-on base 904. A silicone rubber slab 906 or other hi-temp rubber compound with an 80-Shore-A resilience, for example, is bonded to the face. For example, slab 906 can be comprised of a styrene-butadiene copolymer like Total Petrochemicals' Finaprene® 411x, or other thermoplastic elastomer type radial styrene-butadiene block copolymer. The edges of the resilient rubber slab 906 are chamfered at 45-degrees all around the edges to the base.
Devices based on 3D chip stacking and integration can significantly outperform traditional planar (2D) devices. Cost reductions and fits within confined spaces are possible by integrating multiple functional entities in one package. Stacking of individual chips, both chip-to-wafer and wafer-to-wafer, has the inherent advantage that different functional subsystems like logic and memory can be processed on separate wafers thereby greatly reducing the complexity and the number of process steps. Individual chips, like ASIC's, microprocessors, and QChips, can be processed on different substrates with different technologies, in different fabs, and by different producers. Wafer-level integration has the advantage of higher throughput and enhanced cleanliness. Standard fab equipment can be used for further processing. 3D integration and chip-to-wafer bonding can be used to stack dies of different sizes, e.g. several small dies on one big base die.
Manufacturing embodiments of the present invention can employ chip to chip and chip to wafer techniques in which 3D stacking mounts an ASIC underneath of a QChip or QStrip with interconnects made by through silicon vias (TSV's) or conventional drill and plate vias. A hybridization method embodiment of the present invention puts the active area of a QChip into the static area of a payment card magnetic stripe. Alternative manufacturing embodiments of the present invention when combined with the prior reference to the Stripline Patent filing will use through-polymer vias, or conventional drill and plate vias.
The chip to wafer techniques of
Although particular embodiments of the present invention have been described and illustrated, such are not intended to limit the invention. Modifications and changes will no doubt become apparent to those skilled in the art, and it was intended that the invention only be limited by the scope of the appended claims.
The invention is claimed, as follows.
