Patent Application
20200355981
The present invention relates to the field of integration and, more particularly, to electronic products, related semiconductor products, and their methods of manufacture.
In recent years semiconductor products have been developed in which different electrical sub-blocks are integrated on a common substrate in order to build functions to generate, transmit, convert, detect, etc. electrical signals. Many advanced chips need to couple electronic functions to additional electronic functions or components either on the same substrate or by stacking according to packaging solutions.
In the example represented in
In devices such as the functional structure illustrated in
Furthermore, in the functional structure 100, it is also desirable to assure good impedance matching of the electrical transmission line that is used to propagate the electrical signal. Indeed, improper impedance matching can result in a large fraction of the electrical wave being reflected back to the source, resulting in loss of efficiency and/or improper control of the functional structure. The impedance Z that is commonly taken as a reference is usually Z=50Ω and the magnitude of the characteristic impedance of the electrical transmission line is Z˜√(L/(C)), where L is the line inductance (H·m−1) and C is the line capacitance (F·m−1). However, in practice, using conventional dielectrics it is difficult to achieve an impedance low enough to assure good impedance matching because the minimum dimensions (critical dimensions, CDs) achievable with conventional technologies (e.g. co-fired ceramics) are limited to several dozens of μm for line width/space within a plane and for the diameter/pitch of a connecting via-hole conductor.
The present invention has been made in the light of the above problems.
The present invention provides an electronic product, comprising: a silicon-on-insulator substrate comprising a base substrate, an insulator layer on the base substrate, and a silicon layer on the insulator layer; a porous layer of anodic oxide or anodic hydroxide formed over the silicon layer; and a metal layer formed over the porous layer, the metal layer providing at least one electrical transmission line, wherein a porosity ratio of the porous layer in a region underlying the metal layer is configured based on a desired velocity of an electrical signal in the at least one electrical transmission line.
In electronic products having the above configuration the porous layer may be formed to contain a large volume of air/vacuum. Moreover, the fraction of air/vacuum in the finished product can be set by controlling the size of the pores that are formed in the porous layer.
By suitable adjustment of the ratio of material and air/vacuum (porosity ratio) present in the porous layer a number of beneficial consequences may be achieved.
Firstly, by suitable adjustment of the porosity ratio of the porous layer, the apparent permittivity εeff of the medium may be controlled. Control of εeff enables control of the velocity factor Vf which is correlated to the velocity of the electrical signal in the electrical transmission line. A desired velocity of the electrical signal in the electrical transmission line, to meet particular application requirements for example, can thus be achieved.
Secondly, the inclusion of air/vacuum in the medium underlying the conductors of the electrical transmission line may result in an increase in impedance, especially if the porosity ratio is large (i.e. the fraction of air/vacuum in the porous layer is large). However, the increase of impedance (related to lowering of coupling capacitance) can be compensated for by reduction of critical dimensions (CDs), for instance: line width/spacing rules can be reduced by 2 orders of magnitude compared to the known MLCC (Multilayer Ceramic Capacitor) approach (e.g. minimum CDs <5 μm can be attained), and this allows the line impedance to be tuned to a lower value. Likewise, vertical dimensions may also be reduced by 2 orders of magnitude compared to MLCC. Thus, the overall size (CDs) can be reduced for a given target impedance and the integration density may be further improved.
Thirdly, by appropriate adjustment of the porosity ratio of the porous layer it is possible to adapt a specific layout of electronic device to different driver frequencies, while maintaining performance.
In an embodiment, the electronic product further comprises an optical waveguide formed within the silicon layer, and the porosity ratio of the porous layer in the region underlying the metal layer is configured so that the velocity of the electrical signal in the at least one electrical transmission line approaches a velocity of an optical signal propagating in the optical waveguide.
In electronic products according to embodiments of the invention, the pores in the porous layer may be tubular in shape. The tubular pores extend towards the underlying silicon layer.
Typically, the porosity ratio of the porous layer may range from 50% up to 91%.
In an embodiment, the porous layer is made of anodic aluminum oxide (MO).
In an embodiment, the electronic product further comprises an anodization control device, formed in the silicon layer, configured to control the porosity ratio of the porous layer during manufacture. The anodization control device is configured such that the voltage drop that occurs during anodization across the region being anodized (the anodic voltage) results in the desired porosity ratio for the region. To control the anodization control device, a metal contact is provided on a surface above the porous layer, and a conductive path is provided to interconnect the metal contact to the anodization control device. In an embodiment, the metal contact comprises a via-hole conductor extending through the porous layer.
In an embodiment, the anodization control device is provided by a diode formed by a p-type region and an n-type region formed in the silicon layer. However, embodiments are not limited to the anodization control device being a diode and other passive devices (e.g., resistors) integrated into the silicon layer may be used in other embodiments.
In another embodiment, the electronic product comprises multiple anodization control devices each configured to control the porosity of a respective region of the porous layer. In an embodiment, the multiple anodization control devices are configured such that regions of different porosities are produced in the porous region. In an embodiment, the porous layer comprises a first porous region having a first porosity ratio and a second porous region having a second porosity ratio.
One or more electrical transmission lines, of same or different types, can be provided in electronic products according to embodiments of the invention. The one or more electrical transmission lines can include transmission lines of the microstrip line type, the coplanar waveguide type, the differential microstrip guide type, etc.
The one or more electrical transmission lines may be constructed on a common substrate having a porous layer with uniform porosity. Alternatively, the one or more electrical transmission lines may be provided over multiple porous regions of varying porosity ratios. This makes it possible to provide, on a common substrate, electrical transmission lines supporting different signal velocity requirements.
In an embodiment, multiple sets of anodization control devices are provided for respective different electrical transmission lines on a common substrate. The properties of each anodization control device are set as required by the porosity ratio that is desired for the porous region(s) associated with the respective electrical transmission line. Anodization in the different regions can thus be achieved by application (e.g. at the periphery of the substrate/wafer) of a common voltage to the different anodization-control devices. This facilitates the anodization process.
The present invention further provides a method of manufacturing an electronic product, the method comprising: forming a first p-type region and a first n-type region in the silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a base substrate, an insulator layer on the base substrate, and the silicon layer on the insulator layer, the first p-type region and the first n-type region forming a first anodization control diode; forming a second p-type region and second n-type region in the silicon layer to form a second anodization control diode; forming a metallic layer over the silicon layer; anodizing the metallic layer, using the first and second anodization control diodes, to form a porous layer of anodic oxide or anodic hydroxide; and forming a metal layer over the porous layer, the metal layer providing at least one electrical transmission line.
According to the above method, the porosity ratio achieved in the porous layer underlying the at least one electrical transmission line, and hence the effective permittivity, can be controlled in a simple manner by control of the anodization process that anodizes the metallic layer. In an embodiment, the porosity ratio of the porous layer in a region underlying the metal layer is configured based on a desired velocity of an electrical signal in the at least one electrical transmission line.
In another embodiment, anodizing the metallic layer comprises controlling the first anodization control diode and the second anodization control diode during the anodization of the metallic layer such that the formed porous layer includes a first porous region having a first porosity ratio and a second porous region having a second porosity ration. In an embodiment, the method comprises applying a common voltage to the first anodization control diode and the second anodization control diode to anodize the metallic layer to form the porous layer.
In a variation of the above method, the anodization control device(s) are provided by other types of passive devices, such as resistors for example.
The present invention further provides an electro-optical product, comprising: a silicon-on-insulator substrate comprising a base substrate, an insulator layer on the base substrate and a silicon layer on the insulator layer; a first pair of adjacent p-type and n-type regions in the silicon layer, the first pair of adjacent p-type and n-type regions defining a first metallurgical junction therebetween having a boundary along the underlying insulator layer, wherein a depletion zone around the first metallurgical junction is a propagation region for an optical signal of a first optical waveguide; a confinement layer formed on the silicon layer and encapsulating the propagation region of the first optical waveguide; porous regions formed of anodic oxide or anodic hydroxide, either side of the confinement layer and bounded by the confinement layer; and patterned metal layers over the anodic oxide/hydroxide regions, the metal layers forming conductors of an electrical transmission line.
In electro-optical products having the above configuration the anodic oxide/hydroxide regions may be formed to contain a large volume of air/vacuum. Moreover, the fraction of air/vacuum in the finished product can be set by controlling the size of the pores that are formed in the anodic oxide/hydroxide regions.
By suitable adjustment of the ratio of material and air/vacuum present in the anodic oxide/hydroxide regions a number of beneficial consequences may be achieved.
Firstly, by suitable adjustment of the ratio of material and air/vacuum present in the anodic oxide/hydroxide regions the apparent permittivity εeff of the medium may be controlled, for example εeff may be lowered to a point such that the velocity factor Vf that is correlated to the velocity of the electrical wave can be increased closer to 1, so that the mismatch which otherwise arises between the velocity of the electrical signal and the optical velocity in the optical waveguide may be reduced. Increasing the velocity of the electrical signal so that it substantially matches that of the optical signal eliminates the need to include an additional loop in the design and this enables the integration density (i.e. the footprint required to implement the electro-optical device) to be reduced. Moreover, even if the velocity of the electrical signal is brought closer to the velocity of the optical signal without matching it, a technical advantage may be obtained because the size of the required additional loop may be reduced.
Secondly, the inclusion of air/vacuum in the medium underlying the conductors of the electrical transmission line may result in an increase in impedance, especially if the porosity ratio is large (i.e. the fraction of air/vacuum in the anodic oxide/hydroxide regions is large). However, the increase of impedance (related to lowering of coupling capacitance) can be compensated for by reduction of critical dimension (CDs), as described above.
Thirdly, by appropriate adjustment of the porosity ratio of the anodic oxide/hydroxide regions it is possible to adapt a specific layout of electro-optical device to different driver frequencies, while maintaining performance.
In electro-optical products according to embodiments of the invention, conductive paths may interconnect the metal layers forming the conductors of the electrical transmission line with the first pair of p-type and n-type regions defining the first metallurgical junction, and the conductive paths may comprise first via-hole conductors extending through the anodic oxide/hydroxide regions.
In electro-optical products according to embodiments of the invention, an n+-type region and a p+-type region may be provided in the silicon layer, and the n+-type region and p+-type region may be electrically connected to the first pair of n-type and p-type regions forming the first metallurgical junction. A first via-hole conductor may interconnect a metal layer defining a first signal conductor of the electrical transmission line with the n+-type region in the silicon layer (and, thereby, with the n-type region defining the first metallurgical junction). A second via-hole conductor may interconnect a metal layer defining a ground conductor of the electrical transmission line with the p+-type region in the silicon layer (and, thereby, with the p-type region defining the first PN junction).
The size of the first and second via-hole conductors, and the spacing of the first and second via-hole conductors from one another, may be configured to match the impedance of the vias to the characteristic impedance of the electrical transmission line.
It is straightforward to control the size and spacing of the via-hole conductors, for example by use of photolithographic processes. Accordingly, by setting the size and spacing of the via-hole conductors in a manner that matches the impedance of the vias to the characteristic impedance of the electrical transmission line, impedance matching can be achieved in a simple manner.
In electro-optical products according to embodiments of the invention, a second pair of adjacent p-type and n-type regions may be provided in the silicon layer over the insulator layer, the second pair of adjacent p-type and n-type regions defining a second metallurgical junction therebetween, and a second n+-type region in contact with the first n-type region may be provided in the silicon layer. A depletion zone around the second metallurgical junction may be configured as a propagation region for an optical signal of a second optical waveguide. The patterned metal layers may include a second signal conductor. A third via-hole conductor may interconnect a metal layer defining the second signal conductor with the second n+-type region in the silicon layer. The first and second signal conductors may be configured to propagate complementary signals. In this way, the electrical transmission line, first optical waveguide and second optical waveguide may be configured to form an electro-optical modulator.
Plural electro-optical modulators having anodic oxide/hydroxide regions of different porosities may be constructed on a common substrate. This makes it possible to provide, on a common substrate, optical waveguides that have different optical lengths (bearing in mind that the optical signal length is correlated with the wavelength of the optical signal propagating in the optical waveguide).
In electro-optical products according to embodiments of the invention, an electro-optical modulator may comprise, along the optical path, sub-regions of anodic oxide/hydroxide having different porosity ratios.
In electro-optical products according to embodiments of the invention, anodization-control diodes may be provided, electrically connected to the p+-type and n+-type regions in the silicon layer. Anodization-control diodes make it possible, during manufacture, to control the porosity ratio that is achieved in the anodic oxide/hydroxide regions. Moreover, if multiple sets of anodization-control diodes are provided for respective different electrical transmission lines on a common substrate, the properties of the various sets of anodization-control diodes can be set differently from each other as required by the porosity ratio that is desired for the anodic oxide/hydroxide regions associated with each electrical transmission line and yet anodization in the different regions can be achieved by application (e.g. at the periphery of the substrate/wafer) of a common voltage to the different anodization-control diodes.
The porous anodic oxide/hydroxide regions may be made of anodic aluminum oxide.
The present invention further provides a method of manufacturing an electro-optical product, the method comprising: forming a first pair of adjacent p-type and n-type regions in the silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a base substrate, an insulator layer on the base substrate and the silicon layer on the insulator layer, the first pair of adjacent p-type and n-type regions defining a first metallurgical junction therebetween having a boundary along the underlying insulator layer; forming over the silicon layer a confinement layer encapsulating a depletion zone around the first metallurgical junction whereby to configure the depletion zone as a propagation region for an optical signal of a first optical waveguide; forming a metal layer over the silicon layer; anodizing the metal layer to form a porous layer of anodic oxide or anodic hydroxide; forming an opening in the anodic oxide/hydroxide layer facing the optical waveguide; and forming metal conductors of an electrical transmission line over the anodic oxide/hydroxide regions either side of the opening.
According to the above method, the porosity ratio achieved in the dielectric underlying the conductors of the electrical transmission line, and hence the effective permittivity, can be controlled in a simple manner by control of the anodization process that anodizes the metal layer.
The present invention further provides a semi-conductor product comprising: a silicon-on-insulator substrate comprising a base substrate, an insulator layer on the base substrate and a silicon layer on the insulator layer; a first pair of adjacent p-type and n-type regions in the silicon layer, the first pair of adjacent p-type and n-type regions defining a first metallurgical junction therebetween having a boundary along the underlying insulator layer, wherein a depletion zone around the first metallurgical junction is configured as a propagation region for an optical signal of a first optical waveguide; a confinement layer formed on the silicon layer and encapsulating the first optical waveguide; and porous regions formed of anodic oxide or anodic hydroxide, either side of the confinement layer and bounded by the confinement layer.
The above-described semiconductor product may be an intermediate product formed during the manufacture of an electro-optical product according to the invention.
The invention still further provides a method of manufacturing a semiconductor product, the method comprising: forming a first pair of adjacent p-type and n-type regions in the silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a base substrate, an insulator layer on the base substrate and the silicon layer on the insulator layer, the first pair of adjacent p-type and n-type regions defining a first metallurgical junction therebetween having a boundary along the underlying insulator layer; forming over the silicon layer a confinement layer encapsulating a depletion zone around the first metallurgical junction whereby to configure the depletion zone as a propagation region for an optical signal of a first optical waveguide; forming a metal layer over the silicon layer; anodizing the metal layer to form a porous layer of anodic oxide or anodic hydroxide; and forming an opening in the anodic oxide/hydroxide layer facing the optical waveguide.
Further features and advantages of the present invention will become apparent from the following description of certain embodiments thereof, given by way of illustration only, not limitation, with reference to the accompanying drawings in which
Regions 308a and 308b having specified doping types and levels are formed in the thin silicon layer 306. In an embodiment, region 308b is a region of relatively light n-type doping, and region 308a is a region of relatively light p-type doping. A PN diode is formed by the regions 308a and 308b. In an embodiment, as shown in
A porous layer 310 is formed over the silicon layer 306. In an embodiment, the porous layer 310 is made of an anodic oxide or an anodic hydroxide. For example, the porous layer 310 can be made of anodic aluminum oxide (MO). In an embodiment, porous layer 310 is formed by anodizing a metallic layer by performing an anodization process in an electrolyte. In this anodization process an oxide or hydroxide forms on the surface of the metallic layer and the electrolyte dissolves the oxide or hydroxide layer along a preferential direction that is determined by the electrical field (i.e. usually perpendicular to the surface). As the electrolyte dissolves the oxide/hydroxide layer, fresh oxide/hydroxide forms on the surface of the metal that becomes exposed. As a result, the metallic layer is converted progressively into the porous layer 310 of anodic oxide or hydroxide having tubular pores extending substantially perpendicularly from the top surface, each pore being separated from the adjacent pore by a wall of oxide or hydroxide. The resulting porous layer 310 has cylindrical pores that are distributed according to a hexagonal pattern (see
Returning to
In an embodiment, the PN diode formed by regions 308a and 308b provides an anodization control diode, which may be used to control the anodization process resulting in the porous layer 310 during manufacture of electronic product 300A. More specifically, the anodization control diode can be used to control the porosity ratio of the porous layer 310, which is a function of the pitch P and the diameter D of pores within the porous layer 310 (see
In another embodiment, the PN diode formed by regions 308a and 308b is replaced with a passive device of a different type, such as a resistor, formed into silicon layer 306. The passive device may be configured as an anodization control device for controlling the porosity ratio of the porous layer 310.
Returning to
Using the above-described anodization control feature, in an embodiment, the porosity ratio of the porous layer 310 is configured based on a desired velocity of the electrical signal in the at least one electrical transmission line. The desired velocity of the electrical signal may be a velocity required to meet particular application requirements. Specifically, to achieve a greater velocity of the electrical signal, the porosity of the porous layer 310 is increased to reduce the effective permittivity of the medium underlying the electrical transmission line. Conversely, a lower velocity is realized by decreasing the porosity of the porous layer 310 to increase the effective permittivity of the medium underlying the electrical transmission line.
The effects demonstrated in
Generally, the uniformity of the porosity of the porous regions depends on the uniformity of the anodization current that is supplied to different parts of the metal layer being anodized during the anodization process. Taking into account the fact that—in the context of integrated circuit manufacturing—it is desirable/necessary to apply the anodization voltage at the periphery of the wafer, it could be doubted whether it would be possible to achieve a suitable degree of uniformity during the anodization process. However, remarkably, suitable uniformity can be achieved when the anodization voltage is applied from a contact area at the periphery of the wafer, for the reasons explained below.
According to other embodiments, different types of electrical transmission lines can be provided by the metal layer formed over the porous layer 310. For example, in an embodiment shown in
According to other embodiments, the porous layer 310 may comprise a plurality of porous regions of varying porosity ratios. The same electrical transmission lines and/or different electrical transmission lines may be formed over the plurality of porous regions. An example electronic product 300C illustrating this concept is shown in
For the purpose of independently controlling the anodization of the first and second porous regions, separate anodization control devices and associated conductive paths are provided. For example, in the embodiment of
In the example embodiment of
Electronic products such as example electronic product 300C may be manufactured starting from a wafer, such as wafer 50 illustrated in
By implementing specific areas having different porosities on a common substrate, it is possible to integrate structures having different electrical signal velocity requirements.
In the following, an electro-optical product making use of aspects of the invention according to an embodiment will be described with reference to
The electro-optical product 1 illustrated in
Region 4a is a region of relatively heavy n-type doping, designated here as an n+-type region, and region 4e is a region of relatively heavy p-type doping, designated here as an p+-type region. The n+- and p+ regions 4a, 4e serve to facilitate electrical connection of the PIN diode's doped regions 4b and 4c to conductors of an electrical transmission line (in this example a coplanar waveguide, see below) and reduce access impedance to the metallurgical junction.
Recesses 6a, 6b are formed on either side of, and spaced somewhat from, the metallurgical junction. A zone 8 between the recesses serves as the propagation region of the optical signal. The zone 8 is surrounded by a confinement material 9 provided overlying the recessed area and filling the recesses 6a, 6b. The confinement material 9 may be made of the same material as the insulator layer 3, for example SiO2. The confinement material 9 ensures that the proper refractive index transitions occur at the boundary surfaces between the optical path and the confinement material 9, which prevents unwanted optical signal losses resulting from parasitic reflections at these boundaries.
The confinement material 9 overlaps over the edges of the n+ and p+-regions 4a, 4e and abuts adjacent regions 10 made of a porous layer of anodic oxide or anodic hydroxide. In this example the porous regions 10 are made of anodic aluminum oxide. An opening 17 is provided through the porous anodic oxide/hydroxide layer 10 overlying the optical path, and the opening 17 is free from anodic oxide/hydroxide so as to avoid unwanted reflections that could otherwise take place at an interface between the optical path and the anodic oxide/hydroxide. The confinement material has guard portions 19 which extend up and over the edges of the porous anodic oxide/hydroxide layer 10 around the periphery of the opening 17. The guard portions 19 serve to control the porosity of the vertical surfaces of the regions 10 adjoining the guard portions 19 and prevent the formation of lateral pores.
Via-hole electrodes 12a, 12b having one end contacting the n+ and p+-regions 4a, 4e, respectively, are provided in via holes that pass through the anodic oxide/hydroxide regions 10, and metal strips 14, 15 corresponding to a signal line and a ground line, respectively, of an electrical transmission line make contact with the other ends of the via-hole electrodes 12a, 12b. In this manner the signal line 14 of the electrical transmission line is connected electrically to the n-type region 4b of the PIN diode, via the n+-region 4a, and the ground line 15 of the electrical transmission line is connected electrically to the p-type region 4d of the PIN diode, via the p+-region 4e. Connections (not shown) are provided for supplying the electrical signal to the conductors of the electrical transmission line and input/output connections (not shown) to the optical waveguide are also provided.
Because the porous regions 10 are formed of anodic oxide or anodic hydroxide, it is possible to form these regions so that they contain a large and adjustable percentage of air or vacuum. This enables the effective permittivity of the medium underlying the conductors of the electrical transmission line to be reduced to a specified value. Reduction in the effective permittivity enables the velocity of the electrical signal in the electrical transmission line to be brought closer to the velocity of the optical signal. The porosity ratio of the porous regions 10 can be set by appropriate control of the dimensions and spacing of the pores as shall be discussed below.
A method of manufacturing the electro-optical product according to an embodiment of the invention will now be described with reference to
According to the manufacturing method of this example, the silicon layer 4 of a Silicon On Insulator (SOI) substrate wafer is subjected to doping, preferably to attain a relatively low level of p-type doping, for example a boron concentration of 1×1017 a/cm3 (the SOI wafer comprises the p type silicon layer 4 above an insulator layer 3 which, here, is a buried oxide layer). At least one PIN diode structure is formed in the silicon layer 4 such that the vertical depth of the PN junction extends to the depth of the buried oxide 3. The PIN diode structure is implemented by implanting dopants of opposite types into respective regions which delimit a volume of silicon that has a very low p-type doping. The implantation process is followed by an activation/drive in a process step (thermal treatment) that forms a metallurgical junction having low doping level on both sides. Alternatively the desired PIN diode structure can be created by performing successive implantation steps to create corresponding highly-doped n/p sub-regions (corresponding to the p-type and n-type regions of the PIN structure) and low-doped n/p sub-regions (corresponding to the central portion of the PIN diode). To reduce access impedance to the intrinsic area, preferably contact areas to the P and N electrodes of the PIN diode are formed to have a heavier doping (or even preferably are formed as silicides) to form the n+-region 4a and p+-region 4e mentioned above.
The p and n doped regions are etched down to form recesses 6a, 6b in the vicinity of the low doped area (near the metallurgical junction) that corresponds to the waveguide for the optical signal.
As shown in
As illustrated in
As illustrated in
Further material having an appropriate value of refractive index is deposited to coat the surfaces of the metal layer 100 at the periphery of the opening 17 and form the guard portions 19 (see
The metal layer 100 is anodized by performing an anodization process in an electrolyte. In this anodization process an oxide or hydroxide forms on the surface of the metal and the electrolyte dissolves the oxide or hydroxide layer along a preferential direction that is determined by the electrical field (i.e. usually perpendicular to the surface). As the electrolyte dissolves the oxide/hydroxide layer, fresh oxide/hydroxide forms on the surface of the metal that becomes exposed. As a result, the metallic layer 100 is converted progressively into a porous layer 10 of anodic oxide or hydroxide having tubular pores extending substantially perpendicularly from the top surface, each pore being separated from the adjacent pore by a wall of oxide or hydroxide. The porous regions 10 are preferably anodic aluminum oxide regions having cylindrical pores that are distributed according to a hexagonal pattern (see
Via holes are etched through the porous regions 10, to expose the underlying n+ and p+-regions 4a,4e and then a metal layer is deposited over the structure and etched by known photolithographic processes to form the via-hole conductors 12 and the conductors 14, 15 of the electrical transmission line. As a result, the coplanar waveguide signal (S) and ground (GND) lines are connected to the respective n-type and p-type regions defining the PN junction used by the optical waveguide (as illustrated in
Because the voltage set to the p-type silicon layer (specifically to region 4a) is anodic (positive) during the anodization process, the diode formed with the n+-region is forward biased (thus non-blocking). As a consequence, the voltage experienced by the thick metallic layer 100 is the voltage applied to the p-type silicon layer 4 at the edge of the wafer, minus the forward voltage drop VF of the diode (which is of the order of 0.6V). As far as the p+-region is concerned the contact is ohmic and therefore has no impact on the voltage distribution (considering the low current density involved in the anodic reaction). As a consequence the anodic oxide/hydroxide regions formed over the silicon layer 4 have approximately equal porosity irrespective of whether they are formed over regions having p-type or n-type polarity.
As described above, because embodiments of the invention employ regions of anodic oxide/hydroxide whose porosity ratios can be set to desired values during manufacture, it becomes possible to create, on a common substrate (wafer), different zones having different effective permittivities (porosity ratios). For example, in a variant electro-optical product 31 that is illustrated in
The anodization-control diodes 40a, 40b may be formed by means of two additional implantation steps. One of these implantation steps implants p-type dopants into small zones that contact the n+-region 4a and p+-region 4e, respectively. The other of these implantation steps implants n-type dopants into adjacent small zones located towards the outside of the structure.
Subsequently, during the anodization process, an anodic voltage is applied to the silicon layer 4, and the voltage experienced by the thick metallic layer 100 corresponds to the voltage of the anodic power supply (VAnodic) decreased by the reverse-bias voltage (Vz) of the anodization-control diodes 40a, 40b described above. As a result, by properly adjusting the properties (notably Vz) of anodization-control diodes 40a, 40b provided at different locations on a wafer, different voltages can be applied to different locations on a common substrate resulting in different levels of porosity at the different locations, while still using a common VAnodic voltage that is applied to the silicon layer 4. The properties of the anodization-control diodes 40a, 40b (e.g., Vz) may be set as desired by appropriate adjustment of the doping of the NP diodes 40a, 40b. In another embodiment, the anodization control diodes 40a, 40b can be designed to be substantially identical and different anodic voltages, configured to result in different anodization levels, are applied to the different locations of the common substrate.
Additional Variants
Although the present invention has been described above with reference to certain specific embodiments, it will be understood that the invention is not limited by the particularities of the specific embodiments. Numerous variations, modifications and developments may be made in the above-described embodiments within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 18305056.6 | Jan 2018 | EP | regional |
The present application is a continuation of International application No. PCT/EP2019/051485, filed Jan. 22, 2019, which claims priority to European Patent Application No. 18305056.6, filed Jan. 25, 2018, the entire contents of each of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP2019/051485 | Jan 2019 | US |
| Child | 16937951 | US |
