Embodiments of the invention relate generally to structures and methods for packaging light emitting semiconductor devices and, more particularly, to electronics packaging that utilizes direct chip metallization to a light emitting semiconductor device, so as to provide for excellent heat transfer from the light emitting semiconductor device with reduced cost and complexity as compared to existing packaging substrates.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Most power semiconductor devices are only used in commutation mode (i.e., they are either on or off), and are therefore optimized for this. One such device is a light emitting semiconductor device, with a prominent example being a light emitting diode (LED). LEDs are semiconductor chips that are packaged to emit radiation in response to an applied voltage or current. These LEDs are used in a number of commercial applications such as automotive, display, safety/emergency, and directed area lighting. LEDs may be fabricated using any materials which emit visible, ultra-violet, or infrared radiation.
As is known in the art, there are various technologies used to assemble and package LEDs for inclusion in a lighting structure. As one example of such LED packaging, LEDs are assembled onto insulated metal substrates (IMS), such as a metal core printed circuit board (MCPCB) or other ceramic-based substrate, for example. The MCPCB includes a metal baseplate (e.g., aluminum baseplate) covered by a thin layer of dielectric material (e.g., an epoxy-based layer) and a layer of copper, with the baseplate then being attached to a heatsink to provide cooling. One face of the LED chip/die is then typically soldered or silver adhesive attached to the copper and the other terminal/face wirebonded to the MCPCB. Alternatively, the LED chip can be packaged in a first level package which can then be soldered to the MCPCB. In this first level package, one face of the LED chip is soldered or silver die attached to a pad on a substrate (metalized ceramic or polymer) and the other terminal/face is attached via wirebond to another pad on the same substrate. As another alternative, the LED chip can be connected to the MCPCB via a flip-chip type attachment.
It is recognized, however, that there are several drawbacks to the existing method of packaging LED chips on a MCPCB and of the wirebonding/flip-chip attachment of the LED chip to the MCPCB. As a primary example, thermal management of the LED chip is challenging for high power applications (i.e., LEDs operated at 5-10 W or higher) when employing traditional packaging of the LED chip on a MCPCB. That is, it is recognized that the layer of dielectric material in the MCPCB (between the metal baseplate and the LED chip) can add unnecessary thermal resistance that may make it difficult to control LED chip-to-board junction temperatures, with these temperature control issues negatively impacting performance and/or efficiency of the LED chip, along with the reliability and “stability” of the LED, i.e., ability to control the intensity and/or wavelength of light emitted by the LED. Failure to control the LED chip-to-board junction temperatures can also lead to a junction temperature above an allowable threshold, which may damage the LED chip and/or lead to interfacial stress and cracks in the MCPCB due to coefficient of thermal expansion (CTE) mismatch between the chip and board. Additional drawbacks of packaging LED chips on a MCPCB include the increased cost and size/thickness of the MCPCB, as well as limitations regarding packing density and integration of the driver and control circuitry with the LED chip and MCPCB package.
Accordingly, it is desirable to provide a light emitting semiconductor device package that is freed from the constraints and drawbacks associated with mounting on a standard MCPCB. The light emitting semiconductor device package would provide improved thermal performance as compared to a standard MCPCB, while doing so in via a compact, low cost package that enables increased packing density and integration of driver and control circuitry.
Embodiments of the invention overcome the aforementioned drawbacks by providing a packaging structure for use with light emitting semiconductor (LES) chips, where the packaging structure makes direct electrical and thermal connections to the LES chip(s). Vias are metalized to input/output (I/O) pads on the LES chip to provide electrical and thermal pathways thereto, with the conductive vias providing improved heat transfer out from the LED chip.
In accordance with one aspect of the invention, a light emitting semiconductor (LES) device includes an insulating substrate layer comprising a top surface and a bottom surface and a plurality of vias formed therein and at least one LES chip mounted on the top surface of the insulating substrate layer, each of the at least one LES chips including an active surface including a light emitting area configured to emit light therefrom responsive to a received electrical power and a back surface positioned on the top surface of the insulating substrate layer and including connection pads thereon. The LES device also includes a conductor layer positioned on the bottom surface of the insulating substrate layer and in the plurality of vias, the conductor layer in direct contact with the connection pads of the at least one LES chip so as to be electrically and thermally connected thereto. The LES device further includes an encapsulant positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the at least one LES chip, the encapsulant comprising a light transmitting material.
In accordance with another aspect of the invention, a method of forming a LES device includes providing a LES chip comprising an active surface having a light emitting area configured to emit light therefrom and a back surface having connection pads thereon, attaching the back surface of the LES chip to a first side of an insulating substrate layer, and forming a conductor layer on a second surface of the insulating substrate layer opposite the first surface, the conductor layer extending through vias in the insulating substrate layer to electrically couple with the connection pads of the LES chip. The method also includes positioning a conductor layer on the bottom surface of the insulating substrate layer and in the plurality of vias, the conductor layer directly coupled to the connection pads of the LES chip so as to be electrically and thermally connected thereto. The method further includes applying an encapsulant over the insulating substrate layer and about the LES chip to at least partially surround the LES chip via a panel process that maintains planarity of the LES device during encapsulation of the LED chip.
In accordance with yet another aspect of the invention, a LES device includes an insulating substrate layer comprising a top surface and a bottom surface and a plurality of vias formed therein and an array of LES components mounted on the top surface of the insulating substrate layer, wherein each LES component comprises an active surface including a light emitting area configured to emit light therefrom and a back surface including connection pads. The LES device also includes a conductor layer positioned on the bottom surface of the insulating substrate layer and in the plurality of vias to provide a direct electrical and thermal path to the array of LES components, the conductor layer comprising conductive vias formed in the plurality of vias and directly coupled to the connection pads of each of the LES components in the array of LES components and conductive plates coupled to the conductive vias and positioned on the bottom surface of the insulating substrate layer, the conductive plates providing anode and cathode connections to the LES device. The LES device further includes an encapsulant positioned adjacent the top surface of the insulating substrate layer and surrounding the array of LES components.
These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention that is provided in connection with the accompanying drawings.
The drawings illustrate embodiments presently contemplated for carrying out the invention.
In the drawings:
Embodiments of the present invention provide a packaging structure for use with light emitting semiconductor chips such as LED chips, where the packaging structure makes direct electrical and thermal connections to the LED chip. Vias are metalized to input/output (I/O) pads on the LED chip to provide electrical and thermal pathways thereto, with the metalized vias providing improved heat transfer out from the LED chip.
Referring to
Referring now to
According to various embodiments, insulating substrate 20 may be provided in the form of an insulating film or dielectric substrate, such as for example a Kapton® laminate flex, an organic film, or substrate comprising polyimide, epoxy, BT resin, although other suitable materials may also be employed, such as Ultem®, polytetrafluoroethylene (PTFE), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide substrate, or inorganic substrates such as Si, SiC, AlN, ceramic, or glass, as non-limiting examples. In one embodiment, a layer of component attach material 24 is used to affix LED chip 12 to a top surface 22 of insulating substrate 20. According to various embodiments, component attach material 24 is an electrically insulating material that is applied to surrounding components of the electronics package by, for example, spin coating, spray coating, or meniscus coating. Component attach material 24 may be a polymeric material (e.g., epoxy, silicone, liquid crystal polymer, or a ceramic, silica, or metal filled polymer) or other organic material as non-limiting examples. According to embodiments, component attach material 24 may be provided on top surface 22 of insulating substrate 20 in either an uncured or partial cured (i.e., B-stage) form, or component attach material 24 may be applied to the LED chip 12 prior to coupling component attach material 24 to top surface 22 of insulating substrate 20.
According to one embodiment, and as shown in phantom in
In alternative embodiments, LED chip 12 may be affixed to insulating substrate 20 by way of an adhesive property of the insulating substrate 20 itself. In such an embodiment, component attach material 24 is omitted and insulating substrate 20 is provided in the form of a single dielectric layer having adhesive properties. Non-limiting examples of such an adhesive dielectric layer include a spin-on dielectric such as polyimide or polybenzoxzaole (PBO).
As shown, LED chip 12 is positioned such that a back surface 27 thereof comprising electrical contact pads or connection pads 26 is positioned into component attach material 24 and such that an active surface or area 28 (i.e., light emitting surface/area) of the LED chip 12 is left exposed. Contact pads 26 provide conductive routes (I/O connections) to internal contacts within LED chip 12. Contact pads 26 may have a composition that includes a variety of electrically conductive materials such as aluminum, copper, gold, silver, nickel, or combinations thereof as non-limiting examples.
Conductor layer 16 is an electrically conductive material that creates a series of electrical connections to the contact pads 26 of LED chip 12. That is, conductor layer 16 extends through a series of vias 30 formed through a thickness of insulating substrate 20 (and also adhesive layer 24)—thereby forming conductive vias 31 that are directly coupled/connected to contact pads 26 on LED chip 12. The conductive vias are joined to large area conductive pads or plates 32 that are formed on bottom surface 18 of the insulating substrate 20.
According to one embodiment, conductor layer 16 (i.e., conductive vias 31 and conductive pads/plates 32) are formed solely of copper. However, other electrically conducting materials or a combination of metal and a filling agent may be used in other embodiments. That is, the conductor layer 16 may be composed of a barrier or adhesion layer, a seed layer, and a relatively thick layer of bulk material that is plated atop the seed and barrier layers achieving the desired conductive layer thickness. In alternative embodiments, the barrier layer and/or the seed layer may be omitted from the wiring layers. The barrier layer, when used, is applied to the insulating substrate 20 prior to application of the seed layer and bulk material. The barrier layer may include titanium or chromium, as non-limiting examples. When used, seed metal layer may be an electrically conductive material such as copper, as one non-limiting example. The layer of bulk material is plated up to achieve the desired thickness of the conductor layer 16, with the bulk material portion of each wiring layer including at least one electrically conductive material such as copper, aluminum, gold, silver, nickel, other standard wiring material, or combinations thereof as nonlimiting examples. However, other electrically conducting materials or a combination of metal and a filling agent may be used in other embodiments. In some embodiments the barrier layer may have a thickness in the approximate range of 0.1 to 0.4 microns, the seed metal layer may have a thickness in the approximate range of 1 to 3 microns and the bulk layer may have a thickness in the approximate range of 10 to 100 microns, with it being recognized that other materials at other thicknesses can be used based on design requirements. Alternatively, conductor layer 16 may be formed of an electrically conductive polymer or formed using inks that contain conductive metal particles.
According to an exemplary embodiment, conductor layer 16 is fabricated as a power overlay (POL) connection having a robust construction, such that the conductor layer 16 (i.e., conductive vias 31 and conductive pads/plates 32) may function as an efficient electrical and thermal connection to LED chip 12. That is, the conductive vias 31 and conductive pads/plates 32 are formed to a desired shape or thickness so as to provide for electrical and thermal connections to LED chip 12. According to one embodiment, the size and number of conductive vias 31 is controlled to maximize heat transfer out from the LED chip 12 and to the conductive pads or plates 32. For example, conductive vias 31 having a diameter of 30 micrometers or greater may be provided, with 1 to 100 conductive vias being formed to the LED chip 12 to remove heat therefrom, with it being understood that the size and number of vias is driven by the pad size of the LED chip. Additionally, the conductive pads or plates 32 in conductor layer 16 are constructed to provide a large area thermal and electrical connection on the bottom side of electronics package 14, with the plates having a thickness of 10 micrometers or greater (e.g., 100 micrometers), to provide for efficient heat removal out from LED chip 12. Heat removal from the LED chip 12 may be controlled based on the specific conductive pads 32 (i.e., which and how many) are connected for second level assembly. According to an embodiment, the conductor layer 16 can also serve as the cathode and anode of the LES device 10.
As further shown in
According to an exemplary embodiment, and as shown in
In another embodiment of LES device 10, and as shown in
While the LES device 10 is illustrated in
According to an exemplary embodiment, the encapsulant 34 may be applied/formed by a panel process that is used to maintain planarity of the LES device during encapsulation of the LED chip 12. That is, as will be explained in further detail below with regard to the fabrication process of LES device 10, the LES device 10 (i.e., insulating substrate 20 thereof) is maintained on a frame during build-up of the LES device 10, and encapsulant 34 is applied onto insulating substrate 20 via a panel process while the insulating substrate is still mounted to the frame. Accordingly, the planarity of a light emitting surface 37 of the LES device 10 may be maintained at a desired level during fabrication thereof—with the light emitting surface 37 being a planar or nearly planar surface. As defined herein, the term “nearly planar” is understood to mean that the light emitting surface is within <500 micrometers of planarity. According to the embodiments illustrated in
According to embodiments of the invention, the electronics package 14 may be constructed as a rigid structure, a flexible structure, or a “flex-rigid” structure where the area about LED chip(s) 12 is rigid/not bendable but the area outside the LED chip(s) would bend freely. That is, in an embodiment where LES device 10 is to be used as a directional light source, then electronics package 14 may be built as a rigid structure, with conductor layer 16, insulating substrate 20, and encapsulant 34 being structured to provide rigidity to the LES device 10. In an embodiment where LES device 10 is to be used in a product having a curved surface or shape, such as round lamp bulbs, flood lights, cylindrical flashlights, etc., then electronics package 14 may be built as a flexible structure or flex-rigid structure, with conductor layer 16, insulating substrate 20, and encapsulant 34 being structured to provide flexibility to the LES device 10. As examples of providing such flexibility, the insulating substrate 20 may be formed as a flexible film, and the encapsulant 34 may have a partitioned construction, with the encapsulant 34 around each LED chip 12 being partitioned/sectioned from the encapsulant 34 around adjacent LED chips 12 by way on slits 38 formed in the encapsulant 34 that provide flexibility between adjacent encapsulate sections, with it being recognized that the insulating substrate 20 could extend outside the region of encapsulant 34, based on the planned use of the LES device 10. These flexible features in electronics package 14 allow the electronics package to generally conform to a shape/pattern of the device or component in which LES device 10 is incorporated.
Referring now to
Referring first to
The LED chip 12 is coupled to insulating substrate 20 by positioning the back surface of the LED chip 12 on the component attach material 24 using conventional pick and place equipment and methods, as shown in
Referring now to
Upon securing LED chip 12 onto the insulating substrate 20 and following the formation of vias 30, the vias 30 are cleaned (such as through a reactive ion etching (ME) desoot process or laser process) and subsequently metalized to form conductor layer 16, as shown in
Conductor layer 16 extends through vias 30 to form conductive vias 31 that electrically couple with contact pads 26 of LED chip 12, with conductor layer 16 being formed to a desired shape or thickness on bottom surface 18 to form conductive pads or plates 32 that provide for electrical and thermal connections to LED chip 12. According to one embodiment, the size and number of conductive vias 31 is controlled to maximize heat transfer out from the LED chip 12 and to the conductive pads or plates 32. For example, conductive vias 31 having a diameter of 30 micrometers or greater may be provided, with 1 to 100 conductive vias being formed to the LED chip 12 to remove heat therefrom. Additionally, conductive pads or plates 32 are constructed to provide a large area thermal and electrical connection on the bottom side of electronics package 10, with the pads/plates having a thickness of 10 micrometers or greater (e.g., 100 micrometers), for example, to provide for efficient heat removal out from LED chip 12. In forming conductor layer 16, a photoresist mask (not shown) may be formed on the conductor layer 16 and patterned with openings. With the first layer photoresist mask in place, the conductor layer 16 is subsequently patterned using an etching process to yield a patterned conductor layer 16 as shown in
Referring now to
Referring now to
The encapsulant 34 may be in the form of silicone another suitable light transmitting material and is applied to surround sides of the LED chip 12. The encapsulant 34 may also be applied over the active surface 28 of LED chip 12 to protect the active area 28 thereof while permitting light to pass therethrough, or alternatively a window/opening may be left open over the active surface 28 of LED chip 12 and active area thereof. In the embodiment of
According to an exemplary embodiment, the encapsulant 34 may be applied/formed by a panel process that is used to maintain planarity of the LES device during encapsulation of the LED chip 12. As shown in
Beneficially, embodiments of the invention provide a packaging structure for use with light emitting semiconductor chips such as LED chips, where the packaging structure makes direct electrical and thermal connections to the LED chip. These electrical and thermal pathways provided by the packaging structure enable efficient heat transfer out from the LED chip, with a thermal resistivity at a junction between the LED chip and the insulating substrate layer being between 0.5 and 1.0 C/W. A junction temperature between the LED chip and the insulating substrate layer 20 may thus be maintained between 85° C. and 95° C. during operation of the LES chip, according to an exemplary embodiment. The LED chip is thereby provided with improved thermal performance, low junction temperatures, and thus higher reliability (and improved/higher lumen output) as compared to a standard MCPCB to which LED chips are typically mounted. The LED chip packaging structure provides this improved thermal performance in a compact, low cost package that is freed from the constraints and drawbacks associated with mounting on a standard MCPCB. Additionally, the LED chip packaging structure may be configured as a flexible structure that provides for an arrangement of LED chips in various complex shapes, with the flexible interconnect structure conforming around complex shapes such as those typical in general incandescent lighting, for example, while still providing a robust interconnect to the LED chips.
Therefore, according to one embodiment of the invention, a light emitting semiconductor (LES) device includes an insulating substrate layer comprising a top surface and a bottom surface and a plurality of vias formed therein and at least one LES chip mounted on the top surface of the insulating substrate layer, each of the at least one LES chips including an active surface including a light emitting area configured to emit light therefrom responsive to a received electrical power and a back surface positioned on the top surface of the insulating substrate layer and including connection pads thereon. The LES device also includes a conductor layer positioned on the bottom surface of the insulating substrate layer and in the plurality of vias, the conductor layer in direct contact with the connection pads of the at least one LES chip so as to be electrically and thermally connected thereto. The LES device further includes an encapsulant positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the at least one LES chip, the encapsulant comprising a light transmitting material.
According to another embodiment of the invention, a method of forming a LES device includes providing a LES chip comprising an active surface having a light emitting area configured to emit light therefrom and a back surface having connection pads thereon, attaching the back surface of the LES chip to a first side of an insulating substrate layer, and forming a conductor layer on a second surface of the insulating substrate layer opposite the first surface, the conductor layer extending through vias in the insulating substrate layer to electrically couple with the connection pads of the LES chip. The method also includes positioning a conductor layer on the bottom surface of the insulating substrate layer and in the plurality of vias, the conductor layer directly coupled to the connection pads of the LES chip so as to be electrically and thermally connected thereto. The method further includes applying an encapsulant over the insulating substrate layer and about the LES chip to at least partially surround the LES chip via a panel process that maintains planarity of the LES device during encapsulation of the LED chip.
According to yet another embodiment of the invention, a LES device includes an insulating substrate layer comprising a top surface and a bottom surface and a plurality of vias formed therein and an array of LES components mounted on the top surface of the insulating substrate layer, wherein each LES component comprises an active surface including a light emitting area configured to emit light therefrom and a back surface including connection pads. The LES device also includes a conductor layer positioned on the bottom surface of the insulating substrate layer and in the plurality of vias to provide a direct electrical and thermal path to the array of LES components, the conductor layer comprising conductive vias formed in the plurality of vias and directly coupled to the connection pads of each of the LES components in the array of LES components and conductive plates coupled to the conductive vias and positioned on the bottom surface of the insulating substrate layer, the conductive plates providing anode and cathode connections to the LES device. The LES device further includes an encapsulant positioned adjacent the top surface of the insulating substrate layer and surrounding the array of LES components.
While the invention has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. Additionally, while various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.