The present invention relates to apparatus and methods for packaging a microelectronic component with one or more optical components in a compact yet functional manner. In particular, the present invention relates to a packaging technology that aligns and secures an electrooptic element between a microelectronic package and a substrate with a waveguide.
Higher bandwidth, improved performance, lower cost, and increased miniaturization are ongoing goals of the computer industry to enhance communication between chips within a computer. It is known that integrated circuit components have undergone increased miniaturization and, as this goal is achieved, microelectronic dies become still smaller. Similar miniaturization of the microelectronic package is desirable as it would enable reductions in cost and component external dimensions (form factor).
As for achieving higher bandwidth, e.g., on the order of 10 Gb/s or more, optical interchip communications face many challenges. Among these challenges are high bandwidth, low latency communication between the microprocessor and the optical emitter/detector chips, alignment and coupling between the optical emitter/detector chips and a waveguide, and maintaining acceptable cost. Until now, the difficulty of meeting all of these challenges has meant that interchip communications are typically achieved in an electronic manner.
Meeting the challenges facing optical interchip communications will provide significant benefits, including the higher bandwidth that optical interchip communication provides as well as reduced noise from sources such as electromagnetic interference (EMI) and crosstalk. However, it will be necessary for electrooptic assemblies to provide good alignment to waveguide structures that may be located on the printed circuit board, low electrical parasitics between the microprocessor and optical emitter/detector chips, and relatively low cost fabrication.
Therefore, it would be advantageous to develop new apparatus and methods for securing a microelectronic package to a substrate such as a printed circuit board with an electrooptic element in alignment with a coupler and waveguide integrated into the printed circuit board (electrooptic PCB) to provide a suitable electrooptic assembly.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
Although
The present invention includes a packaging technology that secures a microelectronic package to an electrooptic PCB in a manner that secures an electrooptic element in alignment with a coupler and waveguide in the electrooptic PCB. The electrooptic element is disposed between the microelectronic package and the electrooptic PCB to convert an electrical signal from a microelectronic die in the microelectronic package to an optical signal that is transmitted to the coupler and waveguide. Alternatively, the electrooptic element can convert an optical signal from the coupler and waveguide in the electrooptic PCB to an electrical signal that is transmitted to the microelectronic package.
In particular, an adhesive-type protective film 28 may be applied prior to placing the microelectronic die 30 and microelectronic package core 20 in a mold or other piece of equipment which can be used for an encapsulation process. The protective film 28 may also be a non-adhesive film, such as a EPFE (ethylene-petrafluoroethylene) or Teflon® film, which is held on the microelectronic die active surface 32 and the microelectronic package core first, or active surface 24 by an inner surface of a mold or other piece of equipment which can be used for an encapsulation process. In either case, the protective film 28 will be removed from the active surface 32 of the microelectronic die 30 and the first, or active surface 24 of the microelectronic package core 20, following an encapsulation process.
The microelectronic die 30 is then encapsulated using an encapsulation material 36 to fill the portions of the opening 22 in the microelectronic package core 20 which are not occupied by the microelectronic die 30, as shown in
After encapsulation, the protective film 28 is removed, as shown in
As shown in
As shown in
A plurality of conductive traces 46 is formed on the dielectric layer 42, as shown in
The plurality of conductive traces 46 may be formed by any known technique, including but not limited to semi-additive plating and photolithographic techniques. An exemplary semi-additive plating technique can involve depositing a seed layer, such as a sputter-deposited or electroless-deposited metal on the dielectric layer 42. A resist layer can then be deposited and then patterned on the seed layer. A layer of metal, such as copper, can then be applied by electrolytic plating on the seed layer exposed by open areas in the patterned resist layer. The patterned resist layer can then be stripped and portions of the seed layer not having the layer of metal plated thereon can be etched away to complete the formation of the conductive traces 46. While the foregoing sets forth one known technique for forming conductive traces, other methods of forming the plurality of conductive traces 46 will be apparent to those skilled in the art.
The sequence of process steps used to deposit the dielectric material, form vias, and form traces can be repeated as needed to dispose the traces in such positions as may be required to achieve a suitable interconnection or to meet electrical or other performance requirements. Once the conductive traces 46 are formed, they can be used in the formation of conductive interconnects with solder bumps, solder balls, pins, and the like for communication with external components, such as an optical substrate. For example, a soldermask material 48 can be disposed over the dielectric layer 42 and the conductive traces 46 with soldermask openings 51, as shown in
As shown in
Alignment between the electrooptic element and the coupler may be achieved by solder self-alignment. Such self-alignment may be achieved, for example, by BGA reflow. Successful alignment by this method requires accurate placement of the coupler with respect to the BGA solder mask openings of the optical substrate.
Still referring to
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
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