Patent Application
20100091475
The present disclosure generally relates to stacked integrated circuits (ICs). More specifically, the present disclosure relates to shielding stacked ICs from electrostatic discharge.
Electrostatic discharge (ESD) events are a common part of everyday life and some of the larger discharges are detectable by the human senses. Smaller discharges go unnoticed by human senses because the ratio of discharge strength to surface area over which the discharge occurs is very small.
ICs have been shrinking at an incredible rate over past decades. By way of example, transistors in ICs have shrunk to 45 nm and will likely continue to shrink. As transistors shrink in size, the supporting components around transistors generally shrink as well. The shrinking of ICs decreases surface area. Thus, the ratio for a given discharge strength to surface area increases with smaller component sizes, and the components become susceptible to a larger range of ESD events.
An ESD event occurs when an object at a first charge comes near or into contact with an object at second, lower charge. The differential discharges as a single event. Rapid transfer of charge from the first object to second object occurs such that the two objects are at approximately equal charge. Where the object with lower charge is an IC, the discharge attempts to find the path of least resistance through the IC. Typically, this path flows through interconnects. Any part of this path that is unable to withstand the energy associated with the discharge sustains damage. Such damage often occurs in the gate oxide, which is generally the link most susceptible to discharge in ICs. When the gate oxide is damaged, it typically changes from an insulator to a conductor, such that the IC will no longer function as desired. Alternative mechanisms of damage for the ESD event include rupturing of the gate oxide in a through silicon via to create a short circuit in the device or fusing of the metal in an interconnect to create an open circuit in the device.
Fabrication sites where the manufacturing of integrated circuits is carried out have matured and implemented procedures to prevent ESD through integrated circuits during manufacturing. For example, design rules are used to assure that large charges do not accumulate during manufacturing. Conventionally, ESD protective structures are also built into the substrate and connected to the devices for protection. These structures consume a considerable amount of area (tens to hundreds of square microns for each ESD buffer) on the substrate that could otherwise be used for active circuitry. However, an ESD event may still occur during the process of manufacturing an IC. Detecting such damage sites in an IC is difficult, and the first sign that such damage occurred during manufacture typically occurs when the end product does not function as desired. As a result, a significant amount of time and resources may be spent manufacturing a device that does not function correctly.
One recent development in further advancing ICs capabilities is stacking integrated circuits to form a 3-D structure or stacked IC. This allows multiple components to be built into a single chip in separate tiers. For example, a memory cache may be built on top of a microprocessor. The resultant stacked IC has significantly higher densities of devices and significantly more complex manufacturing methods. It is anticipated that tier-to-tier connection densities in stacked ICs will exceed 100,000/cm2.
For stacked ICs, manufacturers may perform a first set of IC manufacturing processes at one fabrication site and ship that IC tier to a second fabrication site that performs a second set of manufacturing processes for the second tier. A third site may then assemble the tiers into the stacked IC. When tiers of the integrated circuits leave the controlled environment of the manufacturing sites, they are exposed to potential ESD events that can render an entire stacked IC useless. Before the individual tiers are stacked, (i.e., bonded together to create the stacked IC), the tiers are especially vulnerable to ESD events.
As a result, there is a need to protect individual tiers of stacked integrated circuits from ESD events when transported outside of controlled environments during the manufacturing process.
According to one aspect of the disclosure, an unassembled stacked IC device includes an unassembled tier. The unassembled stacked IC device also includes a first unpatterned layer on the unassembled tier. The first unpatterned layer protects the unassembled tier from ESD events.
According to another aspect of the disclosure, a method for manufacturing a stacked IC device includes manufacturing a tier of the stacked IC device. The method also includes depositing an unpatterned layer on the tier before transporting to an assembly plant. The unpatterned layer protects the tier from ESD events.
According to yet another aspect of the disclosure, a method for manufacturing a stacked IC device includes altering an unpatterned layer protecting a tier of a stacked IC device from ESD events to allow the tier of the stacked IC device to be integrated into the stacked IC device. The method also includes integrating the tier into the stacked IC device.
According to a further aspect of the disclosure, an unassembled stacked IC device includes means for shielding the unassembled stacked IC device from ESD events prior to assembling the stacked IC device.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.
In
Turning now to
During handling and processing of the wafer, an ESD source 23 at a relatively higher charge than the device 20 may come near or in contact with the substrate 21. For example, an ESD source 23 may come into contact with an exposed connection such as the tier-to-tier connection 228. Near or upon contact with the exposed connection, the ESD source 23 will discharge into the device 20 to reach equilibrium. A current flow 24 will form to make a complete circuit. The current flow 24 will follow the path of least resistance through the device 20. In the present case, this path may be through the tier-to-tier connection 228, the interconnect 226, the intermediate layer 224, the interconnect 222, and the contact layer 220. The current flow 24 then flows through the substrate 21 to the through silicon via 214 and through the contact layer 220, the interconnect 222, the intermediate layer 224, the interconnect 226, and the tier-to-tier connection 228 creating a closed path with the ESD source 23. Anything in the path of the current flow 24 may potentially sustain damage that may result in failure of the device 20 through the mechanisms described earlier.
Turning now to
According to an aspect of the present disclosure, a device and its components are protected from ESD damage during the manufacturing process while outside controlled environments by depositing a thin film coating on the device. The coating may be an insulator (such as silicon oxide, silicon nitride, or polymer), a semiconductor (such as silicon), or a metal (such as copper). A metal or semiconductor coating provides a path of relatively low resistance for the current flow resulting from an ESD event, thereby preventing the current from damaging sensitive components under the protective layer. Alternatively, an insulator coating prevents the current flow from an ESD event through the components under the protective layer. Several embodiments of the coating will be further described in detail.
According to one embodiment, an insulating protective layer is used to protect the device from ESD events. Some materials that may be used for the insulating protective layer include silicon oxides, silicon nitrides, polymers, photoresist, or spin on glasses (SOGs). The thickness of the protective layer may vary based on the circuit design and the manufacturing process. According to one embodiment, the layer is 100-50000 Angstroms in thickness. If additional ESD prevention is desired, the thickness can be increased. Thicker insulating layers may withstand larger potential differences before experiencing breakdown and allowing current flow from the ESD source to the device. If ESD prevention is sufficient and quicker manufacturing processes are desired, the layer may be thinner. Thinner insulating layers are easier and faster to remove or pattern in future processing. In one embodiment, the layer is thick enough to mechanically withstand transportation.
Turning now to
After the insulating protective layer is deposited and the device is transported to a second controlled environment (for example a testing and assembly plant), the insulating protective layer may be removed before assembly of the stacked IC. According to one embodiment, the layer may be stripped using available methods such as wet or dry etching. According to another embodiment, the protective layer may be patterned such that contact can be made to the tier-to-tier connections below the insulating protective layer. Openings in the insulating protective layer are etched away to reveal the tier-to-tier connections below. Metal contacts may then be deposited in the etched openings. These etched openings will now be described in further detail.
According to another embodiment, a metal protective layer or semiconductor protective layer may protect the device from ESD events outside of controlled environments. In such an arrangement, the final layer of connections is left unpatterned resulting in an unpatterned metal layer remaining on the surface of the device. The layer is left unpatterned such that any current resulting from an ESD event travels through the protective layer instead of through the IC. The final connections are patterned from the protective metal layer after transport to a second fabrication site. The metal could be, for example, copper or aluminum depending on device design. In one embodiment, semiconductor materials, such as poly-silicon are used. The thickness of the protective layer should be thick enough to mechanically withstand transport and electrically withstand current densities anticipated from ESD sources.
Turning now to
In the case of a metal protective layer, no additional costs or procedures are added to the fabrication process. The metal layer typically patterned to form interconnects is left unpatterned such that a continuous metal layer remains on the surface of the die. This metal layer serves as the protective layer until the die reaches another fabrication facility at which time the layer is patterned into interconnects. In the case of an insulator protective layer, additional procedures and layers are implemented; however, the additional cost of these layers is offset by the savings gained from not fabricating ESD devices in the silicon and the savings in occupied silicon area.
Although specific circuitry has been set forth, it will be appreciated by those skilled in the art that not all of the disclosed circuitry is required to practice the disclosure. Moreover, certain well known circuits have not been described, to maintain focus on the disclosure.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
