An enhancement mode gallium nitride (GaN) transistor is a recent development. In a GaN transistor, a P-type GaN (pGaN) gate is grown on top of aluminum gallium nitride (AlGaN)/GaN structure to create a positive threshold voltage. Known pGaN gate structures, however, do not have optimized thicknesses, which can lead to dielectric failure if the pGaN structure is too thick, or can lead to an over-conductance of current if the pGaN gate structure is too thin.
Known enhancement mode GaN transistors all have gates with pGaN structures of thicknesses t of at least 1000 Å. For example, X. Hu, et al., “Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate,” 36 Electronic Letters, Issue 8, at pp. 753-54 (Apr. 13, 2000) teaches a 1000 Å pGaN structure. In addition, U.S. Patent Application Publication No. 2006/0273347 teaches pGaN structures with thicknesses of 1000 Å. However, explained below, pGaN thicknesses t greater than or equal to 1000 Å can lead to dielectric failure.
It is apparent from the foregoing that 1000 Å is too thick for a pGaN gate structure in an enhancement mode GaN transistor. It would desirable, therefore, to provide an enhancement mode GaN transistor with a pGaN gate that is sufficiently thin to avoid the risk of dielectric failure.
The present invention is directed to an enhancement mode GaN transistor having a pGaN gate structure thin enough to avoid dielectric failure. In one embodiment, for 5V gate voltage applications, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å. Such thicknesses are thick enough to avoid over-conductance of current.
The present invention is directed to an enhancement mode GaN transistor having a pGaN gate thickness in the range of 400 Å to 900 Å. Such a range is thin enough to avoid dielectric failure. As described below, such a range is also thick enough to avoid the problems associated with pGaN gates that are too thin. In a preferred embodiment, the pGaN gate thickness is 600 Å.
The pGaN gate structure is Mg doped and activated to p-type conductivity. In one embodiment, the pGaN gate structure is a semi-insulating GaN that is doped with Mg and compensated with hydrogen.
As shown in
As shown in
The above gate thicknesses and measurements relate to a device operated at a rated gate voltage of 5V. Obviously, at lower rated gate voltages, the thickness of the pGaN structure would be correspondingly reduced. Thus, the enhancement mode GaN transistor has a gate structure with a thickness of a factor A×(400 Å to 900 Å), wherein the factor A corresponds to the ratio of rated gate voltage/5V. The term “rated gate voltage” in the above-described embodiments means the maximum safe operating gate voltage of the device.
The above description and drawings are only to be considered illustrative of a specific embodiment of the invention which achieves the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. Accordingly, the invention is not considered as being limited by the foregoing description and drawings.
This application claims the benefit of U.S. Provisional Application Ser. No. 61/167,788, filed Apr. 8, 2009, which is incorporated by reference in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
6897495 | Yoshida et al. | May 2005 | B2 |
6914273 | Ren et al. | Jul 2005 | B2 |
20060220060 | Nakata et al. | Oct 2006 | A1 |
20060273347 | Hikita et al. | Dec 2006 | A1 |
20070164314 | Beach et al. | Jul 2007 | A1 |
20070272945 | Matsuo et al. | Nov 2007 | A1 |
20080079023 | Hikita et al. | Apr 2008 | A1 |
20080296618 | Suh et al. | Dec 2008 | A1 |
20090072272 | Suh et al. | Mar 2009 | A1 |
Number | Date | Country |
---|---|---|
2007-311733 | Nov 2007 | JP |
Entry |
---|
X. Hu, et al. “Enhancement Mode AIGaN/GaN HFET With Selectively Grown pn Junction Gate”, Electronics Letters, vol. 35, No. 8, pp. 753-754, Apr. 13, 2000. |
T. Fuji et al. “High On/Off Ratio in Enhancement-Mode AIxGax1-N/GaN Junction Heterostructure Field Effect Transistors with P-Type GaN Gate Contact”, Japanese Journal of Applied Physics, vol. 45, No. 39, pp. L1048-L1050, 2006. |
Y. Uemoto et at. Gate Injection Transistor (GIT)—A Normally-Off A1GaN/GaN Power Transistor Using Conductivity Modulation, IEEE Transactions on Electron Devices, vol. 54, No. 12, pp. 3393-3399, Dec. 2007. |
Number | Date | Country | |
---|---|---|---|
20100258842 A1 | Oct 2010 | US |
Number | Date | Country | |
---|---|---|---|
61167788 | Apr 2009 | US |