Fabricating an electroconductive contact on a top layer of a tunneling magnetoresistance element using two hard masks

Abstract

In one aspect, a method includes depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure; depositing a first hard mask on the MR layers; depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask; etching the exposed portions of the first hard mask; etching a portion of the MR layers using the first hard mask; depositing a second hard mask on a first capping layer; depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask; etching the exposed portions of the second hard mask; etching the MR element using the second hard mask; etching portions of the first hard mask down to a top MR layer of the MR element; and depositing a conducting material on the top MR layer to form an electroconductive contact.

Description

BACKGROUND

A magnetic field sensing element is used to describe a variety of electronic elements that can sense a magnetic field. The magnetic field sensing element can be, but is not limited to, a Hall effect element, a magnetoresistance element, or a magnetotransistor. As is known, there are different types of Hall effect elements, for example, a planar Hall element, a vertical Hall element, and a Circular Vertical Hall (CVH) element. There are different types of magnetoresistance elements, for example, a semiconductor magnetoresistance element such as Indium Antimonide (InSb), a giant magnetoresistance (GMR) element, for example, a spin valve, an anisotropic magnetoresistance element (AMR), a tunneling magnetoresistance (TMR) element, and a magnetic tunnel junction (MTJ). The magnetic field sensing element may be a single element or, alternatively, may include two or more magnetic field sensing elements arranged in various configurations, e.g., a half bridge or full (Wheatstone) bridge. Depending on the device type and other application requirements, the magnetic field sensing element may be a device made of a type IV semiconductor material such as Silicon (Si) or Germanium (Ge), or a type III-V semiconductor material like Gallium-Arsenide (GaAs) or an Indium compound, e.g., Indium-Antimonide (InSb).

SUMMARY

In one aspect, a method includes depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure, the MR layers comprising a top MR layer, a middle MR layer, and a bottom MR layer; depositing a first hard mask on the MR layers; depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask; etching the exposed portions of the first hard mask; etching a portion of the top MR layer and a portion of the middle MR layer using the first hard mask; depositing a first capping layer on the bottom MR layer and on the first hard mask; depositing a second hard mask on the first capping layer; depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask; etching the exposed portions of the second hard mask; etching a portion of the bottom MR layer using the second hard mask; depositing a second capping layer; depositing and patterning a third photoresist on the second capping layer using photolithography to expose portions of the second capping layer; etching the exposed portions of the second capping layer down to the first hard mask; depositing and patterning a fourth photoresist using photolithography to expose portions of the first hard mask; etching the portions of the first hard mask not covered by the fourth photoresist down to the top MR layer; and depositing a conducting material on the top MR layer to form an electroconductive contact.

DESCRIPTION OF THE DRAWINGS

The foregoing features may be more fully understood from the following description of the drawings. The drawings aid in explaining and understanding the disclosed technology. Since it is often impractical or impossible to illustrate and describe every possible embodiment, the provided figures depict one or more illustrative embodiments. Accordingly, the figures are not intended to limit the scope of the broad concepts, systems and techniques described herein. Like numbers in the figures denote like elements.

FIG. 1 is a block diagram of a prior art example of a tunneling magnetoresistance (TMR) element;

FIGS. 2A to 2U are diagrams of an example fabrication of an electroconductive contact on a top layer of a TMR element using two hard masks; and

FIG. 3 is a flowchart of an example of a process to fabricate the electroconductive contact on the top layer of the TMR element using two hard masks.

DETAIL DESCRIPTION

Described herein are techniques to fabricate an electroconductive contact on a top layer of a tunneling magnetoresistance (TMR) element using two hard masks. The techniques described herein may be used to fabricate an electroconductive contact on a top layer of more than one TMR element. In one example, a diameter of the TMR element is a micron or less. In another example, a diameter of the TMR element is a half micron or less. While the detailed description herein focuses on TMR elements other types of magnetoresistance elements (e.g., a giant magnetoresistance (GMR) element) may be used.

As used herein the term “hard mask” is used to describe a type of barrier that is used during a photolithography/etch process, which can be distinguished from photoresist mask (i.e., soft mask). For example, the hard mask may include material such as silicon dioxide and/or silicon nitride. In some examples, the hard mask may include at least one of silicon dioxide, silicon nitride, polysilicon, and/or oxide-nitride-oxide (ONO). Alternatively, any other suitable materials may be used to form the hard mask, which can a) withstand oxidation process (i.e., not get burnt in a furnace) and/or b) provide a barrier against oxidation of silicon layer underneath.

Referring to FIG. 1, an illustrative TMR element 100 can have a stack 102 of layers 106, 110, 114, 118, 122, 126, 128, 132 indicative of one pillar of a multi-pillar TMR element. Generally, the layer 106 is a seed layer (e.g., a copper nickel (CuN) layer) with the layer 110 located on the seed layer 106. The layer 110 may include platinum manganese (PtMn) or iridium manganese (IrMn), for example. The layer 114 is located on the layer 110 and the layer 118 is located on the layer 114. In one example, the layer 114 may include cobalt iron (CoFe) and the layer 118 is a spacer layer and may include ruthenium (Ru).

On the layer 118, a magnesium oxide (MgO) layer 126 is sandwiched between two cobalt iron boron (CoFeB) layers 122, 128. The layer 126 functions as a tunneling barrier.

A cap layer 132 (e.g., tantalum (Ta)) is located on the CoFeB layer 128. The layer 114 is a single layer pinned layer that is magnetically coupled to the layer 110. The physical mechanism that is coupling layers 110 and 114 together is sometimes called an exchange bias.

A free layer 130 may include the CoFeB layer 128. In some examples, the free layer 130 may include an additional layer of nickel iron (NiFe) (not shown) and a thin layer of tantalum (not shown) between the CoFeB layer 128 and the NiFe layer.

It will be understood that a driving current running through the TMR element 100 runs through the layers of the stack, running between seed and cap layers 106 and 132, i.e., perpendicular to a surface of a bottom electrode 104. The TMR element 100 can have a maximum response axis that is parallel to the surface of the bottom electrode 104 and that is in a direction 129, and also parallel to the magnetization direction of the reference layer 150, comprised of layers 110, 114, 118, and 122, most notably in the layer CoFeB 122.

The TMR element 100 has a maximum response axis (maximum response to external fields) aligned with the arrow 129, i.e., perpendicular to bias directions experienced by the free layer 130, and parallel to magnetic fields of the reference layer 150, notably pinned layer 122. Also, in general, it is rotations of the magnetic direction of the free layer 130 caused by external magnetic fields that result in changes of resistance of the TMR element 100, which may be due to a change in angle or a change in amplitude if an external bias is present because the sum vector of the external field and the bias is causing a change in the angle between the reference and free layers.

FIGS. 2A to 2U depict one example to fabricate an electroconductive contact on a top layer of one or more TMR elements (e.g., TMR element 100 (FIG. 1)). In one example, the fabrication of the electroconductive contact may begin with a cushioned layered structure.

In one example, the TMR elements have a diameter that is a micron or less. In some examples, the TMR element has a diameter that is a half micron or less.

Referring to FIGS. 2A to 2M, one example of a cushioned layered structure is a cushioned layered structure 200, which includes a first dielectric material 12 and a conductive material 14 on the first dielectric material 12. In one example, the conductive material 14 is titanium nitride (TiN). In one particular example, the conductive material forms a coil. A second dielectric material 16 separates portions of the conductive material 14.

A TMR 201 is deposited on the conductive material 14. The TMR 201 includes a bottom TMR layer 202, a middle TMR layer 203 and a top TMR layer 204. In one example, the top TMR layer 204 and/or the bottom TMR layer 202 may include one or more layers.

In one particular example, the top TMR layer 204 may include the CoFeB layer 128 (FIG. 1). In one particular example, the middle TMR layer 203 may be the magnesium oxide (MgO) layer 126 (FIG. 1). In one particular example, the bottom TMR layer 202 may include the PtMn layer 110, the CoFe layer 114, the Ru layer 118 and the CoFeB layer 122.

A capping layer 205 may be deposited on the top TMR layer 204. In one example, the capping layer 205 may be silicon nitride. In one example, the capping layer 205 may be used as an etch-stop layer.

A first hard mask 206 is deposited on the capping layer 205. In one example, the first hard mask 206 includes silicon dioxide.

A first photoresist 207 is deposited and patterned to expose portions of the first hard mask 206. The exposed portions of the first hard mask 206 are etched.

After the first photoresist 207 is removed, the exposed portions of the capping layer 205 are etched along with the top TMR layer 204 and the middle TMR layer 203. In one example, a diameter of the top TMR layer 204 and the middle TMR layer 203 are a micron or less. In another example, a diameter of the top TMR layer 204 and the middle TMR layer 203 are a half micron or less.

A capping layer 208 is deposited on the bottom TMR layer 202 and the first hard mask 206 to protect sidewalls of the TMR pillar (i.e., sidewalls of the middle TMR layer 203 and sidewalls of the top TMR layer 204). In one example, the capping layer 208 may be silicon nitride.

A second hard mask 209 is deposited on the capping layer 208. In one example, the second hard mask 209 includes silicon dioxide.

A second photoresist 210 is deposited on the second hard mask 209 and patterned to expose portions of the second hard mask 209. The exposed portions of the second hard mask 209 are etched exposing portions of the capping layer 208. The exposed portions of the capping layer 208 are etched along with the bottom TMR layer 202 underneath.

FIGS. 2A to 2M focus on forming an electroconductive contact for one TMR for simplicity of description. However, the fabrication of the electroconductive contact may be formed for more than one TMR at the same time. For example, the FIGS. 2N to 2U depict forming an electroconductive contact for two TMR elements (the TMR element 201 and a TMR element 201′) at the same time.

Referring to FIGS. 2N to 2U, a capping layer 221 is deposited on the second hard mask 209. In one example, the capping layer 221 may be silicon nitride.

A third photoresist 222 is deposited on the capping layer 221 and patterned to expose portions of the capping layer 221. The exposed portions of the capping layer 221 are etched along with portions of the second hard mask 209 and portions of the capping layer 208.

After the third photoresist 222 is removed, a fourth photoresist 223 is deposited and patterned to expose portions of the first hard mask 206. The exposed portions of the first mask 206 are etched down to the top TMR layer 204.

After the fourth photoresist 223 is removed, a conducting material 224 is deposited on and in contact with a top surface of the top TMR layer 204 forming a device 250. The conducting material 224 forms a jumper between the two TMR elements 201, 201′. In some examples, the conducting material 224 may be aluminum, copper and/or titanium nitride.

Referring to FIG. 3, an example of a process to fabricate an electroconductive contact on a top layer of a TMR element using two masks is a process 300. In one example, process 300 may be used to form the device 250 (FIG. 2U).

Process 300 starts with a cushion layered structure (302). For example, process 300 starts with the cushion layered structure 100 (FIG. 2A).

Process 300 deposits top, middle and bottom TMR layers (306). For example, bottom TMR layer 202, middle TMR layer 203 and top TMR layer 204 are deposited on the conductive material 14 (FIG. 2B).

Optionally, process 300 may deposit a capping layer (308). For example, the capping layer 205 is deposited on the top TMR layer 204 using standard deposition techniques (FIG. 2B).

Process 300 deposits first hard mask (312). For example, the first hard mask 206 is deposited on the capping layer 205 (FIG. 2C).

Process 300 deposits a first photoresist (318) and patterns the first photoresist using photolithography to expose portions of the first hard mask (320). For example, the first photoresist 107 is patterned using standard photolithographic techniques to expose portions of the first hard mask 206 (FIG. 2D).

Process 300 etches the first hard mask (322). For example, the exposed portions of the first hard mask 206 are etched using reactive ion etching process (FIG. 2E). The capping layer 205 may be used as an etch-stop.

Process 300 strips the first photoresist (324). For example, the first photoresist 107 using standard photoresist stripping techniques (FIG. 2F).

Process 300 etches the TMR layers (326). For example, the first hard mask 206, the middle TMR layer 203, the top TMR layer 204, and the capping layer 205 are etched using ion beam etch process (FIG. 2G).

Process 300 deposits a capping layer (330). For example, the capping layer 208 is deposited on the first hard mask 206 and the bottom TMR layer 202 using standard deposition techniques (FIG. 2H).

Process 300 deposits a second hard mask (334). For example, the second hard mask 209 is deposited on the capping layer 208 (FIG. 2I).

Process 300 deposits a second photoresist (338) and patterns the second photoresist using photolithography to expose portions of the second hard mask (342). For example, the second photoresist 210 is patterned using standard photolithographic techniques to expose portions of the second hard mask (FIG. 2J).

Process 300 etches the second hard mask (346). For example, the exposed portions of the second hard mask 209 are etched using reactive ion etching process (FIG. 2K).

Process 300 strips the second photoresist (350). For example, the second photoresist 210 is removed using standard photoresist stripping techniques (FIG. 2L).

Process 300 etches a portion of the bottom TMR layer (354). For example, the bottom TMR layer 202 is etched, and the etching stops at the conductive material 14 using standard etching techniques (FIG. 2M).

Process 300 deposits a capping layer (358). For example, the capping layer 221 is deposited on the second hard mask 209 and the bottom TMR layer 202 using standard deposition techniques (FIG. 2N).

Process 300 deposits a third photoresist (362) and patterns the third photoresist using photolithography to expose portions of the capping layer (366). For example, the third photoresist 222 is patterned using standard photolithographic techniques to expose portions of the capping layer 221 (FIG. 2O).

Process 300 etches the exposed portions of the capping layer down to the first mask (370). For example, a dry etch process is used to etch the exposed portions of the capping layer 221, the (FIG. 2P).

Process 300 strips the third photoresist (374). For example, the third photoresist 222 is removed using standard photoresist stripping techniques (FIG. 2Q).

Process 300 deposits a fourth photoresist (378) and patterns the fourth photoresist using photolithography to expose portions of the first hard mask (382). For example, the fourth photoresist 223 is patterned using standard photolithographic techniques to expose portions of the first hard mask 206 (FIG. 2R).

Process 300 etches the exposed portions of the first mask down to the top TMR layer (386). For example, the exposed portions of the first hard mask 206 and the capping layer 205 underneath are etched down to the top TMR layer 204 (FIG. 2S).

Process 300 strips the fourth photoresist (392). For example, the fourth photoresist 223 is removed using standard photoresist stripping techniques (FIG. 2T).

Process 300 deposits a conducting material in contact with the TMR (396). For example, the conducting material 224 is deposited on the TMRs 201, 201′ (FIG. 2U).

The processes described herein are not limited to the specific examples described. For example, the process 300 is not limited to the specific processing order of FIG. 3. Rather, any of the processing blocks of FIG. 3 may be re-ordered, combined, or removed, performed in parallel or in serial, as necessary, to achieve the results set forth above. Also, the process 300 is not limited to TMRs having a diameter less than a micron or less than a half micron.

Having described preferred embodiments, which serve to illustrate various concepts, structures, and techniques, which are the subject of this patent, it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts, structures and techniques may be used.

Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

Claims

1. A method, comprising: depositing magnetoresistance (MR) layers of a MR element on a semiconductor structure, the MR layers comprising a top MR layer, a middle MR layer, and a bottom MR layer;depositing a first hard mask on the MR layers;depositing and patterning a first photoresist on the first hard mask using photolithography to expose portions of the first hard mask;etching the exposed portions of the first hard mask;etching a portion of the top MR layer and a portion of the middle MR layer using the first hard mask;depositing a first capping layer on the bottom MR layer and on the first hard mask;depositing a second hard mask on the first capping layer;depositing and patterning a second photoresist on the second hard mask using photolithography to expose portions of the second hard mask;etching the exposed portions of the second hard mask;etching a portion of the bottom MR layer using the second hard mask;depositing a second capping layer;depositing and patterning a third photoresist on the second capping layer using photolithography to expose portions of the second capping layer;etching the exposed portions of the second capping layer down to the first hard mask;depositing and patterning a fourth photoresist using photolithography to expose portions of the first hard mask;etching the portions of the first hard mask not covered by the fourth photoresist down to the top MR layer; anddepositing a conducting material on the top MR layer to form an electroconductive contact.

2. The method of claim 1, wherein the MR element is a tunneling magnetoresistance element.

3. The method of claim 1, wherein the MR element is a giant magnetoresistance element.

4. The method of claim 1, wherein depositing the MR layers on a semiconductor structure comprises depositing MR layers on the semiconductor structure comprising a conductive material disposed on and in contact with a dielectric.

5. The method of claim 4, wherein the conductive material forms a coil.

6. The method of claim 1, wherein etching the portion of the top MR layer and the portion of the middle MR layer using the first hard mask comprises etching the portion of the top MR layer to have a diameter of less than a micron and the portion of the middle MR layer to have a diameter of less than a micron.

7. The method of claim 1, wherein etching the portion of the top MR layer and the portion of the middle MR layer using the first hard mask comprises etching the portion of the top MR layer to have a diameter of less than a half micron and the portion of the middle MR layer to have a diameter of less than a half micron.

8. The method of claim 1, further comprising, before depositing the first hard mask, depositing a third capping layer on the top TMR layer.

9. The method of claim 8, wherein etching the portions of the first hard mask not covered by the fourth photoresist down to the top MR layer comprises etching the third capping layer.

10. The method of claim 1, wherein the MR element is a first MR element, the top MR layer is a first top MR layer, and the electroconductive contact is a first electroconductive contract, wherein depositing the conducting material comprises depositing the conducting material on a second top MR layer of a second MR element to form a second electroconductive contact.