The present disclosure relates to the fabrication of integrated circuit devices, and in particular, to a method for fabricating a Metal-Oxide Semiconductor (MOS) device using a post-linear-anneal operation.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Shallow Trench Isolation (STI) has been widely used in Metal-Oxide-Semiconductor (MOS) devices with a Critical Dimension (CD) below 0.25 um. In a conventional STI process, a silicon wafer may undergo many complicated operations to fabricate the STI structure. During these operations, stress may generally be accumulated in the active region of the silicon wafer, which may affect the electrical performance of the fabricated MOS devices.
The STI stress is mainly caused by the curvature of the silicon wafer before a trench isolation material is filled. If the STI stress cannot be reduced or eliminated, the silicon wafer cannot be restored to flatness. With this stress effect induced through the STI fabrication process, the saturation current of the fabricated NMOS and PMOS devices may drop by as much as 15% as the channel narrows, resulting in the dependency of the saturation current of the MOS devices on the channel width, which may negatively affect the driving capability of the devices.
The present disclosure provides a method for fabricating an MOS device, the method may include: depositing a silicon-nitride (SiN) layer above a substrate surface of a silicon wafer; etching one or more trenches on the silicon wafer; performing a high-temperature post-liner-anneal process on the silicon wafer to reduce stress from the etched SiN layer to the silicon wafer; and filling the one or more trenches with oxide isolation material. The high-temperature post-liner-anneal process may reduce the dependence of the saturation current of the MOS device on the channel width.
The present disclosure further provides a MOS device, the device includes one or more shallow trench isolations (STIs).
The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. These drawings depict only several embodiments in accordance with the disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and make part of this disclosure.
Throughout the disclosure, the term “semiconductor structure” may broadly refer to a physical structure constructed based on a semiconductor fabrication process. For example, a fabrication process may be a multiple-step sequence of photographic and chemical-processing operations. During the fabrication process, different electronic components may gradually be created on a semiconductor wafer using various depositions and etching operations. The fabrication process may deposit a layer of material on top of other materials, or etch/wash away material from the semiconductor structure. Throughout the disclosure, when a first layer of material is deposited “above” a second layer of material, the first layer of material may either be directly on the top of the second layer, or there might be additional material in between the first and the second layers. In other words, after the second layer of material is fabricated, additional material may be deposited on the top of the second layer before the first layer of material being deposited. Further, the term “top”, “bottom”, “above”, “below”, “up”, or “down” may be relative to one surface of a horizontally-placed silicon wafer.
In some embodiments, the pad oxide layer 113 may be formed by placing the semiconductor structure 100 through an oxidize operation at a temperature of about 850 to 1000° C. The pad oxide layer 113, which may have a thickness between about 50 and 300 Angstroms, may provide foundational support to the pad SiN layer 115. Afterward, the pad SiN layer 115 may be deposited above the pad oxide layer 113 through a chemical vapor deposition operation. The pad SiN layer 115 may have a thickness of about 1000 to 2000 angstroms.
In some embodiments, during the above trench-etching operation, mechanical stress may be introduced in the semiconductor substrate 200 near the shallow trenches 210. Specifically, during the pre-STI fabrication operation, when the pad (SiN) layer 115 is deposited on the top surface of the silicon wafer, the bottom surface of the silicon wafer may also be deposited with similar materials at the same time. Although the pad SiN layer 115 may generate internal stress, the stresses from the SiN material on both sides of the wafer may cancel each other out, resulting the wafer to remain flat.
In the subsequent trench-etching operation, the pad SiN layer 115 on the top surface of the wafer may be etched to have“islands” and “valleys”, and the SiN layer on the bottom surface of the wafer remains intact. This may cause the stresses applied to the top and bottom surface of the wafer to be in-balanced. As shown in
In some embodiments, after the depositing of the liner layer 240, the semiconductor structure 230 may undergo an active reverse-etching operation. Specifically, the reverse-etching operation may remove/etch-down the liner layer 240 to be lower than the top of the substrate 110 surface, so that the liner layer 240 may not cover the SiN layer 115 and/or the oxide layer 113.
In some embodiments, the post-liner-annealing operation may place the semiconductor structure 230 of
In some embodiments, a semiconductor fabrication system may be configured to perform some or all of the above fabrication operations and to construct one or more STIs in a wafer. The semiconductor fabrication system may include, without limitation, oxidation equipment, deposition equipment, lithographic equipment, cleaning equipment, annealing equipment, and dicing equipment. A wafer, which may be a thin slice of semiconductor material (e.g., silicon crystal), may be processed by equipment from the above system one or more times based on operation routes, product's specifications, and manufacturing recipes.
In some embodiments, the oxidization equipment may be configured to perform one or more of thermal oxidation, wet anodization, chemical vapor deposition (CVD), and/or plasma anodization or oxidation operations. The oxidation equipment may be configured to oxidize the surface of the wafer in order to form a layer of silicon dioxide. The deposition equipment may be configured to deposit a layer of specific material over the wafer. In some embodiments, the deposition equipment may deposit an oxide layer or a SiN layer above a surface of the wafer.
In some embodiments, the lithographic equipment may be configured to perform wet-etching, dry-etching, or plasma-etching operations in order to construct and/or remove portions of semiconductor layers. The cleaning equipment may be configured to rinse and clean the surface of semiconductor components after the deposition, etching, and/or dicing operations. The annealing equipment may be configured to anneal the semiconductor components by applying high-temperature heat toward the wafer. The dicing equipment may be configured to dice a fabricated silicon wafer into a diced wafer. Afterward, the silicon wafer may be cut/diced into a plurality of wafer segments, each of which may be used to construct a finished product. The wafer segments may then be packaged into a final product.
One skilled in the art will appreciate that, for this and other processes and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Furthermore, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the essence of the disclosed embodiments. Moreover, one or more of the outlined steps and operations may be performed in parallel.
At block 510, during a STI fabrication process, a pad oxide layer may be deposited above a substrate surface of a silicon wafer. At block 520, a SiN layer may be deposited above the pad oxide layer. Alternatively, the SiN layer may be deposited directly above the substrate surface of the silicon wafer without the pad oxide layer. Such an approach may reduce the process complexity and manufacturing cost.
At block 530, a photo-resistance layer may be deposited above the SiN layer. At block 540, a lithographic operation may etch one or more trenches on the silicon wafer. Specifically, the lithographic operation may etch through the photo-resistance layer to define the one or more trenches. Afterward, an etching operation may etch through the SiN layer and the substrate surface to form the one or more trenches.
At block 550, a liner layer may be formed on interior surfaces of the one or more trenches. At block 560, the fabrication process may perform a high-temperature post-liner-anneal operation on the silicon wafer to reduce stress from the etched SiN layer to the silicon wafer. Specifically, the high-temperature post-liner-anneal operation may be performed at a temperature of above 1,150 degrees Celsius for at least about 30 minutes. The post-liner-anneal operation may reduce stresses in the semiconductor substrate near the one or more trenches, thereby improving semiconductor device performance.
At block 570, the fabrication process may fill the one or more trenches with oxide isolation material. Specifically, dialectic oxide isolation material may be deposited to form an oxide isolation layer that fills the one or more trenches and covers the SiN layer. At block 580, the fabrication process may etch the oxide isolation layer until the top of the substrate surface is exposed to form one or more shallow trench isolations (STIs). The fabrication process may etch down the oxide isolation layer, the photo-resistance layer, the SiN layer, and the oxide isolation layer until reaching the top of the substrate surface to form the one or more STIs. In some embodiments, the etching of the oxide isolation layer may use a dry-etching operation or a wet-etching operation. The constructed STIs may be used in a Metal-Oxide Semiconductor (MOS) device.
Thus, multiple embodiments of a method for fabricating the MOS device have been described. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be recognized that the disclosure is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense.
One skilled in the art will appreciate that, for this and other apparatuses and methods disclosed herein, the functions performed in the processes and methods may be implemented in differing order. Furthermore, the outlined steps and operations are only provided as examples, and some of the steps and operations may be optional, combined into fewer steps and operations, or expanded into additional steps and operations without detracting from the essence of the disclosed embodiments. Moreover, one or more of the outlined steps and operations may be performed in parallel.