Patent Application
20230228828
A magnetic field sensing element is used to describe a variety of electronic elements that can sense a magnetic field. The magnetic field sensing element can be, but is not limited to, a Hall effect element, a magnetoresistance element, or a magnetotransistor. As is known, there are different types of Hall effect elements, for example, a planar Hall element, a vertical Hall element, and a Circular Vertical Hall (CVH) element. There are different types of magnetoresistance elements, for example, a semiconductor magnetoresistance element such as Indium Antimonide (InSb), a giant magnetoresistance (GMR) element, for example, a spin valve, an anisotropic magnetoresistance element (AMR), a tunneling magnetoresistance (TMR) element, and a magnetic tunnel junction (MTJ). The magnetic field sensing element may be a single element or, alternatively, may include two or more magnetic field sensing elements arranged in various configurations, e.g., a half bridge or full (Wheatstone) bridge. Depending on the device type and other application requirements, the magnetic field sensing element may be a device made of a type IV semiconductor material such as Silicon (Si) or Germanium (Ge), or a type III-V semiconductor material like Gallium-Arsenide (GaAs) or an Indium compound, e.g., Indium-Antimonide (InSb).
In one aspect, a method includes forming a coil in a coil layer, performing planarization on the coil layer, and depositing a magnetoresistance (MR) element on the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.
In another aspect, a magnetic field sensor includes a substrate, a planarized coil layer comprising a coil on the substrate, a magnetoresistance (MR) element in contact with the planarized coil layer, and a capping layer deposited over the MR element and the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.
The foregoing features may be more fully understood from the following description of the drawings. The drawings aid in explaining and understanding the disclosed technology. Since it is often impractical or impossible to illustrate and describe every possible embodiment, the provided figures depict one or more illustrative embodiments. Accordingly, the figures are not intended to limit the scope of the broad concepts, systems and techniques described herein. Like numbers in the figures denote like elements.
Described herein are techniques to fabricate a planarized coil layer, which includes a coil, that is in contact with a magnetoresistance (MR) element. In particular, there is no dielectric material between the coil layer and the MR element, which is sometimes referred to as having a gapless coil. In one example, a surface of a coil layer has been planarized using chemical mechanical polishing (CMP) so that the MR element may be directly attached to the planarized coil layer.
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As will be further described, the coil material 102 will be etched to form a coil material 102a and a coil material 102b (see, for example,
Electrical signals may be conducted through vias (not shown) to the coil 102a. In one example, the electrical signals may be used to generate a magnetic field from the coil 102a. In other examples, the coil 102a may be used to pick-up an induced electromotive force caused by a changing magnetic field received at the coil 102a.
In some embodiments, the substrate 101 does not have to support electronic circuitry, but may be, for example, a dummy substrate that only supports a magnetoresistance element. In one example, the substrate 101 may include any material suitable for supporting electronic circuitry. In some embodiments, the substrate 101 may include a semiconductor material, including but not limited to silicon, germanium, gallium arsenide, and/or other types of semiconductor materials. In other embodiments, the substrate 101 may include diamond, glass, ceramic, polymer and/or other materials. In one particular example, the substrate 101 is silicon dioxide or silicon nitride. In other examples, the substrate 101 may include both semiconductor and non-semiconductor materials.
A photoresist is deposited on the coil material 102. The photoresist is patterned using photolithography to expose regions of the coil material 102 that will be removed to define a coil. The remaining photoresist 103 protects the portions of the coil material 102 that will not be removed and not exposed.
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There is no dielectric material between the MR element 105 and the planarized coil layer 112. In one example, the MR element 105 is in direct contact with the planarized coil layer 112.
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Process 200 forms vias in a substrate (202). For example, the substrate 101 is etched to form ducts and an electroconductive material is deposited within the ducts, as depicted in
Process 200 deposits a coil (206). For example, a sputtering process used to deposit an electroconductive material (e.g., titanium nitride) on the substrate 101, as depicted in
Process 200 deposits a first photoresist (208) and process 200 patterns the first photoresist using photolithography to expose portions of the coil (212). For example, the photoresist 103 remains after photolithography, as depicted in
Process 200 etches the exposed portions of the coil (216). In one example, the coil material 102 is etched using a standard etching process that uses the photoresist 103 as a mask, as depicted in
Process 200 strips the first photoresist (222). For example, the photoresist 103 is removed using a standard photoresist stripping process, as depicted in
Process 200 deposits insulator material (226). For example, the insulator material (e.g., silicon dioxide) is deposited using a standard deposition process that completely covers the coil materials 102a, 102b, as depicted in
Process 200 etches the insulator material (232). For example, a standard etching process is used to etch the insulator material 104 down to the coil materials 102a, 102b and exposing the coil materials 102a, 102b, as depicted in
Process 200 performs planarization (238). For example, a chemical mechanical polishing (CMP) process is used to polish the coil materials 102a, 102b and the insulator material 104 together to form the planarized surface 110, as depicted in
Process 200 deposits a magnetoresistance element (242). For example, the magnetoresistance element 105 is deposited using a standard deposition process on the polarized surface 110 of the planarized coil layer 120, as depicted in
Process 200 deposits a hard mask (248). For example, a hard mask 106 (e.g., silicon dioxide) is deposited using a standard deposition process on the MR element 105, as depicted in
Process 200 deposits a second photoresist (252) and process 200 patterns the second photoresist using photolithography to expose portions of the hard mask (258). For example, a photoresist is deposited on the hard mask 106 and is patterned using standard photolithographic process leaving the remaining photoresist 107 and exposing portions of the hard mask 106, as depicted in
Process 200 etches the exposed portions of the hard mask (262). For example, the exposed portions of the mask 106 are etched using a reactive ion etch process, which expose portions of the MR element 105, as depicted in
Process 200 strips the second photoresist (268). For example, the photoresist 107 is removed using a standard photoresist stripping process, as depicted in
Process 200 etches exposed portions of the MR element (272). For example, the exposed portions of the MR element 105 are etched away using an ion beam etching process and the hard mask 106 is also eroded down, but not completely removed, as depicted in
Process 200 deposits capping layer on the coil and on the MR element (278). For example, a caping layer (e.g., silicon nitride) is deposited using a standard deposition process on the hard mask 106, the coil material 102, the insulator material 104 and sidewalls of the MR element 105 to protect the MR element 105 and the coil material 102, as depicted in
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The first spin valve 301a includes bias layers 310, free layer 314 and reference layers 316. The bias layers 310 includes an antiferromagnetic pinning layer 311 and a ferromagnetic pinned layer 312 disposed over the antiferromagnetic pinning layer 311. The first spin valve 301a also includes a nonmagnetic spacer layer 313 disposed over the ferromagnetic pinned layer 312 with the free layers 314 structure 314 disposed over the nonmagnetic spacer layer 313. The free layers 314 includes a first ferromagnetic free layer 314a and a second ferromagnetic free layer 314b disposed over the first ferromagnetic free layer 314a.
The first spin valve 301a further includes a nonmagnetic spacer layer 315 disposed over the free layers 314 with the reference layers 316 disposed over the nonmagnetic spacer layer 315. The reference layers 316 includes a ferromagnetic layer 316a, a ferromagnetic pinned layer 316c and a nonmagnetic spacer layer 316b disposed therebetween.
The second spin valve 301b, which is similar to the first spin valve 301a, but includes layers that are in a substantially reverse order or arrangement as the layers which are shown in the first spin valve 301a with respect to the seed layer 302, includes reference layers 331 disposed over the antiferromagnetic pinning layer 320, a nonmagnetic spacer layer 332 disposed over the reference layers 331 and free layers 333 disposed over the nonmagnetic spacer layer 332. The reference layers 331 includes a first ferromagnetic layer 331a, a second ferromagnetic pinned layer 331c and a nonmagnetic spacer layer 331b disposed therebetween. Additionally, the free layers 334 includes a first ferromagnetic free layer 334a and a second ferromagnetic free layer 334b disposed over the first ferromagnetic free layer 334a.
The second spin valve 301b also includes bias layers 330. The bias layer 330 includes nonmagnetic spacer layer 333 disposed over the free layers 334, a ferromagnetic pinned layer 335 disposed over the nonmagnetic spacer layer 333 and an antiferromagnetic pinning layer 336 disposed over the ferromagnetic pinned layer 335.
Each of the layers in prior art MR element 300 includes one or more respective materials (e.g., magnetic materials) and has a respective thickness, as shown. Materials of the layers are shown by atomic symbols. Additionally, thicknesses of the layers are shown in nanometers. In other embodiments, the material and thicknesses of the layers in MR element 300 may be replaced with other materials and thicknesses.
Arrows are shown that are indicative of magnetization directions of the layers. Arrows coming out of the page are indicated as dots within circles and arrows going into the page are indicated as crosses within circles.
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Metal interconnects (e.g., a metal interconnect 420a) connect to a metal layer 440a on one end and to the MR element 405a on the other end. Metal interconnects (e.g., a metal interconnect 420b) connect to a metal layer 440b on one end and to the MR element 405b on the other end. Vias (e.g., via 430a) connect the coil 402a to the metal layer 412. Vias (e.g., via 430b) connect the coil 402b to the metal layer 412.
A current flows in the metal layer 410 in a direction 426 (i.e., into the page) and causes a magnetic field in a direction 436a in the MR element 405a and a magnetic field in a direction 436b (antiparallel to the direction 436a) in the MR element 405a. The directions 436a, 436b are also orthogonal to the plane 450.
The processes described herein are not limited to the specific examples described. For example, the process 200 is not limited to the specific processing order of
Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
