FABRICATION METHOD FOR SEMICONDUCTOR INTERCONNECTIONS

Abstract

There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is view broadly illustrating one embodiment of a fabrication method for semiconductor interconnections, according to the invention;

FIG. 2 is a graph showing a relationship between an annealing temperature and an electric resistivity with reference to a specimen No. 61 in Table 4;

FIG. 3 is a graph showing a relationship between an annealing temperature and an electric resistivity with reference to specimens No. 62 to No. 64, in Table 4; and

FIG. 4 is a graph showing a relationship between an annealing temperature and an electric resistivity with reference to specimens No. 65 and No. 66, in Table 4.

Claims

1. A method for fabricating semiconductor interconnections of a Cu-alloy embedded in respective recesses provided in an insulating film on a semiconductor substrate, said method comprising the steps of: forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1;forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses; andsubsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

2. A method for fabricating semiconductor interconnections of a Cu-alloy embedded in respective recesses provided in an insulating film on a semiconductor substrate, said method comprising the steps of: forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1;forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and Dy in a range of 0.01 to 3 at % over the respective recesses; andsubsequently, annealing the Cu-alloy film to not lower than 400° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

3. A method according to claim 2, wherein the Cu-alloy film containing also N in a range of 0.4 to 2.0 at % is formed.

4. A method according to claim 1, wherein the Cu-alloy film is formed by the sputtering method under an atmosphere of an inert gas containing N2 in a range of 2.5 to 12.5 vol. %.

5. A method according to claim 3, wherein the Cu-alloy film is formed by the sputtering method under an atmosphere of an inert gas containing N2 in a range of 2.5 to 12.5 vol. %.