Patent Application
20060157732
The invention relates to the field of strained semiconductor structures on top of a strain-relaxed buffer layer, which can be applied in particular to the fabrication of integrated circuits comprising buried-channel and surface-channel strained-Si field effect transistors with a metal-oxide gate.
The beneficial role of tensile strain for enhancing the electronic properties of Si was recognized in the mid eighties by Abstreiter et al. (see Abstreiter et al., Phys. Rev. Lett. 54, 2441 (1985)), the content of which is incorporated herein by reference hereto.
Nearly 20 years of intense research on strained-Si have followed this initial discovery (see for example Schäffler, Semicond. Sci. Technol. 12, 1515 (1997), the content of which is incorporated herein by reference hereto). The most common way to impose tensile strain is by epitaxial growth. A relaxed buffer layer or virtual substrate (VS) with lattice parameter larger than that of Si is grown first, followed by the layer of strained Si. Provided that the Si layer is kept sufficiently thin, the strained-Si/VS interface remains defect-free, and the lateral lattice parameters of strained-Si and VS are equal.
In practice, an alloy layer of Si1-xGex (0<x≦1) is used to form the VS, the lattice parameter of which can be chosen to lie anywhere between that of pure Si and pure Ge, since the lattice parameter of Ge exceeds that of Si by 4.2%. In order to act as VS the alloy layer must be grown beyond its critical thickness for strain relaxation, which depends on the Ge content and the method of growth. Strain relaxation proceeds by introducing misfit dislocations at the alloy layer/substrate interface. Unfortunately, these are usually accompanied by so-called threading dislocations (TDs). The TDs reach the surface of the VS and tend to pierce any electrically active layers grown on top, thereby degrading its electrical properties (see for example Ismail et al., J. Vac. Sci. Technol. B 14, 2776 (1996), the content of which is incorporated herein by reference hereto).
In U.S. Pat. No. 5,221,413, the content of which is incorporated herein by reference hereto, Brasen et al., have described a way to reduce the TD density by successively depositing alloy layers with increasing Ge content. The concept of graded SiGe alloy layers has been explained also in a seminal paper by Fitzgerald et al. (see Fitzgerald et al., Appl. Phys. Lett. 59, 811 (1991), the content of which is incorporated herein by reference thereto).
Linearly- or step-graded SiGe VS have formed the basis for most strained-Si devices processed in the past. Strained-Si devices can be divided into two broad classes: modulation doped field effect transistors (MODFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs).
MODFETs are characterized by a selectively (also called modulation) doped buried channel and are considered among the fastest transistors available. Modulation doping has been applied first to the gallium arsenide-gallium aluminium arsenide system. There, facing layers of gallium arsenide and aluminium gallium arsenide force electrons into an essentially two-dimensional electron gas. The electrons which are restricted in this way are less susceptible to scattering because they are separated from their donor ions and can therefore move more quickly. Although consumer applications of such two dimensional devices, such as MODFETS have been somewhat limited, they are used in satellite television receivers where the frequency range of GaAs and the low-noise behaviour of modulation-doped devices come into play.
In Si technology, MOSFETs are on the other hand by far the most common field effect transistors in both digital and analogue circuits. The MOSFETs have a surface channel of n-type or p-type semiconductor material, and are accordingly called either NMOSFETs or PMOSFETs.
Surface channel MOSFETs have the advantage of a small gate to channel distance and hence efficient electrostatic control by the gate. They suffer, however, from interface scattering at the oxide/silicon interface. Buried channel devices are on the other hand characterized by reduced scattering at the smoother epitaxial interfaces at the expense of poorer gate control because of the larger gate to channel distance.
The present invention provides a means of combining the advantages of surface and buried channel devices. The potential benefits of buried-channel MOSFET devices have been described for example by Welser et al. in IEEE EI. Dev. Lett. 15, 100 (1994), the content of which is incorporated herein by reference thereto. Device performance was limited, however, due to transport through the low-mobility SiGe cap at high vertical field.
Under the influence of strain the mobility of Si channels is enhanced both for electrons and holes, leading to better transistor performance for n-channel as well as p-channel devices. Holes require, however, a larger amount of strain than electrons for the mobility to be significantly enhanced. This necessitates higher Ge content in the VS (see for example Fischetti et al., J. Appl. Phys. 80, 2234 (1994), and R. Oberhuber et al., Phys. Rev. B 58, 9941 (1998), the contents of which are incorporated herein by reference thereto).
With Si channels under tensile strain, MOSFET devices with enhanced mobility of both electrons and holes can be fabricated and combined in a CMOS circuit, as described for example in U.S. Pat. No. 6,649,480 to Fitzgerald et al., the content of which is incorporated herein by reference thereto.
Especially the mobility enhancement for holes seems, however, to be limited in this approach (see for example Leitz et al., J. Appl. Phys. 92, 3745 (2002), the content of which is incorporated herein by reference thereto). Here, higher enhancement factors can be achieved by using buried SiGe alloy channels (see for example Höck et al., Appl. Phys. Lett. 76, 3920 (2000), the content of which is incorporated herein by reference thereto).
It may therefore be advantageous to combine buried alloy channels for hole transport and Si surface channels for electron transport in a so-called dual-channel approach (see for example Badcock et al., Solid-State Electronics 46, 1925 (2002) and Lee et al., Appl. Phys. Lett. 83, 4202 (2003), the contents of which are incorporated herein by reference thereto).
For the actual fabrication of strained-Si devices, epitaxial growth techniques such as molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) are commonly used (see for example Weitz et al. Surf. Sci. 361/362, 542 (1996), and Ismail et al., Appl. Phys. Lett. 66, 1077 (1995), respectively, the contents of which are incorporated herein by reference thereto). Both methods are characterized by low throughput, especially because of low CVD growth rates at low substrate temperatures, and the large thickness required for high-quality VS growth.
A method for epitaxy, much faster than MBE and CVD, has been presented in U.S. Pat. No. 6,454,855 by von Känel et al, the content of which is incorporated herein by reference thereto. In this patent to von Känel, the application of this so-called low-energy plasma-enhanced chemical vapor deposition (LEPECVD) technique was restricted to coherent, defect-free epitaxial interfaces (see also Rosenblad et al., J. Vac. Sci. Technol. A 16, 2785 (1998), the content of which is incorporated herein by reference thereto). The application of LEPECVD to the fabrication of relaxed graded VS has been described for example in the European Patent Application Nr. EP 1 315 199 to von Känel and in U.S. patent application No. U.S. 60/565,205, the contents of which are incorporated herein by reference thereto.
Application of LEPECVD to the fabrication of highly relaxed VS comprising a constant composition SiGe alloy layer without the use of any graded layer has been described for example by in the International Patent Application No. PCT/EP03/03136 to von Känel and by Chrastina et al., J. Cryst. Growth 281, 281 (2005), the contents of which are incorporated herein by reference thereto.
The advantages of applying LEPECVD to the fabrication of relaxed SiGe VS for MODFETs with a buried modulation doped Si channel were described for example in Appl. Phys. Lett. 76, 427 (2000) by Rosenblad et al., the content of which is incorporated herein by reference thereto.
For selectively doped buried channels the need to keep the gate to channel distance short, and the need to limit dopant diffusion and segregation during high temperature anneals, provide additional hurdles to epitaxial growth and subsequent device processing. For simpler Schottky-gated devices, excellent results have been achieved by growing the VS by LEPECVD and the active layer stack by MBE (see for example von Känel et al. in U.S. patent application No. U.S. 60/565,205, and Enciso-Aquilar et al., Electronics Letters 39, 149 (2003), the content of which is incorporated herein by reference thereto).
It is an object of the present invention to provide a method by which the higher demands of MOSFET processing can be met.
A method of fabricating semiconductor heterostructures including the steps of: (a) positioning a silicon wafer in a suitable environment and (b) further processing the silicon substrate by applying several processing steps A first optional processing step includes growing an epitaxial graded buffer layer onto the silicon substrate by low-energy plasma-enhanced chemical vapor deposition (LEPECVD). A second processing step includes growing an epitaxial strain-relaxed constant composition buffer layer by LEPECVD. A third processing step includes subjecting the surface of the strain-relaxed buffer layer to a deposition process for a period of time and under prescribed conditions, in order to grow at least one additional layer.
The present invention provides a method for the fast growth of heterostructures comprising a strain relaxed buffer layer on Si substrates (virtual substrate, VS) with an active layer stack on top. The structures are especially suitable for the fabrication of integrated circuits based on buried-channel strained-Si field effect transistors.
It is another object of the invention to provide the necessary steps for the processing of modulation-doped field effect transistors with a metal-oxide gate (MOSMODFET).
It is another object of the invention to provide a method for performance gain of buried-channel strained-Si FETs through non-standard processing.
It is another object of the invention to provide a method for producing buried strained-Si electron and strained-SiGe hole channels for complementary CMOSFETs.
It is another object of the invention to provide a method for producing buried alloy channels combined with strained-Si surface channels for CMOSFETs.
Referring now to
(1) Buried Si Channel Device for N-Type MOSMODFETs
Referring now to
In a first embodiment of the invention, preferably for Ge contents below x=0.3, the substrate temperature is kept constant during growth of layers 20 and 30. The substrate temperature is chosen such as to guarantee nearly complete relaxation of the buffer layer. For temperatures above 700° C. this has been shown to be the case.
In another embodiment of the invention, the substrate temperature is kept constant only during part of the growth of layer 20 up to approximately x=0.3, whereupon it is lowered in proportion to the Ge content. This has the advantage of lowering the surface roughness and threading dislocation (TD) density. For example for xf=0.4 a final temperature of 540° C. was found to result in a TD density below 2×105 cm−2.
In another embodiment of the invention, the graded part 20 of the VS is omitted. In this case strain-relaxed layer 30 is grown directly on the silicon substrate preferably to a minimum thickness of 100 nm in the temperature range between 500° C. and 600° C. by using a high-density plasma, whereby a growth rate of several nm/s can be achieved. Layer 30 may be subjected to post-growth annealing at a temperature below 1000° C. for a period of time of about 5 min in order to increase the degree of strain relaxation.
In a preferred embodiment of the invention, the buffer layers 20 and 30 are doped during growth. For n-channel devices, p-type doping must be used, for example by boron or gallium impurities, preferably introduced at a density of about 5×1017 cm−3. In this embodiment, a thin undoped layer 100 is subsequently grown at a lower rate of preferably less than 0.5 nm/s by using a plasma of lower density. The substrate 10 on the other hand is high resistive p-doped.
In another embodiment, only the substrate 10 is p-doped, while the buffer layers 20 and 30 are not intentionally doped. In this case, layer 100 is optional.
In a preferred embodiment of the invention, the Ge content x of layers 100, 120, and 130 is chosen to be slightly higher than that of layer 30 in order to provide some compensation of the tensile strain imposed by the channel 110 and the Si cap layer 140.
The strained-Si channel 110 is grown at a low rate for example of 0.3 nm/s by using a low-density plasma and reduced reactive gas flow, and at a substrate temperature preferably above 500° C. Similar parameters may be used for the rest of the active layer stack 120-140. The thickness of the Si channel is chosen in accordance with the final Ge content xf. For xf=0.3 a thickness of 8 nm has been found to be adequate. During channel growth, a surplus of hydrogen may be added to the reactive gas flow in order to minimize the effect of Ge segregation.
The undoped alloy spacer layer 120 is grown to a thickness preferably of 4-5 nm. The doping supply layer 130 should be very thin and highly doped. A thickness of 3 nm and a doping level of at least 3×1018 cm−3 have been shown to yield good results.
In a preferred embodiment of the invention, doping at a level above 3×1018 cm−3 can be achieved by LEPECVD by lowering the substrate temperature to below 500° C., preferably to about 400° C. The plasma density is preferably kept lower by about a factor of ten with respect to that employed during growth of layers 20 and 30. A hydrogen flow of at least 5 sccm (standard cubic centimeters per minute) is added to the reactive gas mixture. This has been shown to be effective in suppressing dopant segregation to the surface.
Doping can be achieved for example by a flow of phosphine, preferably diluted with an inert gas.
The layer stack is completed by an undoped strained-Si cap 140 of a preferable thickness of not less than 2 nm and not more than 5 nm, for protection of the SiGe layers.
In another embodiment of the invention the stack of layers 100-140 is grown by an alternate deposition method, such as molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) in a separate deposition chamber.
(2) Buried Si-Channel on Top of SiGe-Channel Device for Complementary CMOSMODFETs
Referring now to
In another embodiment of the invention, the graded part 20 of the VS is omitted. In this case, strain-relaxed layer 30 is grown directly on the Si substrate preferably to a minimum thickness of 100 nm in the temperature range between 500° C. and 600° C. by using a high-density plasma, whereby a growth rate of several nm/s can be achieved. Layer 30 is preferably n doped to a level not less than 2×1017 cm−3 to act as p-channel punch-through stopper. Layer 30 may be subjected to post-growth annealing at a temperature below 1000° C. for a period of time of about 5 min in order to increase the degree of strain relaxation.
An undoped layer 100 with a Ge content of x≦xf and a preferable thickness of 20 to 60 nm is subsequently grown at a lower rate of preferably less than 0.5 nm/s by using a plasma of lower density. This layer can be designed to serve both as a strain compensating and carrier-depletion absorb layer. The substrate temperature is lowered to about 450° C. during growth of layer 100.
An undoped strained-Si1-yGey layer 101 with a Ge content of at least y=xf+0.2 is grown at a low rate by using a low-density plasma and reduced reactive gas flows. The thickness of layer 101 is chosen to be about 8 nm. A hydrogen flow of at least 5 sccm is added to the reactive gas mixture. This has been shown to prevent buckling of the compressively strained Si1-yGey channel 101.
An undoped spacer layer 102 with a Ge content of x≦xf and a thickness of about 4-5 nm is grown at a low rate. It may again act as a strain-compensating layer. Here, additional hydrogen is preferably used to prevent Ge segregation. During growth of layer 102, the substrate temperature may again be raised to above 500° C.
A very thin, preferably 3 nm, highly p-type doped layer 103 with a Ge content of x≦xf is grown at a low rate to act as a p-type carrier supply layer and a punch-through stopper for the above lying n-channel strained-Si layers. In a preferred embodiment of the invention, doping of layer 103 at a level above 3×1018 cm−3 can be achieved by LEPECVD by lowering the substrate temperature to below 500° C., preferably to about 400° C. The plasma density is preferably kept lower by about a factor of ten with respect to that employed during growth of layers 20 and 30. A hydrogen flow of at least 5 sccm is added to the reactive gas mixture. This has been shown to be effective in suppressing dopant segregation to the surface. Doping can be achieved for example by a flow of boron, preferably diluted with an inert gas.
It is a preferred embodiment of the invention, to introduce a strained-Si etch stop layer 104 to facilitate removal of the top 5 layers for p-MOS processing, a preferred thickness of layer 104 is 5-10 nm.
It is a preferred embodiment of the invention, to introduce an undoped layer 109 with a Ge content of x≦xf and a preferable thickness of 40 to 60 nm, this layer 109 is grown at a lower rate of preferably less than 0.5 nm/s by using a plasma of lower density. This layer can be designed to serve both as a strain compensating and carrier-depletion absorption layer. It furthermore anticipates a parasitic parallel conduction in the n-type doped layers 20 and 30 via the n-type contact implantation described below. The substrate temperature is lowered to about 450° C. during growth of layer 109.
In another embodiment, the Ge content x of layer 109 is chosen to be slightly above that of layer 30, x≧xf. This is preferable when the tensile strain imposed by layers 104, 110 and 140 becomes too large to be compensated by the compressively strained Si1-yGey channel 101. The resulting strain of the entire heterostructure may be tuned to near zero through proper choice of Ge content of layer 109. Furthermore, a higher Ge content of layer 109 will improve the efficacy of layer 104 as an etch stop layer because of enhanced selectivity.
The strained-Si channel 110 is grown at a low rate for example of 0.3 nm/s by using a low-density plasma and reduced reactive gas flow, and at a substrate temperature preferably above 500° C. Similar parameters may be used for the rest of the active layer stack 120-140. The thickness of layer 110 is chosen to be equal or less than 8 nm. During channel growth, a surplus of hydrogen may be added to the reactive gas flow in order to minimize the effect of Ge segregation.
The undoped alloy spacer layer 120 is grown to a thickness of preferably 4-5 nm.
The doping supply layer 130 should be very thin and highly doped. A thickness of 3 nm and a doping level of at least 3×1018 cm−3 have been shown to yield good results. The Ge content of layers 120 and 130 is preferably chosen to be close to xf.
In a preferred embodiment of the invention, doping of layer 130 at a level above 3×1018 cm−3 can be achieved by LEPECVD by lowering the substrate temperature to below 500° C., preferably to about 400° C. The plasma density is preferably kept lower by about a factor of ten with respect to that employed during growth of layers 20 and 30. A hydrogen flow of at least 5 sccm is added to the reactive gas mixture. This has been shown to be effective in suppressing dopant segregation to the surface.
Doping can be achieved for example by a flow of phosphine, preferably diluted with an inert gas.
The layer stack is completed by an undoped strained Si cap 140 of not less than 2 nm and of not more than 5 nm.
In another embodiment of the invention the stack of layers 100-140 is grown by an alternate deposition method, such as molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) in a separate deposition chamber.
(3) Si Surface Channel on Top of Buried SiGe-Channel Device for Complementary CMOSFETs
Referring now to
In another embodiment of the invention, the graded part 20 of the VS is omitted. In this case, strain-relaxed layer 30 is grown preferably to a minimum thickness of 100 nm in the temperature range between 500° C. and 600° C. by using a high-density plasma, whereby a growth rate of several nm/s can be achieved. Layer 30 is preferably n doped to a level around 1017 cm−3. Layer 30 may be subjected to post-growth annealing at a temperature below 1000° C. for a period of time of about 5 min in order to increase the degree of strain relaxation.
An undoped layer 100 with a Ge content of x≦xf and a preferable thickness of 50 to 100 nm is subsequently grown at a lower rate of preferably less than 0.5 nm/s by using a plasma of lower density. This layer can be designed to serve both as carrier-depletion absorption layer and as a means to simplify the processing complexity by allowing less stringent control of ohmic contact implantation depths. The substrate temperature is lowered to about 450° C. during growth of layer 100.
The undoped strained Si1-yGey channel layer 101 with a Ge content y exceeding xf by at least 0.2 is grown at a low rate by using a low-density plasma and reduced reactive gas flows. Before growth of the channel 101, the substrate temperature is lowered to approximately 450° C. The thickness of layer 101 is chosen to be below or slightly above the critical thickness for strain relaxation. A hydrogen flow of at least 5 sccm is added to the reactive gas mixture. This has been shown to prevent buckling of the compressively strained Si1-yGey channel 101. An undoped Si surface channel 110 is finally grown at a low rate for example of 0.3 nm/s by using a low-density plasma and reduced reactive gas flow, and at a substrate temperature preferably above 500° C. After initiation of Si channel growth, the hydrogen flow is preferably stopped. The preferable minimum thickness of the strained-Si channel is 5 nm.
In another embodiment of the invention the stack of layers 100-110 is grown by an alternate deposition method, such as molecular beam epitaxy (MBE) or chemical vapor deposition (CVD) in a separate deposition chamber.
(4) Device Processing and Characterization
Referring now to
In the preferred embodiment of the invention, the alloy spacer layer 120 and the doping supply layer 130 were chosen to be 5 and 3 nm thin, respectively, in order to keep the distance between gate and channel small and hence to facilitate a high transconductance of the device.
Further, the protective Si cap layer should be removed as completely as possible, using a 20 s HF dip followed by a selective tetramethylammonium hydroxide ((CH3) 4NOH-TMAH) etch.
In addition to standard CMOS processes a number of non-standard CMOS processes have been employed for device fabrication.
Referring now to
In a second non-standard CMOS process step, RCA2 (ULSI Technology, C. Y. Chang and S. M. Sze, Mc Graw-Hill International Editions (1996), the contents of which are incorporated herein by reference thereto) is executed to clean after layer 140 has been removed. This step avoids deterioration of the SiGe supply layer.
In a third non-standard CMOS process step, deposition of a gate insulator takes place at low-temperature, preferably below 400° C., this being an object of the invention. In the embodiment of the invention, a low-temperature LPCVD SiO2 is deposited at 400° C. This step three avoids dopant segregation. In the embodiment of the invention, a 20 nm thick SiO2 is deposited for low leakage current and high homogeneity. In a preferred embodiment of the invention, an in-situ doped n-type polySi gate electrode layer has to be deposited using low-temperature LPCVD to avoid the necessity for high thermal anneals.
In a fourth non-standard CMOS process step, the Ohmic contact implantations are annealed at low temperatures of preferably 600° C. In a preferred embodiment of the invention, a RTA anneal at 600° C. for 60 s is employed. This approach has been shown to give acceptable contact resistance values around 1.2 Ωmm. It is a preferred embodiment of the invention to have 1 anneal step only for all implantations in double channel devices (see
Referring now to
For the buried-channel strained-Si MOSMODFET, the maximum intrinsic transconductance as a function of the gate length is compared in Erreur ! Source du renvoi introuvable. with the results of the control bulk-Si MOSFET, processed according to the process steps as defined by the invention. The intrinsic transconductance for the buried-channel strained-Si FET shows an improvement of around 50% with respect to that of the bulk-Si control.
Referring again to
Referring again to
In an advantage, a method is provided for fabricating buried channel field effect transistors with metal-oxide gates which combine the advantages of modulation-doped heterostructures and MOSFET processing.
In another advantage, a method for the fast growth of heterostructures is provided comprising a strain relaxed buffer layer on Si substrates (virtual substrate, VS) with an active layer stack on top. The structures are especially suitable for the fabrication of integrated circuits based on buried-channel strained-Si field effect transistors.
It is an object of the invention to provide the necessary steps for the processing of modulation-doped field effect transistors with a metal-oxide gate (MOSMODFET).
It is another object of the invention to provide a method for performance gain of buried-channel strained-Si FETs through non-standard processing.
It is another object of the invention to provide a method for producing buried strained-Si electron and strained-SiGe hole channels for complementary CMOSFETs.
It is another object of the invention to provide a method for producing buried alloy channels combined with strained-Si surface channels for CMOSFETs. Multiple variations and modifications are possible in the embodiments of the invention described here. Although certain illustrative embodiments of the invention have been shown and described here, a wide range of modifications, changes, and substitutions is contemplated in the foregoing disclosure. In some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the foregoing description be construed broadly and understood as being given by way of illustration and example only, the spirit and scope of the invention being limited only by the appended claims.
| Number | Date | Country | |
|---|---|---|---|
| 60625952 | Nov 2004 | US |
