The present invention is directed to memory fault diagnosis in a memory built-in self-test environment. Aspects of the invention have particular applicability to the collection and analysis of test data so as to provide for continuous at-speed testing of embedded memory in integrated circuit devices.
Embedded memories are often parts of many integrated circuit devices. For example, System-on-a-Chip (SoC) devices typically contain a number of embedded memory systems. The embedded memory systems include a set of memory cells, which are components capable of retaining a state, typically characterized by a high voltage value or a low voltage value that can represent a binary digit (bit) of 0 or 1, respectively. The memory cells are arranged in an embedded memory in the form of an array, often specified in terms of a row and a column. Data lines can apply or read the voltage values on specified cells to store or retrieve a bit value, respectively. Memory cells are furthermore typically arranged into words, that is, a fixed number of cells that are addressed simultaneously as a single unit.
Every row consists of W words, each B bits long, with R rows in all. Consecutive bits belonging to one word can be either placed one after another or be interleaved forming segments 105, as illustrated in
Recently, a rapid increase in the chip area occupied by memory arrays has been observed. Following this trend, the International Technology Roadmap for Semiconductors predicts that memories will take up more than 90% of the silicon area of some chips within the decade. Due to their extremely large scale of integration, memory arrays have already started introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in test strategies. Indeed, many types of failures, such as time-related or complex read faults, often not seen earlier, originate in the highest density areas of semiconductor chips. Thus, the capability to test current and future embedded memory systems is even more important than in previous generations of embedded memory systems.
In contrast to stand-alone memory units, however, embedded memory systems are more difficult to test and diagnose. This difficulty arises not only because of the more complex structure of embedded memories, but also because of the decreasing number of inputs and outputs available to access and control these circuits, resulting in a reduced bandwidth of test channels. Memory built-in self-test (MBIST) has become a desirable solution for performing high quality testing. Among the reasons that MBIST typically is a desirable option are the following: (1) embedded memory comprises regular structures that do not require application of sophisticated test patterns, so test stimuli and expected test responses can be generated, compressed, and stored by a relatively simple testing circuitry that incurs small hardware overhead; (2) a reduced number of input/output channels usually suffice to control the necessary BIST operations such as activation, scan-in, scan-out, and others; and (3) the entire test logic can be located on-chip, which enables testing to be performed at-speed thus allowing detection of time-related faults. One implementation of memory BIST testing is described in U.S. Pat. No. 6,421,794, “Method and Apparatus for Diagnosing Memory Using Self-Testing Circuits,” John T. Chen and Janusz Rajski, issued Jul. 16, 2002, which is hereby incorporated herein by reference in its entirety.
Although certain MBIST controllers are designed as hardwired finite state machines (FSM), some flexibility usually is desired. Consequently, many MBIST implementations are programmable (micro-coded) devices. Such circuits can be conveniently programmed to meet challenges of up-to-date embedded memory structures.
Fault diagnosis for embedded memories, known as built-in self-diagnosis (BISD), typically involves certain modifications in a conventional MBIST flow aimed mainly at determining incorrect test responses (sometimes generally referred to as failing patterns), that can indicate faulty memory cells, faulty memory array columns, or faulty memory array rows. The process of identifying failing sites of a memory array can be performed either on chip or, alternatively, off line, for example in automatic test equipment (ATE), or another diagnostic tool, after downloading compressed test responses (sometimes referred to as “signatures”) from a chip. Signatures corresponding to incorrect test responses, whether compressed or not, may be referred to herein as “failing signatures.” Fault diagnosis is carried out mainly to “repair” faulty memory arrays by replacing faulty rows or columns with spare ones in a built-in self-repair (BISR) process. Fault diagnosis is also carried out to facilitate modifying an existing fabrication process, for example, to improve future manufacturing yield.
In order to test a memory circuit for time-related faults, it is desirable to perform testing “at-speed,” that is, at the rated functional speed of the memory circuit. However, relatively low bandwidth at the I/O channels of the integrated circuit device can make it difficult or impossible to quickly download failing signatures or address locations of failing sites of the embedded memory. This problem grows in significance when another fault is detected while downloading previously obtained diagnostic data. Consequently, many BIST schemes modified to test memory circuits employ either a “pause and resume” mode of operation or a “stop and restart” mode of operation.
In a “pause and resume” mode, if there is, for example, only a single register to store the incorrect test response, the BIST controller goes into a hold mode when a failure is encountered. Once the incorrect test response is scanned out from the single register to the ATE, the BIST controller resumes its operations. In some BIST schemes, multiple registers are provided to store multiple incorrect test responses. When this is the case, the BIST controller can continue to test while encountering failures, until the registers are filled. The BIST controller then enters the hold mode until the contents of all the failure storage registers have been completely scanned out, and subsequently resumes its testing operations.
In a “stop and restart” mode, the BIST controller moves to an initial test state once a fault is detected, and the corresponding diagnostic data is scanned out. The rationale is that the BIST controller could otherwise miss timing related defects between the address where a fault was most recently detected and the next target location (where the BIST controller could resume its operations). In successive repetitions the BIST controller does not monitor the memory output until the address of the most recently detected fault is passed.
It is worth noting that certain single faults may produce large amounts of diagnostic data. For example, a failure in just one signal line or “interconnect” could result in an entire row or column of the memory array working incorrectly, producing a great deal of erroneous data. Hence, there are two primary concerns regarding a high volume of diagnosis data with respect to conventional memory BIST. First of all, it may take a significant amount of time to scan the data out. Second, the ATE memory may get filled up very quickly, especially if all memory failures are being recorded. Thus, either the data has to be truncated, or the memory BIST controller has to stop so that the ATE memory can be unloaded. Truncation of data is typically not acceptable from a diagnostic point of view. Indeed, all of the diagnostic data usually is needed to analyze failures to decide whether a given memory is repairable. Also, a lengthy unloading of the ATE memory is often unacceptable due to time constraints.
Various aspects of the invention relate to techniques and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an ATE along with memory location information. A diagnostic tool may receive the compacted test response signatures and memory location information from the ATE. Then, using the memory location information, the diagnostic tool may select an appropriate diagnostic procedure for a compacted test response signature to provide very time-efficient off-line routines to safely recover failure data from the compacted test response signatures.
According to various implementations of the invention, an integrated circuit with embedded memory and a memory BIST controller also includes a linear feedback structure for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. The linear feedback structure may be, for example, a linear feedback shift register. In various implementations, the integrated circuit may also include a failing words counter, a failing column indicator, and/or a failing row indicator. The failing words counter, failing column indicator, and failing row indicator collect memory location information whenever the linear feedback structure compacts a failing test response. With these implementations, on-chip compression of diagnostic data, that is, test response data and location data, reduces the time to transfer the diagnostic data to the ATE.
According to various other implementations of the invention, a diagnostic tool receives the diagnostic data from the ATE, and selects an appropriate diagnostic technique by using a lookup table. The values stored by the failing words counter, the failing column indicator, and the failing row indicator may serve as indices for the look-up table. Moreover, the diagnostic tool may employ additional look-up tables to speed up extraction of diagnostic data from the compressed test responses. In this way, time to test and amount of test data provided to the ATE and received by the diagnostic tool from the ATE can be significantly reduced. These and other features and aspects of the invention will be apparent upon consideration of the following detailed description.
a and
As discussed in more detail below, various implementations of the invention are related to embedded memory circuit fault diagnosis in a memory BIST environment. First, a brief overview of test and diagnostic flow in a memory BIST environment is presented. Next, an embodiment of an integrated circuit device having embedded memory and a memory BIST controller with additional components to support at-speed testing is discussed, along with an embodiment of a method of operation. Various implementations of a signature register that can receive and compact test response signatures are presented. Further components, namely, a failing words counter, a failing row indicator, and a failing column indicator, are also discussed in detail, along with logic components that support the collection of memory location information and provide for on-chip compression of memory test failure data.
Following the discussion of the integrated circuit device, the embodiment of a method of operation of the disclosed integrated circuit device is discussed in more detail. This discussion shows how the aforementioned components work together in various implementations to achieve the results of continuing at-speed memory built-in self-test operations, even in the presence of multiple time related memory test failures. This discussion also shows how the components work together in various implementations to compress the diagnostic data volume, that is, test response data and location data, in order to reduce the time to transfer the diagnostic data to an automatic test equipment device.
Following that, details of an embodiment of a method of diagnosing test response signatures are presented. In particular, a look-up table of diagnostic failing test patterns will be presented, with some examples of diagnosis. The discussion also includes details of additional lookup tables and calculations to ascertain memory addresses of failing cells using a linear feedback structure. Finally, a diagnostic tool that can carry out an embodiment of a method of diagnosing test response signatures is discussed.
The embodiments of electronic circuit testing techniques and associated apparatus disclosed below are representative and should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed methods, apparatus, and equivalents thereof, alone and in various combinations and subcombinations with one another. The disclosed technology is not limited to any specific aspect or feature, or combination thereof, nor do the disclosed methods and apparatus require that any one or more specific advantages be present or problems be solved.
As used in this application, the singular forms “a,” “an” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “is made up of” without implying that no other elements can be present. Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections and indirect connections through one or more intermediate elements not affecting the intended operation of the circuit.
Although the operations of some of the disclosed methods and apparatus are described in a particular sequential order for convenient presentation, it should be understood that this description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed methods and apparatus can be used in conjunction with other methods and apparatus. Additionally, the description sometimes uses terms like “determine” and “select” to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation, but are readily discernible by one of ordinary skill in the art.
Various embodiments of the invention can be implemented in, for example, a wide variety of integrated circuits having embedded memories (for example, application-specific integrated circuits (ASICs) (including mixed-signals ASICs), systems-on-a-chip (SoCs), or programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs)).
Further, any of the disclosed devices can be stored as circuit design information on one or more computer-readable media. For example, one or more data structures containing design information (for example, a netlist, HDL file, or GDSII file) can be created (or updated) and stored to include design information describing any of the disclosed apparatus. Such data structures can be created (or updated) and stored at a local computer or over a network (for example, by a server computer). Such computer readable media are considered to be within the scope of the disclosed technologies.
In addition, one or more aspects of the invention may be embodied by the execution of software instructions on a programmable computing device to perform one or more functions according to the invention. Alternately or additionally, one or more aspects of the invention may be embodied by computer-executable software instructions stored on a computer-readable medium for performing one or more functions according to the invention.
Moreover, any of the disclosed methods can be used in a computer simulation or other EDA environment, wherein test patterns, test responses, and diagnostic results are determined by or otherwise analyzed using representations of circuits, which are stored on one or more computer-readable media. For presentation purposes, however, the present disclosure sometimes refers to a representation of a circuit or a circuit component by its physical counterpart (for example, memory array, counter, register, logic gate, or other such term). It should be understood, however, that any reference in the disclosure to a physical component includes representations of such circuit components as are used in simulation or other such EDA environments.
In a representative memory test and diagnostic flow, a comprehensive test, sometimes referred to as a “march” test, is typically used to check a memory array for defects. A march test is a sequence of test steps applied to each memory address in turn. Each test step typically consists of at least one write and/or read operation. In a description of a march test, as shown, for example, in the top line of Table 1, each test step is denoted by an expression in parentheses that specifies the operations performed in the test step. Each test step is separated by a semicolon from its successor. Moreover, in the expression of a test step, an arrow specifies the order in which memory is accessed in the test step. A test step may access memory in order of ascending addresses, denoted by an upward arrow , or in order of descending addresses, denoted by a downward arrow .
The march test of Table 1 consists of an initialization step, denoted (w0), in which a “data background” word, denoted by “0,” is written to each memory word address in ascending order. The data background word may be a bit pattern consisting entirely of zeroes, entirely of ones, or may be some combination of both, for example, 00110011 for a particular 8-bit word. Conversely, a “1” signifies an inverse from the data background pattern, for example, a word consisting entirely of ones when the data background word consists entirely of zeroes, or in the other example above, consisting of 11001100 when the data background word is 00110011. For definiteness, in the following discussion, unless otherwise specified the data background word is a bit pattern consisting entirely of B zeroes, and the inverse word from the data background word is a bit pattern consisting entirely of B ones. Accordingly, the quotation marks around 0 and 1 are omitted below.
The initialization step is followed by a test step, (r0, w1), in which a target memory is accessed in ascending address order. In the test step, two operations are performed in sequence on each memory address. In the first operation, (r0), a memory word is read. The 0 following the r indicates that the correct test response is the data background word, that is, 000 . . . 0, and any other response is an incorrect response. In the second operation (w1), the inverse word, that is, 111 . . . 1, is written to the memory word. Both of these operations are performed at a particular address before the test step advances to the next memory address.
In the subsequent test step, (r1, w0), the target memory is again accessed in ascending address order. In this test step, two operations are performed in sequence on each memory address. In the first operation, (r1), a memory word is read. The 1 following the r indicates that the correct test response is the inverse word from the data background word, that is, 111 . . . 1, and any other response is an incorrect response. In the second operation (w0), the data background word, 000 . . . 0, is written to the memory word. Both of these operations are performed at a particular address before the test step advances to the next memory address.
The fourth test step, (r0, w1), differs from the second test step, (r0, w1), only in the order of memory access, in that the target memory is accessed in descending address order. Similarly, the fifth test step, (r1, w0), differs from the third test step, (r1, w0), only in that here too, the target memory is addressed in descending order.
(w0);
(r0,
(r1,
(r0,
(r1,
March tests can be used to detect a variety of types of failures in memory arrays. Table 1 is a fault dictionary which correlates errors that may be observed by the march test with possible causes for the observed errors.
In general, a fault dictionary is a table in which the rows are labeled by faults, and the columns are labeled by operations of test steps. The table contains a 1 in a table cell corresponding to a particular fault and a particular test step operation if the test step operation detects the fault. Otherwise, if the test step operation does not detect the fault, the table cell contains a 0. For example, the columns under the write operations in Table 1 are filled with 0s since a write operation does not detect faults.
A fault dictionary can be created based, for example, on an analysis of the memory circuit, on simulation, or on experiment. The faults listed in the first column of Table 1 include, for example, a “stuck-at-0” fault, SAF0, and a “stuck-at-1” fault, SAF1. TF0 and TF1 are transition faults, and faults whose denotations begin with CF are coupling faults. Faults denoted SOF0, SOF1, and SOF2 are stuck-open faults. The AF0 and AF1 faults are address decoder faults. Thus, for example, SAF0 may be diagnosed when, in a test step, after 111 . . . 1 is written to a word address, any bit pattern that includes a 0 is read from that word address.
One application of memory failure diagnosis is the construction of two-dimensional pictures (bitmaps) corresponding to a memory array. The construction process uses memory test responses to select a value for each bitmap pixel, so that each pixel represents the status (that is, good or failing) of one memory cell. In monochrome bitmaps, white pixels indicate good cells while black pixels indicate failing sites of a memory array. These bitmaps naturally abstract from specific classes of fault types, for example, stuck-at faults, providing only the basic information of whether a cell was good or not given a read operation.
Color bitmaps, on the other hand, can have different pixel colors representing different classes of faults. For example, stuck-at faults may be represented by one color, and transition faults by a different color. A color bitmap can be obtained, for example, after applying a suite of march tests, with different test steps and/or data backgrounds in each march test, in a BIST mode. Color bitmaps can in addition or alternatively be obtained during off-line post processing of a set of monochrome bitmaps representing the same copy of a memory array. In certain embodiments, a fault dictionary can be used (see, e.g., Table 1) to help in creating color error bitmaps of memory arrays. Such a dictionary summarizes the results of a reasoning process which is based on a specific march test routine. Examples of dictionaries and dictionary generation methods as may be used with the disclosed technology are described in L.-T. Wang, C.-W. Wu, X. Wen, “VLSI Test Principles and Architectures. Design for Testability,” Morgan Kaufmann Publishers, New York, 2006. It should be understood that memory tests other than march tests can be applied in a memory BIST environment, for example, Galpat, Walking, Butterfly, Sliding diagonal, NPSF, and other tests. There are hundreds of variations of algorithms that have been proposed. Testing algorithms are described in A. J. van de Goor, “Testing Semiconductor Memories: Theory and Practice,” John Wiley & Sons Inc., New York, 1998, and in R. Dean Adams, “High Performance Memory Testing: Design Principles, Fault Modeling, and Self-test,” Springer, N.Y., 2002. It should be understood that use of the methods and devices described herein with memory tests other than march tests is within the scope of this disclosure.
Integrated Circuit Device with Temporal Compaction
In various embodiments, fault diagnosis can produce very accurate monochrome error bitmaps that show the failing memory cells. For example,
While a particular example of an integrated circuit device 207 with only a single embedded memory array 204 and a single MBIST controller 206 is discussed below, it will be appreciated that the integrated circuit device 207 can have multiple embedded memories, and can have multiple memory BIST controllers so that each of the memory BIST controllers can test several embedded memories. The embedded memory array 204 may have a memory architecture such as that shown above in
In an initialization step 323, the method begins at the first test step, for example, of a march test such as the march test shown in the top line of Table 1. The memory BIST controller 206 (see
The BIST controller 206 (see
When a read operation is carried out, a test response word may be captured 327. Concurrently, the memory BIST controller 206 (see
Following operation 329 of the comparator 209 (see
Thus, a resultant difference shown by the output of the comparator 209 (see
Following step 331, the BIST controller 206 (see
In various embodiments, the transfer 334 of test data may be facilitated by the use of “shadow registers.” In the embodiment illustrated in
In various embodiments in which shadow registers are used, the test data collectors 210, 211, 213, and 214 (see
Continuing with the discussion of various components of
In the initial state, therefore, the signature register's contents are in a specified non-zero state, signifying that no errors have been compacted. It should be understood that any “seed” other than zero can be loaded into the signature register to establish an initial state. The signature register employs sequential logic—rather than only combinational logic—so that test response signatures output by the comparator 209 presented to the signature register by the outputs of the comparator are sequentially stored in states of the signature register 210, that is, temporally compacted. The content of the signature register 210 is periodically unloaded—for example, once per test step—so that errors detected in a test step can be identified and diagnosed. The content of the signature register 210 indicates whether failures in the memory array were detected.
In some embodiments, the signature register 210 (see
Some of the latches 438 in the MIRG are connected so as to receive input from a logic network (XOR or XNOR, for example) rather than directly from another latch, in order to implement performance identical to the associated “canonical” linear feedback shift register. In addition, some of the XOR or XNOR networks 438 are configured as an “injector” network 439. An injector operates to receive input external to the MIRG, or to provide output from the MIRG. In
Continuing with discussion of the integrated circuit device 207 (see
In general, any counting device can be used to act as the FWC 211 (see
As shown in the embodiment of
In some embodiments, the content of the FCI 213 (see
Returning to
The circuit of
As mentioned previously, various embodiments of the disclosed technology include a failing row indicator (FRI) 214 that can act as a complement to the FCI 213. Various other embodiments may include a FRI 714 to complement the FCI 713 mentioned above. In various embodiments that include a FRI 714, the FRI stores information related to errors occurring in rows.
Bits stored in the shift register 849 are advanced along the register when testing in a test step advances to another row. Clocking of the shift register 849 when testing of the words in a row is completed is accomplished by detecting an overflow (ovf, 848) in the row address register 850. For example, suppose each row consists of four words. The first word may have an address of, for example, 00000000. The next word may have an address of 00000001. The third and fourth words have addresses of 00000010 and 00000011, respectively. After that, incrementing the address register to advance to the next word address is memory gives an address of 00000100. That is, incrementing the lowest two bits of the address register has produced an overflow (of those two bits), as the memory address advances to the next row. This overflow occurs every time the address register 850 advances from an address ending in 11, to the next following address. In this way, the ovf signal 848 can trigger a reset of the flip-flop 847, and can also trigger the shift register 849, to track which row in memory is currently under test, and which rows have or have not had failures. That is, successive bits of the shift register 849 correspond uniquely to horizontal segments of the memory array 204 (see
An embodiment of an enhanced version of the failing row indicator (E-FRI) 846 is shown in
In more detail, the enhanced failing row indicator 846 includes a B-bit shift register 849 that is clocked whenever an overflow of the row address register 850 takes place. D flip-flops 851a, 851b, and 851c are configured to register three successive word failures in the same row. When this occurs, an output of logical one is provided by D flip-flop 851c to the shift register 849 to record the row failure when the shift register 849 is clocked by the overflow 848 of row address register 850.
Three particular embodiments of the integrated circuit device 207 (see
As discussed above, at the end of a test step, compacted test response signature data, and memory location data, are made available to the ATE. Subsequently, the compacted test response signature data and memory location data can be provided by the ATE to a diagnostic tool (2800, see
Turning first to the analysis of failing patterns, failing patterns can be grouped into classes that can be distinguished both by the layout of the failing pattern in the memory array, and by the values of FWC, FCI, and FRI that would be collected in the presence of these types of failing patterns. In Table 2 and the further discussion below, FWC, FCI, and FRI can refer to the values collected by the FWC 211, the FCI 213, and the FRI 214.
The rationale for collecting data in the FWC 211 (see
In a first example of faults whose failing pattern classes are listed in Table 2, two diagonal cells show failures. This corresponds to failing pattern class No. 3 in Table 2. There are two possible situations as shown in
In the second example, all the cells in a single column show failures. This corresponds to failing pattern class No. 7 in Table 2. An example of this situation is shown in
In the third example of faults whose failing pattern classes are listed in Table 2, all the cells in a row and a column show failures, as shown in
Turning now to a discussion of how failure diagnosis may be performed according to various embodiments, several diagnostic techniques can be applied in different circumstances to determine locations of failing memory cells. In this disclosure, four generic diagnostic techniques are discussed that can be used alone or in combination with one another to perform accurate fault diagnosis in the MBIST environment. It should be appreciated that these diagnostic techniques may be carried out on-chip in some embodiments. In other embodiments, the diagnostic techniques may be applied in a separate diagnostic tool external to the integrated circuit device under test. In this disclosure the diagnostic techniques are also referred to as diagnostic schemes.
Typically, the disclosed embodiments of diagnostic techniques follow at-speed test data collection as shown earlier. Depending on a memory failure type (indicated, for instance, by the content of FCI 828, FRI 946 and FWC 826 (see FIG. 8)), one of the schemes described here can be deployed to make the diagnostic process time-efficient and accurate. In the remainder of this disclosure, the following notation will be used: whenever flip-flops are shown in figures, their content is represented as black and white boxes corresponding to the logic values of 1 and 0, respectively. Similarly as in the previous discussion, slashed lines in memory arrays indicate failing memory cells.
A first diagnosis technique is referred to herein as a discrete logarithm approach (DELTA), and can be used to diagnose the majority of failures occurring most commonly in memory arrays. As an example, consider a failure presented in
DELTA, the diagnostic technique presently under discussion, takes advantage of a discrete logarithm-based method. Further detail about the discrete logarithm-based method is provided in D. W. Clark, L.-J. Weng, “Maximal and near-maximal shift register sequences: efficient event counters and easy discrete logarithms,” IEEE Trans. on Computers, vol. 43, No. 5, May 1994, pp. 560-568, which is incorporated herein by reference in its entirety. The discrete logarithm-based method solves the following problem: given an internal XOR LFSR (Galois LFSR) and its particular state, determine the number of clock cycles necessary to reach that state assuming that the LFSR is initially set to 0 . . . 001. The method employs the Chinese Remainder theorem and requires pre-computing of a reasonable number of LFSR states which, once generated, can be stored in a look-up table (LUT). The number of LFSR states to be pre-computed is given by m1+m2+ . . . +mk, where the product m1·m2· . . . ·mk gives the period m of the LFSR. This period should be chosen carefully to guarantee small values of the coefficients mi (each period has different factorization). The pre-computations can be efficiently done using the fast LFSR simulation introduced below. For example, it takes about 5 seconds on 2.4 GHz CPU to generate all required values for a 55-bit compactor.
DELTA is very time-efficient and usually works in a fixed time. The pre-computation phase is typically executed only once in the diagnostic tool. A particular embodiment of the pre-computation can be summarized by the following method acts (which can be performed alone or in various combinations and subcombinations with one another):
For the case m=21, m1=3, m2=7, it can be checked that v1=1 and v2=5. Numbers vi are also required for the LFSR distance computation as it will be shown in the next paragraph.
In one embodiment, each time DELTA is invoked, the following method acts are performed for a given content y of the LFSR corresponding to a given fault:
y
m/m
modp(x)=(x3+x)21/3mod x5+x+1=x4+x2+x=(10110)
y
m/m
modp(x)=(x3+x)21/7mod x5+x+1=x4+x2+x=(10100)
to obtain the distance L between the current state of the LFSR and the initial state 0 . . . 001:
Applying DELTA to the failing words counter described above is straightforward. Similarly, if one wants to apply the method to the signature register also introduced above in the same section, DELTA is desirably invoked twice for each signature. This process is illustrated by the following two examples:
Assume a single faulty cell cx produces the signature S(cx) 1654 in
Consider a single column failure producing signature S(Cx).
A second diagnosis method is referred to herein as a fast LFSR simulation. In this technique, the state, after a given number of clock cycles, of an LFSR that has been has been initialized with an arbitrary combination of 0s and 1s can be determined in a time-efficient manner. Additional detail concerning this technique is provided in J. Rajski, J. Tyszer, “Primitive polynomials over GF(2) of degree up to 660 with uniformly distributed coefficients,” Journal of Electronic Testing: Theory and Application (JETTA), vol. 19, Kluwer Academic Publishers, 2003, pp. 645-657, hereby incorporated herein by reference in its entirety. As mentioned earlier, the fast LFSR simulation technique can be useful in obtaining states of the LFSR required by DELTA and other diagnostic techniques presented here.
Various embodiments of the techniques use an n×n LUT to store states of the n-bit LFSR after applying a certain number of clock cycles as shown in
Using a table as shown in
Let an internal XOR LFSR implement the primitive polynomial x4+x3+1 and be initialized to 1010, as shown 1960 in
The discrete logarithm approach described above is capable of diagnosing failures where storing or generation of reference signatures is feasible. In certain cases, however, it might be impractical to produce all reference signatures. For instance, if two columns constitute a failure (
In order to cope with more complicated failures, sets of linear equations can be employed. Consider, for example, a signature produced by a single row failure. Since a MIRG is a linear circuit, the corresponding signature can be easily obtained by adding bitwise failing signatures associated with individual memory cells of this particular row of. Moreover, multiple column/row failing signatures can be computed by adding modulo 2 signatures corresponding to single column/row failures. Hence, it may be possible to find defective rows or columns by solving a set of linear equations over GF(2). In these equations, Boolean-valued variables represent either columns or rows, and every equation corresponds to a single signature bit. They can be simplified by using, for instance, Gauss-Jordan elimination. Since the amount of failing columns/rows is known (via the FWC value, for example), solutions of anticipated multiplicity can be sought. If such a solution is not found, Gaussian elimination can be repeated for different sequences of pivot variables. Experiments indicate that in virtually 100% of cases, the first solution of the expected multiplicity is correct provided the size of the MIRG is large enough to ensure sufficient diagnostic resolution.
Consider again a failure that involves two columns located in two vertical segments as shown in
Finally, in certain cases, neither the DELTA nor linear equations methods can be employed due to the following phenomenon. Let a failure be composed of a single failing column and a single failing row. All failing cells are shown in
In cases where failing rows and columns intersect, a signature simulation can be performed. Using one approach, “soft copies” of the signature register—that is, copies created in the memory of the diagnostic tool 2800 (see FIG. 28)—store partial signatures of the failing rows, columns, and “intersection” cells. Such soft copies may be referred to herein as soft signature registers. The partial signatures are subsequently XOR-ed for each mutual configuration, and their sum is compared against the actual failing signature. This is illustrated by the following example.
Consider again a single column and a single row failure of
S(actual_failure)=S(row—x)+S(column—y)+S(cell_(x,y)) (1)
The reference signatures corresponding to the failing row, column and cell are stored in the LUT. Three soft signature registers Sr, Sc, and Si can be used to represent signatures associated with a row, a column and an intersection cell, respectively.
According to various embodiments, the process of signature simulation can include the following:
For the failure shown in
As noted above, some embodiments of the disclosed technology use ring generators to implement counters and signature registers. However, the DELTA method presented above typically uses an LFSR capable of dividing polynomials. Furthermore, the only device with such ability is a Galois (internal XOR) LFSR. In order to use ring generators instead of Galois LFSRs, the ring generator trajectory can be mapped into a trajectory of the internal XOR LFSR. This can be done provided that a ring generator preserving the transition function of a respective LFSR is used. See, e.g., J.-F. Li, C.-W. Wu, “Memory fault diagnosis by syndrome compression,” Proc. DATE, 2001, pp. 97-101. Thus, both the LFSR and the ring generator can produce the same maximum length sequence or m-sequence. An example of such equivalent devices is shown in
By using symbolic Gaussian elimination, the above equations can be simplified as follows:
Assume that the ring generator has reached state wxyz=1110. Equations (3) yield the corresponding state of the Galois LFSR which is, in this particular case, equal to abcd=1001. This conclusion can be confirmed in a different way by performing an exhaustive simulation of the LFSR 2552 and RG 2511, as presented in Table 3. As can be seen, the RG state wxyz=1110 corresponds to the LFSR state abcd=1001 and vice versa.
The grouping into classes shown in Table 2 can be used to set up a look up table for failing patterns where the lookup table uses FWC, FCI, and FRI values to determine the failing patterns that may correspond to these location information values. Thus, in order to accelerate diagnostic procedures for the most prevalent failing patterns, signatures of certain representative faults can be stored in an LUT. Once determined, they can be subsequently employed as a reference. Examples of pre-computed signatures that can be deployed in embodiments of the disclosed MBIST diagnostic schemes are summarized in Table 4.
As discussed above, a variety of diagnosis schemes can be employed to process the location information and compacted signature data resulting from memory test failures. This section, and its subsections, provide examples of failing patterns along with techniques for handling them based on the contents of the FWC, FCI and FRI registers. Although the examples provided below include numerical references indicating one possible flow, the described method acts may in some cases be performed in a different order or simultaneously.
Diagnosis strategies for the failing patterns in Table 5 are now described in the following cases.
Since the exact number of failing cells in a row is unknown in this case, DELTA has to be used more than once (W2 times in the worst case). Each time, a different combination of adjacent failing cells in boundary failing sectors is examined by the following routine:
Searching for two failing rows in two memory segments proceeds in a way similar to that of Case J except the following:
a+b+c+d=1
w+x+y+z=1
Searching for the two failing columns in two memory segments proceeds in a way similar to that presented in Case N above except for the following:
a+b+c+d=1
w+x+y+z=1
In cases where failing cells belonging to rows or columns are assumed to intersect, the simulation method can be used as discussed above in connection with
Turning now to a discussion of the practice of failure diagnosis,
The diagnostic tool in addition receives 2772 failure location information of the integrated circuit device from the ATE. It will be appreciated that in various embodiments the steps 2771 and 2772 may take place concurrently; in various other embodiments one step may follow the other in a particular order. Also, as discussed above, in various embodiments the ATE receives the failure location information from a failing words counter, failing column indicator, and failing row indicator of the integrated circuit device. In various other embodiments, as previously discussed, the ATE receives the failure location information from shadow registers in the integrated circuit device. Moreover, typically the compacted signatures and the failure location data are transferred from the shadow registers to the ATE in response to a signal from the ATE.
As discussed above in connection with Table 5, analysis of filing patterns allows for creation of a lookup table for use in determining a diagnostic procedure to apply, according to the values stored in the filing words counter (FWC), the failing column indicator (FCI), and the filing row indicator (FRI). For example, the FWC, FCI, and FRI values can be used to generate an index into the lookup table. Whether by using the index, or by another method, the diagnostic tool selects 2773 a diagnostic procedure from the set of diagnostic procedures discussed above, based on the failure location data.
Next, the selected diagnostic procedure is executed 2776 in the diagnostic tool to generate coordinates of a failing memory cell from the temporally compacted test response signature. Some test response signatures may indicate more than one failing memory cell. In those cases, the diagnostic procedure executed 2776 in the diagnostic tool generates coordinates for more than one failing memory cell.
After coordinates of the failing memory cell(s) have been determined, the diagnostic tool reports 2777 the coordinates. As discussed in connection with the example fault dictionary in Table 1, the coordinates of the failing memory cells may be used to construct monochrome or color bitmaps for display of memory failure information. It is understood that the reporting of the coordinates of the failing memory cells can include display or printout of such bitmaps.
In various embodiments a user interface 2880 provides for display of data or results, for example on a display device 2881, or may output results and data by for example a printer or plotter (not shown). The user interface 2880 also provides for receipt of user input via, for example, one or more input devices 2882 such as, for example, a keyboard, touch screen, mouse, or other pointing device. It is understood that any suitable device for display of results or data, and any suitable device for receipt of user input, is within the scope of this disclosure.
The diagnostic tool device 2800 in addition includes a set of modules 2883, that may be implemented for example, as instructions in software, or may be hardware implementations. It should be appreciated that some modules may be implemented in software and other modules may be implemented as hardware.
The modules 2883 include a signature receipt module 2871, configured to receive temporally compacted test response signatures, for example, from a signature register of the integrated circuit device, or from a corresponding shadow register for the signature register, as described above, and according to the step 2771 of the method 2700 (see
In addition, the diagnostic tool includes a diagnostic selection module 2873 that is configured to select a diagnostic procedure from a set of diagnostic procedures as discussed above, based on the failure location data. The selection of a diagnostic procedure may be performed by the diagnostic selection module 2873, for example, in accordance with the step 2773 described above. The modules 2883 further include a diagnosis module 2876 configured to execute the selected diagnostic procedure to generate coordinates of a failing memory cell from the temporally compacted test response signature, in accordance with the step 2776 of the method 2700 described above. A reporting module 2877 included with the modules 2883 is configured to report the coordinates of the failing memory cells that have been determined, according to, for example, the step 2777 discussed above.
Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments, it will be recognized that the illustrated embodiments include only examples and should not be taken as a limitation on the scope of the disclosed technology. Rather, the disclosed technology includes all novel and nonobvious features and aspects of the various disclosed apparatus, methods, systems, and equivalents thereof, alone and in various combinations and subcombinations with one another. While the invention has been described with respect to specific examples including presently preferred modes of carrying out the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims.
This application claims priority under 35 U.S.C. §119 to U.S. Provisional Patent Application No. 60/973,432, entitled “Fault Diagnosis in a Memory BIST Environment,” filed on Sep. 18, 2007, and naming Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, and Jerzy Tyszer as inventors, which application is incorporated herein by reference in its entirety.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/US08/76911 | 9/18/2008 | WO | 00 | 7/8/2010 |
Number | Date | Country | |
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60973432 | Sep 2007 | US |