Patent Application
20100166289
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-335484, filed on Dec. 27, 2008; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a feature-quantity extracting method, a designed-circuit-pattern verifying method, and a computer program product.
2. Description of the Related Art
At present, it is a general practice to execute optical proximity correction (OPC) on a photomask used in photolithography. The OPC is a technology for adjusting a layout of a photomask in advance to form a desired pattern on a wafer. To execute the OPC, it is indispensable to perform simulation for accurately predicting a finish of a pattern on a wafer from a mask layout drawing of a circuit pattern.
The simulation for execution of the OPC requires a simulation model called resist model for calculating a resist image from optical simulation images (hereinafter simply referred to as “optical images”) of a mask pattern projected on a wafer taking into account properties of a resist applied on the wafer. When the resist model is created, a plurality of test patterns of various shapes selected in advance are actually exposed to light and a resist dimension is experimentally measured in advance. The simulation is performed under conditions same as exposure conditions and calibration parameters are optimized to reproduce an experimental result, whereby the resist model is created.
In work for measuring a resist dimension as a basis for resist model creation, selection of test patterns to be used is important. When features of an actual circuit pattern that should be predicted (hereinafter simply referred to as “circuit pattern”) and features of a test pattern used for resist model creation are substantially different from each other, it is difficult to create an effective resist model. It is desirable that a plurality of kinds of test patterns are selected and features of the selected kinds of test patterns include all features of a pattern that should be predicted. Recently, feature quantities representing features of optical images obtained by optical calculation for a circuit pattern are extracted from the optical images and test patterns are selected to cover a distribution of the feature quantities of the circuit pattern.
In recent years, microminiaturization of semiconductor integrated circuits is advanced and circuit pattern density is markedly increased. Therefore, in a 45 nm node or beyond, a method called Dense OPC for once calculating resist image intensity on two-dimensional grids and calculating resist image intensity in sections among the grids according to interpolation is effective for an increase in simulation speed (see, for example, Proc. SPIE Vol. 6154 01-1). As a resist image description system of a resist model for describing a two-dimensional resist image, for example, there is a constant threshold model (CTM). With the CTM, feature quantities are extracted from optical images, the extracted feature quantities are multiplied by calibration parameters, and the feature quantities multiplied by the calibration parameters are added to the original optical images to describe a resist image.
When a resist image description system for using feature quantities as explanatory variables such as the CTM is adopted, it is desirable to use test patterns selected based on types of feature quantities same as types of feature quantities used in the CTM. However, when the types of feature quantities used in the CTM are calculated, feature-quantity extraction parameters are used. The feature-quantity extraction parameters require optimization based on a test pattern measurement result. Therefore, feature quantities cannot be extracted at a stage of test pattern selection before the optimization. If a resist model is created by using a model pattern selected by using types of feature quantities different from specific feature quantities used in the CTM, it is likely that the created resist model of the CTM does not entirely cover features of a circuit pattern. As a result, prediction accuracy for a resist image of the circuit pattern is not guaranteed.
A feature-quantity extracting method according to an embodiment of the present invention comprises: setting feature-quantity extraction parameters used by feature-quantity extraction functions for calculating feature quantities used as explanatory variables of a resist model for predicting a resist image; and causing the feature-quantity extraction functions, for which the feature-quantity extraction parameters are set, to act on optical images of a pattern of a photomask and calculating feature quantities from the optical images.
A designed-circuit pattern verifying method according to an embodiment of the present invention comprises: setting feature-quantity extraction parameters used by feature-quantity extraction functions for calculating feature quantities used as explanatory variables of a resist model for predicting a resist image; causing the feature-quantity extraction functions, for which the feature-quantity extraction parameters are set, to act on optical images of a circuit pattern created by a designer and calculating feature quantities at a plurality of points of the circuit pattern from the optical images; comparing a distribution of the calculated feature quantities and a distribution of feature quantities of test patterns and extracting a point of the circuit pattern deviating from a range of the feature quantity distribution of the test patterns; and displaying the extracted point of the circuit pattern on a display device.
A computer program product according to an embodiment of the present invention executable by a computer, the computer program product causes the computer to execute: setting feature-quantity extraction parameters used by feature-quantity extraction functions for calculating feature quantities used as explanatory variables of a resist model for predicting a resist image; and causing the feature-quantity extraction functions, for which the feature-quantity extraction parameters are set, to act on optical images of a pattern of a photomask and calculating feature quantities from the optical images.
Exemplary embodiments of a feature-quantity extracting method, a designed-circuit-pattern verifying method, and a computer program product according to the present invention will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.
Lithography simulation models include a mask model, an optical model, and a resist model. In photolithography, exposure light is irradiated on a photomask and light transmitted through the photomask is irradiated on a resist on a wafer via a projection optical system. The mask model is a model for calculating, from a layout drawing of a mask pattern, how the light transmitted through the photomask changes. Optical images corresponding to a mask pattern formed on the photomask are projected on the resist formed on the wafer. The optical model is a model for calculating a light intensity distribution of the optical images on the resist. A latent image is formed on the resist according to the light intensity distribution of the optical images on the resist. A resist pattern corresponding to the latent image is obtained by performing development processing. The resist model is a model for calculating a resist pattern (a resist image) from the light intensity distribution of the optical images. A dimension of the resist pattern (a resist dimension) can be predicted from a mask layout drawing by combining the mask model, the optical model, and the resist model.
The resist model is created by executing optimization work to reduce a difference between an actual value of a resist dimension and a predicted value by simulation (a residual) as much as possible. As a mask pattern for measuring the actual value, rather than an actual circuit pattern itself having a pattern of an extremely complicated shape, a pattern of a simple shape having features similar to those of a circuit pattern is used to improve measurement accuracy for the actual value used for the optimization work. Therefore, first, work for selecting several test patterns is executed to cover features of a circuit pattern that should be predicted from a prepared large number of test patterns of simple shapes.
In
The feature quantities are values representing features of objects (optical images). Various types of feature quantities can be defined according to what types of features the feature quantities represent. For example, a tilt (Slope) as a tilt of the intensity of the optical images, a maximum of the intensity of the optical images (Imax), and a minimum of the intensity of the optical images (Imin) can be defined as the feature quantities.
The test patterns prepared in advance include various kinds of test patterns such as isoLine as an independent line, isoSpace as an independent space, a Pitch type in which a large number of lines are arranged in parallel spaces away from one another, 2-Line in which two lines are arranged in parallel, 3-Line in which three lines are arranged in parallel, and isoLE (Line End) in which two lines are arranged on the same straight line slightly away from each other. For the respective kinds of the test patterns, there are a large number of patterns having different dimensions of lines and spaces.
In the following explanation, calculating optical images from a mask layout drawing of a mask pattern (a circuit pattern or a test pattern) and extracting feature quantities from the optical images may be simply represented as extracting feature quantities from the mask pattern. Feature quantities extracted from optical images of a mask pattern may be simply represented as feature quantities of the mask pattern.
At step S1, when the feature quantities are extracted from the circuit pattern, feature quantities at a plurality of points of the circuit pattern are extracted based on rules set in advance. For example, it is also possible to virtually arrange two-dimensional grids in the mask layout drawing of the circuit pattern and extract feature quantities at a plurality of points where the grids and the circuit pattern rendered on the mask layout drawing cross. At step S2, when feature quantities are calculated from the test patterns, feature quantities at points determined in advance for each of the test patterns are extracted. For example, in the case of a test pattern of an independent line type, an edge section is set in advance in the center of a line as an extraction point. In the following explanation, extracting feature quantities from a plurality of points of the circuit pattern on the mask layout drawing may be simply represented as extracting feature quantities from the circuit pattern. A distribution of a plurality of feature quantities extracted from a plurality of points of the circuit pattern on the mask layout drawing may be simply represented as a distribution of feature quantities of the circuit pattern or a feature quantity distribution of the circuit pattern.
At the following steps S1 and S2, a distribution of the feature quantities of the circuit pattern calculated at step S1 and a distribution of the feature quantities of the large number of test patterns calculated at step S2 are compared for each of types of the feature quantities and test patterns are selected to sufficiently cover the distribution of the feature quantities of the circuit pattern (step S3). As a method of selecting test patterns to cover the feature quantities of the points of the circuit pattern, there are various methods. For example, as described in a document “Proc. of SPIE Vol. 6520 652048-5”, there is a selection method for plotting feature quantities of a circuit pattern and test patterns on a graph having various feature quantities as different coordinate axes (hereinafter, “feature space”), dividing the coordinate axes with grids at fixed intervals and, paying attention to respective small regions in a minimum unit divided by the grids, executing, in the respective small regions, work for, in the small region where the feature quantities of any one of the points of the circuit pattern are plotted, leaving one test pattern and deleting the other test patterns in the same small region, in the small region where no feature quantities of the points of the circuit pattern are plotted, deleting all the test patterns in the same small region, and selecting the remaining test patterns.
The work shifts to work for creating a resist model based on the selected test patterns. First, the test patterns selected at step S3 are actually exposed to light and a resist dimension of an obtained resist pattern is measured by using a critical dimension scanning electron microscope (CD-SEM) (step S4). Calibration parameters included in a resist model are optimized to reduce a difference (a residual) between a resist dimension (a predicted dimension) obtained by the resist model and the resist dimension (an actual dimension) measured at step S4 (step S5). The calibration parameters are optimized to sufficiently reduce the residual and the resist model is completed (step S6).
As one of resist image description systems that can describe a two-dimensional resist image, there is CTM. With the CTM, when a Gaussian function concerning x of a standard deviation σx is represented as G(σx, x) and optical images are represented as I, a resist image R is described as follows:
R=I+A*G(σ1,I)+B*G(σ2,f1(I))+C*G(σ3,f2(I)) Formula 1
where, f1 and f2 are the following functions:
f1(I)=if(I>b0)I−b0, else 0 Formula 2
f2(I)=if(<b1)bI−I, else 0 Formula 3
G(σ1, I), G(σ2, f1(I)), and G(σ3, f2(I)) are respectively a feature-quantity extraction function (a first feature-quantity extraction function) for extracting a feature quantity (a first feature quantity) concerning fluctuation of the optical images, a feature-quantity extraction function (a second feature-quantity extraction function) for extracting a feature quantity (a second feature quantity) concerning a diffusion behavior of acid, and a feature-quantity extraction function (a third feature-quantity extraction function) for extracting a feature quantity (a third feature quantity) concerning a diffusion behavior of a base. As indicated by Formulas 1 to 3, the resist image R is described as a value obtained by adding up the first to third feature quantities respectively obtained by multiplying the optical images I with calibration parameters A, B, and C. In other words, a resist model by the CTM is a linear model with the first to third feature quantities set as explanatory variables.
To allow this model to hold in a range of values of the explanatory variables (i.e., the first to third feature quantities) taken by a circuit pattern that should be predicted, it is necessary to select test patterns to completely include (cover) a range of the first to third feature quantities that could be taken by the circuit pattern. To select test patterns to strictly completely include the range of the first to third feature quantities of the circuit pattern, it is desirable to use the first to third feature quantities used in the CTM during test pattern selection, i.e., in the process of steps S1 to S3.
However, σ1, σ2, σ3, b0, and b1 (all of which are referred to as feature-quantity extraction parameters) used for calculating the first to third feature quantities are optimized together with A, B, and C at step S5. Therefore, values of the parameters are not decided at the stage of steps S1 to S3. In other words, when a resist model is created by using the CTM, feature quantities cannot be calculated by using the first to third feature quantities during the processing at steps S1 to S3. Therefore, according to this embodiment, the first to third feature quantities can be extracted even before the optimization of the resist model by setting and using values for σ1, σ2, σ3, b0, and b1.
In
Subsequently, the optical-image calculating unit 12 calculates optical images from the received mask layout drawing of the mask pattern (step S12). Specifically, for example, the optical-image calculating unit 12 calculates a mask transmission function from the mask layout drawing and calculates optical images projected on a resist based on the calculated mask transmission function and set conditions for an illumination system and an optical system of an exposure apparatus.
The feature-quantity-extraction-parameter setting unit 13 acquires several feature-quantity extraction parameters of resist models in the past and calculates a range of the feature-quantity extraction parameters of the resist models in the past, i.e., a range of fluctuation in the feature-quantity extraction parameters (step S13). The feature-quantity-extraction-parameter setting unit 13 extracts a representative value of the feature-quantity extraction parameters from the calculated range and sets the representative value as a feature-quantity extraction parameter before optimization (step S14). The feature-quantity calculating unit 14 calculates the first to third feature quantities for the optical images calculated at step S12 using first to third feature-quantity extraction functions for which the feature-quantity extraction parameter set at step S14 is set (step S15). When a plurality of values are set for one type of feature-quantity extraction parameter by the feature-quantity-extraction-parameter setting unit 13, a plurality of feature quantities are calculated for one type of feature quantity based on the feature-quantity extraction functions for which the set respective values are set.
For example, at step S13, the feature-quantity-extraction-parameter setting unit 13 checks values of σ1, σ2, σ3, b0, and b1 from eight actual resist models in total in several generations and layers in the past and finds that the values are respectively in ranges 10 nm<=σ1<=40 nm, 120 nm<=σ2<=200 nm, 140 nm<=σ3<=200 nm, 0.12<=b0<=0.16, and 0.07<=b1<=0.11. At step S14, the feature-quantity-extraction-parameter setting unit 13 sets various feature-quantity extraction parameters at an interval of fixed width in such a manner as σ1=10 nm, 20 nm, 30 nm, and 40 nm, σ2=100 nm, 150 nm, and 200 nm, σ3=100 nm, 150 nm, and 200 nm, b0=0.1, 0.15, and 0.2, and b1=0.05, 0.1, and 0.15.
The first to third feature quantities are independent from one another. There are four kinds of values of σ1, 3×3 kinds of values of combinations of σ2 and b0, and 3×3 kinds of values of combinations of σ3 and b1. Therefore, at step S15, the feature-quantity calculating unit 14 calculates four kinds of values, nine kinds of values, and nine kinds of values for the first to third feature quantities, respectively.
A graph on which feature quantities calculated by the feature-quantity calculating unit 14 from optical images of a certain circuit pattern using the example of the values of σ1, σ2, σ3, b0, and b1 are plotted with slope as the ordinate is shown in
When a large number of values are set for one type of feature-quantity extraction parameters at an interval of small width from the range in which the feature-quantity extraction parameters are included, a resist model that can be highly accurately predicted can be more surely obtained than a resist model obtained when the number of values is small. However, labor and time at step S3 increase according to an increase in the number of values. Therefore, it is desirable to set values of the feature-quantity extraction parameters taking into account certainty of prediction accuracy and labor and time at step S3.
In the example of steps S13 and S14, values are set based on the range of fluctuation in the feature-quantity extraction parameters used in the resist models in the past. However, it is also possible that a user of the feature-quantity extracting apparatus 10 inputs a range of desired values of the feature-quantity extraction parameters and the feature-quantity-extraction-parameter setting unit 13 sets values of the feature-quantity extraction parameters from the input range. It is also possible that the user directly inputs desired values of the feature-quantity extraction parameters and the feature-quantity-extraction-parameter setting unit 13 sets the input values as the feature-quantity extraction parameters.
In the above explanation, the first to third feature quantities are set as the explanatory variables in the resist image description system by the CTM. However, in the CTM, types of feature quantities used as the explanatory variables are not limited to the first to third feature quantities and can be increased or decreased. When the types of feature quantities are increased, for example, slope can be added.
A feature-quantity extracting method according to the first embodiment can be applied in extracting feature quantities used in not only the CTM but also any resist image description system as long as at least one type of feature quantities that need to be extracted by using feature-quantity extraction functions for which feature-quantity extraction parameters are set.
In the above explanation, feature quantities are extracted from the optical images to predict a resist pattern. However, the feature-quantity extracting method according to the first embodiment can be applied in any case as long as, to create a model for predicting a second pattern using feature quantities extracted from a first pattern as explanatory variables, feature quantities are extracted from the first pattern by using feature-quantity extraction functions for which feature-quantity extraction parameters are set. For example, feature quantities can be extracted by applying the first embodiment when, to create, with feature quantities of a layout drawing of a mask pattern, optical images, or a resist image (a first pattern) set as explanatory variables, an etching model for predicting a pattern (a second pattern), which is formed in a processed layer by etching, using a resist pattern as a mask, feature quantities are extracted from the layout drawing of the mask pattern, the optical images, or the resist image by using the feature-quantity extraction functions for which the feature-quantity extraction parameters are set. Further, feature quantities can be extracted by applying the first embodiment when, to create a resist model for predicting a pattern (a second pattern) formed on a resist with feature quantities of a pattern (a first pattern) of a template set as explanatory variables in nano-imprinting for forming a pattern on the resist using the template, feature quantities are extracted from the pattern of the template by using the feature-quantity extraction functions for which the feature-quantity extraction parameters are set.
The feature-quantity extracting apparatus 10 according to the first embodiment can be realized by executing a computer program in a usual computer including a control device 1, a storage device 2, an external storage device 3, a display device 4, and an input device 5 shown in
The control device 1 is, for example, a central processing unit (CPU). The control device 1 executes a feature-quantity extracting program as a program for extracting feature quantities. The display device 4 is a display device such as a liquid crystal monitor and displays, based on an instruction from the control device 1, output information for a user such as an operation screen. The input device 5 includes a mouse and a keyboard and receives the input of operation of the feature-quantity extracting apparatus 10 from the user. Operation information input to the input device 5 is sent to the control device 1. The storage device 2 is a memory area such as a read only memory (ROM) or a random access memory (RAM). The external storage device 3 is a hard disk drive (HDD), a compact disk (CD) drive, or the like.
The feature-quantity extracting program is stored in the ROM and loaded to the RAM. The control device 1 executes the feature-quantity extracting program loaded in the RAM. Specifically, in the feature-quantity extracting apparatus 10, the control device 1 reads out the feature-quantity extracting program from the ROM and expands the feature-quantity extracting program in a program storage area in the RAM to execute various kinds of processing according to instruction input from the input device 5 by the user. A mask layout drawing is input from the external storage device 3 or the like. The control device 1 executes the various kinds of processing based on the mask layout drawing input from the external storage device 3 or the like. The control device 1 temporarily stores data such as optical images and feature-quantity extraction parameters calculated in the various kinds of processing in a data storage area formed in the RAM. The control device 1 outputs calculated feature quantities to the program storage area in the RAM, the external storage device 3, or the like. The control device 1 can display the calculated feature quantities on the display device 4. The feature-quantity extracting program can be stored in the external storage device 3 instead of the ROM. The feature-quantity extracting program has a module configuration including the respective components (the mask-pattern input unit 11, the optical-image calculating unit 12, the feature-quantity-extraction-parameter setting unit 13, and the feature-quantity calculating unit 14). The control device 1 (the CPU) reads out the feature-quantity extracting program from the storage medium and executes the feature-quantity extracting program based on operation by the user via the input device 5. The respective modules are loaded onto the RAM by the execution. The mask-pattern input unit 11, the optical-image calculating unit 12, the feature-quantity-extraction-parameter setting unit 13, and the feature-quantity calculating unit 14 are generated on the main storage device.
The feature-quantity extracting program executed by the feature-quantity extracting apparatus 10 according to the first embodiment can be recorded in a computer-readable recording medium such as a compact disk-read only memory (CD-ROM), a flexible disk (FD), a compact disk-recordable (CD-R), or a digital versatile disk (DVD) as a file of an installable format or an executable format and provided.
The feature-quantity extracting program executed by the feature-quantity extracting apparatus 10 according to the first embodiment can be stored on a computer connected to a network such as the Internet and downloaded through the network to thereby be provided. The feature-quantity extracting program executed by the feature-quantity extracting apparatus 10 according to the first embodiment can be provided or distributed through the network such as the Internet.
The feature-quantity extracting program executed by the feature-quantity extracting apparatus 10 according to the first embodiment can be incorporated in the ROM or the like in advance and provided.
As explained above, according to the first embodiment, feature-quantity extraction parameters are set and feature quantities are extracted from optical images by using feature-quantity extraction functions for which the set feature-quantity extraction parameters are set. Therefore, it is possible to extract feature quantities even before the feature-quantity extraction parameters are optimized.
A second embodiment of the present invention is explained below. As explained above, a resist model is created to reduce a difference between an actual dimension of a resist pattern transferred from selected test patterns and created and a predicted dimension of a resist image by the resist model (step S5 in
On the other hand, test patterns are selected to cover feature quantities of a circuit pattern (step S3 in
Therefore, according to the second embodiment, when test patterns used for resist model creation are selected, test patterns having features with which a resist dimension can be more highly accurately measured are preferentially selected.
As shown in the figure, a test-pattern selecting apparatus 20 includes a feature-quantity extracting apparatus 21 that calculates optical images from a mask layout drawing of a large number of test patterns prepared in advance and a circuit pattern and extracts feature quantities from the calculated optical images, respectively, a priority-information storing unit 22 having stored therein priority information in which priority set for each of the test patterns according to measurement accuracy for a resist dimension is described, and a test-pattern selecting unit 23 that selects test patterns for resist model creation based on the feature quantities extracted by the feature-quantity extracting apparatus 21 and the priority information stored by the priority-information storing unit 22. The feature-quantity extracting apparatus 21 can be the same as the feature-quantity extracting apparatus 10 explained in the first embodiment.
The priority set for each of the test patterns described in the priority information is explained below.
Arrows in the figures indicate sections equivalent to sections where a resist dimension is measured in a resist image transferred onto a wafer. As shown in the figures, the test patterns shown in
In a test pattern shown in
In a test pattern shown in
In the above explanation, as an example, measurement accuracy is compared for each of the kinds of the test patterns and the priority is set for the test patterns.
However, the priority is set for each of the test patterns according to measurement accuracy of a resist dimension.
First, the feature-quantity extracting apparatus 21 calculates optical images from a mask layout drawing of a large number of test patterns prepared in advance and a circuit pattern and extracts feature quantities from the optical images, respectively (step S21).
Subsequently, the test-pattern selecting unit 23 plots feature quantities of the respective test patterns in a feature space formed by dividing respective coordinate axes with grids at a fixed interval. Then, paying attention to respective small regions divided by the grids, when a plurality of test patterns are plotted in the same small regions, the test-pattern selecting unit 23 executes, for all the small regions, operation for leaving test patterns having a highest priority value and removing the other patterns from the feature space and once sets the test patterns left on the feature space as selection candidates (step S22).
The test-pattern selecting unit 23 plots feature quantities of the circuit pattern in the feature space, compares, for each of the small regions, the feature quantities of the test patterns as the selection candidates and the feature quantities of the circuit pattern, removes the test patterns as the selection candidates from the small regions in which the feature quantities of the circuit pattern are not plotted, and finally selects the remaining test patterns as test patterns for resist model creation (step S23).
As explained above, according to the second embodiment, test patterns used for optimization of a resist model are selected based on feature quantities of test patterns and priority set in advance for each of the test patterns according to measurement accuracy for an actual dimension. Therefore, it is possible to create a resist model for which high accuracy is guaranteed using the selected test patterns.
In the above explanation, the test-pattern selecting unit 23 divides respective coordinate axes of a feature space with the grids and selects one test pattern with high priority for each of small regions divided by the grids. However, two or more test patterns can be selected from one small region. Instead of being selected from the small regions divided by the grids, test patterns can be selected by other methods. For example, when the respective coordinate axes of the feature space is normalized and distances among feature quantities of a plurality of test patterns are within a range of a predetermined Euclidian distance in the feature space after the normalization, one test pattern can be selected out of the test patterns based on priority information.
In the above explanation, the test-pattern selecting unit 23 calculates test patterns as selection candidates in advance and finally selects test patterns used for resist model creation out of the test patterns as the selection candidates. However, the test-pattern selecting unit 23 can select test patterns used for resist model creation based on feature quantities of the test patterns, feature quantities of a circuit pattern, and priority information without calculating test patterns as selection candidates in advance.
The test patterns selected according to the second embodiment can be used not only for resist model creation but also as test patterns in creating an etching model.
The second embodiment can be applied when, to predict a pattern formed on a resist, test patterns of a template are selected to cover feature quantities of a circuit pattern of the template.
The test-pattern selecting apparatus 20 according to the second embodiment can be realized by executing a computer program in a usual computer including, for example, the control device 1 such as a CPU, the storage device 2 such as a read only memory (ROM) or a RAM, the external storage device 3 such as a HDD or a CD drive device, the display device 4 such as a display, and the input device 5 such as a keyboard and the mouse shown in
A test-pattern selecting program executed by the test-pattern selecting apparatus 20 according to the second embodiment can be recorded in a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a digital versatile disk (DVD) as a file of an installable format or an executable format and provided.
The test-pattern selecting program executed by the test-pattern selecting apparatus 20 according to the second embodiment can be stored on a computer connected to a network such as the Internet and downloaded through the network to thereby be provided. The test-pattern selecting program executed by the test-pattern selecting apparatus 20 according to the second embodiment can be provided or distributed through the network such as the Internet.
The test-pattern selecting program executed by the test-pattern selecting apparatus 20 according to the second embodiment can be incorporated in the ROM or the like in advance and provided.
The test-pattern selecting program executed by the test-pattern selecting apparatus 20 according to the second embodiment has a module configuration including the respective components (the feature-quantity extracting apparatus 21, the priority-information storing unit 22, and the test-pattern selecting unit 23). As actual hardware, the CPU reads out the test-pattern selecting program from the storage medium and executes the test-pattern selecting program. Consequently, the respective units are loaded onto the main storage device. The feature-quantity extracting apparatus 21, the priority-information storing unit 22, and the test-pattern selecting unit 23 are generated on the main storage device.
A third embodiment of the present invention is explained below. When a dimension (a resist dimension) of a resist pattern formed on a wafer is measured based on test patterns selected for resist model creation for a circuit pattern, in general, a critical dimension-scanning electron microscope (CD-SEM) is used. The CD-SEM is an apparatus manufactured exclusively for a length measuring function among functions such as observation, analysis, and length measurement of a general SEM. However, the CD-SEM cannot obtain a measurement value having high accuracy and reproducibility because of the influence of damage to a measurement pattern due to charge-up and electron beams, roughness of the measurement pattern, or the like.
Therefore, in the third embodiment, a resist model is created by using test patterns with which a resist dimension can be measured even if the CD-SEM is not used.
In
The mask layout drawing of the test patterns generated by the test-pattern generating unit 32 is explained below.
P<λ/{NA(1+σ)} Formula 4
where, λ, Na, and σ are the wavelength of an exposure apparatus, the number of lens apertures, and a coherence factor of illumination, respectively.
When the condition of Formula 4 is satisfied, the L/S structure on the mask is not resolved on the wafer and, instead, a bar-like resist pattern is formed as shown in
The size of the test patterns on the mask and values of the line width change amount d, the center line width L0, and the pitch P are set such that the length L in the longitudinal direction of the resist pattern is length (e.g., several microns) that can be measured by an optical measuring apparatus (e.g., a stereo microscope). When the length L is measured by the optical measuring apparatus, since there is no charge-up or damage to a measuring object, high measurement reproducibility can be obtained. With the test patterns shown in
In this way, the shape of the optical image can be freely changed by changing the values of the line width change amount d, the center line width L0, and the pitch P using the mask layout drawing of the test patterns shown in
In
For example, it is assumed that the feature-quantity extracting apparatus 31 defines, as feature quantities, a maximum Imax of intensity of the optical image and a tilt slope of optical image intensity at an edge.
Imax is larger as L0 is larger. Slope is larger as d is larger. At step S32, the test-pattern generating unit 32 mainly adjusts L0 and d to thereby generate test patterns having feature quantities located at white circles shown in
Referring back to
The test pattern of the line and space shown in
As explained above, according to the third embodiment, test patterns of lines and spaces with dimensions of the lines and the spaces adjusted in a range in which the test patterns are not resolved on a wafer are generated. A resist model is created based on a residual between a predicted dimension of the generated test patterns and an actual dimension of a resist pattern formed on the wafer. Therefore, a resist pattern not depending on process fluctuation is transferred on to the wafer. A dimension of the resist pattern can be measured by the optical measuring apparatus instead of the CD-SEM. In other words, an actual dimension having high reproducibility and high accuracy can be obtained. Therefore, it is possible to create a resist model with high accuracy guaranteed.
The resist-model creating apparatus 30 according to the third embodiment can be realized by executing a computer program in a usual computer including, for example, the control device 1 such as a CPU, the storage device 2 such as a read only memory (ROM) or a RAM, the external storage device 3 such as a HDD or a CD drive device, the display device 4 such as a display, and the input device 5 such as a keyboard and the mouse shown in
A resist-model creating program executed by the resist-model creating apparatus 30 according to the third embodiment can be recorded in a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a digital versatile disk (DVD) as a file of an installable format or an executable format and provided.
The resist-model creating program executed by the resist-model creating apparatus 30 according to the third embodiment can be stored on a computer connected to a network such as the Internet and downloaded through the network to thereby be provided. The resist-model creating program executed by the resist-model creating apparatus 30 according to the third embodiment can be provided or distributed through the network such as the Internet.
The resist-model creating program executed by the resist-model creating apparatus 30 according to the third embodiment can be incorporated in the ROM or the like in advance and provided.
The resist-model creating program executed by the resist-model creating apparatus 30 according to the third embodiment has a module configuration including the respective components (the feature-quantity extracting apparatus 31, the test-pattern generating unit 32, and the resist-model creating unit 33). As actual hardware, the CPU reads out the resist-model creating program from the storage medium and executes the resist-model creating program. Consequently, the respective units are loaded onto the main storage device. The feature-quantity extracting apparatus 31, the test-pattern generating unit 32, and the resist-model creating unit 33 are generated on the main storage device.
A fourth embodiment of the present invention is explained below. With the CTM in the past, a resist image is described by a linear model with feature quantities set as explanatory variables. Therefore, to create a highly accurate resist model, it is desirable that a relation between values of various feature quantities and a difference (a residual) between an actual dimension and a predicted dimension has a linear relation in which a determination coefficient is as close as possible to 1.
On the other hand, in the CTM, feature quantities are extracted according to a nonlinear function using feature-quantity extraction parameters.
Therefore, when the calibration parameters are optimized (step S4 in
However, with this method, feature quantities are extracted every time the feature-quantity extraction parameters are changed. Therefore, large calculation cost is necessary and calculation load and resist model creation time are extremely large.
According to the fourth embodiment, a relation between a resist image and various feature quantities is caused to nonlinearly regress, whereby a highly accurate resist model is quickly created without varying the feature-quantity extraction parameters.
As shown in the figure, a resist-model creating apparatus 40 includes a feature-quantity extracting apparatus 41 that calculates optical images from a mask layout drawing of test patterns selected for resist model creation and extracts feature quantities from the calculated optical images and a resist-model creating unit 42 that optimizes calibration parameters for a resist model based on the feature quantities extracted by the feature-quantity extracting apparatus 41 and an actual dimension of the selected test patterns.
The feature-quantity extracting apparatus 41 can be any apparatus as long as the apparatus can extract the first to third feature quantities and can be the same as, for example, the feature-quantity extracting apparatus explained in the first embodiment. The test patterns for resist model creation can be test patterns selected by any method and can be test patterns selected by, for example, the method explained in the second embodiment.
In
Subsequently, the resist-model creating unit 42 causes a nonlinear kernel function to act on feature quantities of the respective test patterns, i.e., the first feature quantity, the second feature quantity, and the third feature quantity and maps the feature quantities of the respective test patterns to a higher-dimensional space (step S42). As the nonlinear kernel function, there are a Gaussian kernel, a sigmoid kernel, a logistic kernel, and the like. The resist-model creating unit 42 selects and uses an appropriate kernel function such that the feature quantities can be caused to linearly regress in the higher-dimensional space at the mapping destination.
The resist-model creating unit 42 causes the respective feature quantities to linearly regress in the higher-dimensional space and creates a resist model such that a residual among the test patterns is minimized (step S43). As a method of causing the feature quantities to linearly regress, methods of highly accurately causing the feature quantities to linearly regress using a support vector machine and a neural network are known. The resist-model creating unit 42 performs linear regression of the feature quantities using these methods.
As explained above, after being mapped to the higher-dimensional space by the nonlinear kernel function, the respective feature quantities are caused to linearly regress in the space. This is like the feature quantities being caused to nonlinearly regress in a space before the mapping. In other words, according to the fourth embodiment, a resist image is described in a nonlinear model with feature quantities set as explanatory variables. Therefore, it is possible to omit the process of optimizing feature-quantity extraction parameters in the past.
Optical images were calculated under lithography conditions for using zone illumination with NA1.0/σ0.95/ε0.75. Seventy-five kinds of feature quantities were respectively calculated by using the following seventy-five kinds of combinations of feature-quantity extraction parameters in total:
σ1=20, 30, 40 nm
(σ2, b0)=(100, 0.1), (150, 0.1), (200, 0.1), (100, 0.15), (150, 0.15)
(σ3, b1)=(100, 0.1), (150, 0.1), (200, 0.1), (100, 0.15), (150, 0.15)
Differences between predicted dimensions and actual dimensions of resist images calculated by (1) the linear model and (2) the nonlinear model (the method according to the fourth embodiment) were compared.
With the linear model in the past, when five parameters are optimized by the simplex method, four hundred seventy times of iteration are required. If more than seventy-five kinds of feature-quantity extraction parameters are used to create a resist model with a smaller residual RMS, a larger number of times of iteration are required according to an increase of parameters. Therefore, larger calculation cost and calculation time are necessary and time necessary for resist model creation increases. On the other hand, according to the fourth embodiment, an accurate resist model can be created by one calculation using one kind of feature-quantity extraction parameters. Therefore, it is possible to substantially reduce calculation time.
As explained above, according to the fourth embodiment, the nonlinear function is caused to act on feature quantities of optical images of test patterns to map the feature quantities to a higher-dimensional space and, based on a residual between a predicted dimension of a resist image of the test patterns and an actual dimension of a resist pattern formed on a wafer, a relation between the resist image of the test patterns and the feature quantities are caused to linearly regress on the higher-dimensional space to create a resist model. Therefore, it is possible to quickly create a highly accurate resist model without varying the feature-quantity extraction parameters.
In the above explanation, feature quantities are extracted from optical images of test patterns by using feature-quantity extraction parameters and a resist model for predicting a resist image is created by using the extracted feature quantities as explanatory variables. However, the fourth embodiment can be applied to any method of extracting feature quantities from a first pattern using feature-quantity extraction functions for which feature-quantity extraction parameters are set and creating a simulation model for predicting a second pattern using the extracted feature quantities as explanatory variables. For example, the technology of the fourth embodiment can be applied to a method of extracting feature quantities from a layout drawing of mask patterns, optical images, or a resist image (a first pattern) using feature-quantity extraction functions for which feature-quantity extraction parameters are set and creating an etching model for predicting a pattern (a second pattern), which is formed on a processed layer by etching, using the extracted feature quantities as explanatory variables. Further, in nano-imprinting for forming a pattern on a processed layer using a template, the technology of the fourth embodiment can be applied to a method of extracting feature quantities from a pattern (a first pattern) of the template using feature-quantity extraction functions for which feature-quantity extraction parameters are set and creating a simulation model for predicting a pattern (a second pattern) formed on the processed layer using the extracted feature quantities as explanatory variables.
The resist-model creating apparatus 40 according to the fourth embodiment can be realized by executing a computer program in a usual computer including, for example, the control device 1 such as a CPU, the storage device 2 such as a read only memory (ROM) or a RAM, the external storage device 3 such as a HDD or a CD drive device, the display device 4 such as a display, and the input device 5 such as a keyboard and the mouse shown in
A resist-model creating program executed by the resist-model creating apparatus 40 according to the fourth embodiment can be recorded in a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a digital versatile disk (DVD) as a file of an installable format or an executable format and provided.
The resist-model creating program executed by the resist-model creating apparatus 40 according to the fourth embodiment can be stored on a computer connected to a network such as the Internet and downloaded through the network to thereby be provided. The resist-model creating program executed by the resist-model creating apparatus 40 according to the fourth embodiment can be provided or distributed through the network such as the Internet.
The resist-model creating program executed by the resist-model creating apparatus 40 according to the fourth embodiment can be incorporated in the ROM or the like in advance and provided.
The resist-model creating program executed by the resist-model creating apparatus 40 according to the fourth embodiment has a module configuration including the respective components (the feature-quantity extracting apparatus 41 and the resist-model creating unit 42). As actual hardware, the CPU reads out the resist-model creating program from the storage medium and executes the resist-model creating program. Consequently, the respective units are loaded onto the main storage device. The feature-quantity extracting apparatus 41 and the resist-model creating unit 42 are generated on the main storage device.
A fifth embodiment of the present invention is explained below. In general, a designer designs a circuit pattern based on design rules. Up to a 130 nm node, the design rules are decided with lithography taken into account. If the designer designs a layout based on the design rules, the circuit pattern can be patterned and produced without a problem with the lithography. However, in a 90 nm node or beyond, simple design rules are insufficient and more complicated design rules are required. However, if design rules are too complicated, it is difficult to even present the design rules.
Therefore, as described in the document “Proc. SPIE Vol. 5130 (2003) p. 628”, in circuit pattern design, lithography verification for design data for performing lithography simulation and verifying whether a problem occurs in production in view of the likelihood of a lithography process is performed.
Concerning a created resist model, effectiveness of predicted values by the resist model is guaranteed when feature quantities of a circuit model is within a range covered by a feature quantity distribution of test patterns used in resist model creation. If the designer designs a circuit pattern deviating from the range of the feature quantity distribution, a resist image corresponding to the circuit pattern cannot be accurately predicted. In the past, the lithography verification is performed irrespectively of whether feature quantities of a circuit pattern are within a range of a feature quantity distribution of test patterns. Therefore, it is likely that the lithography verification is performed based on invalid predicted values.
In the fifth embodiment, a section where effectiveness of predicted values is not guaranteed in a designed circuit pattern is deduced by determining whether the designed circuit pattern deviates from a distribution range of a feature quantity distribution of test patterns.
As shown in
In
It is desirable to determine, for example, as explained below, whether the feature quantities of the circuit pattern deviate from the range covered by the distribution of the feature quantities of the test patterns. Specifically, it is desirable to normalize a feature space, plot the feature quantities of the circuit pattern and the test patterns in the normalized feature space, and determine that points corresponding to dots of the circuit pattern do not deviate when dots of at least one test pattern are present within a predetermined Euclidian distance from dots of the circuit pattern and that the points deviate when no dot of the test patterns is present within the predetermined Euclidian distance. The predetermined Euclidian distance is desirably set to, for example, 0.1.
It is also possible to give scores corresponding to Euclidian distances to dots of the respective test patterns to dots corresponding to respective points of the circuit pattern in the normalized feature space and determine that points of the circuit pattern with the scores equal to or smaller than a fixed value deviate and points of the circuit pattern with the scores exceeding the fixed value deviate. It is desirable to calculate score values by, for example, integrating, in all the test patterns, values calculated by causing a Gaussian function or the like to act on distances to the dots of the test patterns.
It is also possible to divide respective coordinate axes in a feature space with grids at a fixed interval and, paying attention to small regions of a minimum unit divided by the grids, determine that a circuit pattern does not deviate when feature quantities of test patterns are plotted in a small region same as a small region in which feature quantities of points of the circuit pattern are plotted and that the circuit pattern deviates when the feature quantities of the test patterns are not plotted in the small region.
Following step S52, the deviating-point display unit 53 displays the extracted point of the circuit pattern on a display device such as a liquid crystal display (step S53). Effectiveness of predicted values by a resist model is not guaranteed in the point displayed on the display device. Therefore, the designer desirably changes a shape of the displayed point to a shape with which effectiveness of predicted values is guaranteed.
When the designer learns that the point deviates from the distribution of the feature quantities of the test patterns, the designer corrects the mask layout drawing of the circuit pattern, for example, as shown in
As explained above, according to the fifth embodiment, a distribution of feature quantities of a circuit pattern created by the designer and a distribution of feature quantities of test patterns are compared, a point of the circuit pattern deviating from a range of the feature quantity distribution of the test patterns is calculated, and the calculated point is displayed. Therefore, the designer can learn a section where prediction accuracy for predicted values by a resist model is not guaranteed. Consequently, the designer can correct a mask layout drawing of the circuit pattern to a shape with which the prediction accuracy can be guaranteed.
In the above explanation, verification of a circuit pattern is performed by using a resist model for predicting a resist image using feature quantities extracted from optical images of test patterns as explanatory variables. However, the fifth embodiment can be applied in any case as long as verification of a design drawing of a first pattern or a design drawing of another pattern for creating the first pattern is performed by using a simulation model for predicting a second pattern using feature quantities extracted from the first pattern as explanatory variables. For example, the fifth embodiment can be applied when verification of a design drawing of a mask pattern is performed by using an etching model for predicting a pattern (a second pattern) formed on a processed layer by etching using feature quantities extracted from a layout drawing of the mask pattern, optical images, or a resist image (a first pattern) as explanatory variables. Further, in nano-imprinting for forming a pattern on a processed layer using a template, the fifth embodiment can be applied when verification of a design drawing of a pattern of a template is performed by using a simulation model for predicting a pattern (a second pattern) formed in a processed layer using feature quantities extracted from a pattern (a first pattern) of the template as explanatory variables.
The designed-circuit-pattern verifying apparatus 50 according to the fifth embodiment can be realized by executing a computer program in a usual computer including, for example, the control device 1 such as a CPU, the storage device 2 such as a read only memory (ROM) or a RAM, the external storage device 3 such as a HDD or a CD drive device, the display device 4 such as a display, and the input device 5 such as a keyboard and the mouse shown in
A designed-circuit-pattern verifying program executed by the designed-circuit-pattern verifying apparatus 50 according to the fifth embodiment can be recorded in a computer-readable recording medium such as a CD-ROM, a flexible disk (FD), a CD-R, or a digital versatile disk (DVD) as a file of an installable format or an executable format and provided.
The designed-circuit-pattern verifying program executed by the designed-circuit-pattern verifying apparatus 50 according to the fifth embodiment can be stored on a computer connected to a network such as the Internet and downloaded through the network to thereby be provided. The designed-circuit-pattern verifying program executed by the designed-circuit-pattern verifying apparatus 50 according to the fifth embodiment can be provided or distributed through the network such as the Internet.
The designed-circuit-pattern verifying program executed by the designed-circuit-pattern verifying apparatus 50 according to the fifth embodiment can be incorporated in the ROM or the like in advance and provided.
The designed-circuit-pattern verifying program executed by the designed-circuit-pattern verifying apparatus 50 according to the fifth embodiment has a module configuration including the respective components (the feature-quantity extracting apparatus 51, the deviating-point extracting unit 52, and the deviating-point display unit 53). As actual hardware, the CPU reads out the designed-circuit-pattern verifying program from the storage medium and executes the designed-circuit-pattern verifying program. Consequently, the respective units are loaded onto the main storage device. The feature-quantity extracting apparatus 51, the deviating-point extracting unit 52, and the deviating-point display unit 53 are generated on the main storage device.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-335484 | Dec 2008 | JP | national |
