Patent Application
20060073613
The present invention relates generally to semiconductor devices and more particularly ferroelectric memory cells and methods for fabricating ferroelectric memory cells and ferroelectric capacitors.
Memory systems are used for storage of data, program code, and/or other information in many electronic products, such as personal computer systems, embedded processor-based systems, video image processing circuits, portable phones, and the like. Memory may be provided in the form of a dedicated memory integrated circuit (IC) or may be embedded (included) within a processor or other IC as on-chip memory. Ferroelectric memory, sometimes referred to as “FRAM” or “FERAM”, is a non-volatile form of memory commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) cell configurations, in which each memory cell includes one or more access transistors and cell capacitors formed using ferroelectric dielectric material. The non-volatility of an FERAM memory cell is the result of the bi-stable characteristic of the ferroelectric dielectric material in the cell capacitor(s), wherein the ferroelectric material has multiple electrically distinguishable stable states.
Ferroelectric memory is often fabricated in stand-alone memory integrated circuits (ICs) and/or in logic circuits having on-board non-volatile memory (e.g., microprocessors, DSPs, communications chips, etc.). The ferroelectric memory cells are typically organized in an array architecture, such as folded-bitline, open-bitline, etc., wherein the individual cells are selected by plateline and wordline signals from address decoder circuitry, with the data being read from or written to the cells along bitlines using latch or sense amp circuits. In a typical 1T1C memory cell, a ferroelectric capacitor is coupled between a plateline signal and a source/drain of a MOS cell transistor, the other source/drain is connected to a bitline, and the transistor gate is connected to a wordline control signal to selectively couple the capacitor with the bitline during read and write operations.
The ferroelectric memory arrays are typically constructed in a device wafer along with CMOS logic circuits, wherein the cell transistors are formed concurrently with logic transistors in the device, and the ferroelectric capacitors are constructed in a capacitor layer above the wafer substrate. For example, the construction of the ferroelectric cell capacitors may be integrated into a CMOS fabrication process flow after transistor formation (e.g., after ‘front-end’ processing), and before the metalization or interconnection processing (e.g., before ‘back-end’ processing). In a typical integration of ferroelectric capacitors in a CMOS process flow, transistors are formed on/in a semiconductor body, and a pre-metal dielectric (PMD) layer is constructed over the transistors, including tungsten contacts extending through the PMD level dielectric to the gate and source/drain terminals of the transistors. Ferroelectric capacitors are then constructed in a first inter-level dielectric layer (e.g., ILD0) above the PMD level, where one of the cell capacitor electrodes is connected to a cell transistor terminal (e.g., typically a source/drain) through one of the tungsten PMD contacts, wherein interconnection of the other capacitor electrode and the remaining transistor terminals with other components (e.g., signal routing) is provided in one or more metalization layers or levels above the ILD0 level.
In the construction of the ferroelectric cell capacitors in the initial ILD0 layer or level, it is important to provide low resistance electrodes and low resistance connection between the electrodes and the contacts in the PMD layer, so as to minimize switching times in the resulting memory cells. With respect to the capacitor electrodes, it has been found that conductive metal oxides are preferred for interfacing with the ferroelectric material itself (e.g., in the upper part of the lower electrode, for example), so as to improve switching endurance fatigue properties by curing oxygen vacancies in the ferroelectric material. At the same time, it is desirable to control the crystallinity and orientation of the ferroelectric material that is constructed over the lower electrode, where higher temperature deposition of the ferroelectric material provides better as-deposited material properties. However, conventional ferroelectric cell fabrication techniques do not provide optimum performance due to limitations of the metal oxides used in the capacitor electrode formation, whereby there is a need for improved methods for ferroelectric capacitor and ferroelectric memory cell fabrication by which improved performance and reliability can be achieved.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary presents one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later and is not an extensive overview of the invention. In this regard, the summary is not intended to identify key or critical elements of the invention, nor does the summary delineate the scope of the invention.
The invention relates to semiconductor fabrication techniques in which ferroelectric memory cells and the ferroelectric cell capacitors thereof are created using low temperature metal organic chemical vapor deposition (MOCVD) techniques to deposit the PZT dielectric material of the cell capacitors without significant adverse effect on the metal oxide material of the lower capacitor electrode. The inventors have appreciated that while high PZT deposition temperatures provide better crystallinity in the as-deposited PZT, that such deposition techniques can cause reduction in the oxygen content of metal oxides in the lower capacitor electrode over which the PZT is being deposited, leading to capacitor fatigue and degraded switching endurance. In particular, the inventors have found that Iridium oxide (IrOx) is thermodynamically unstable at high pressures and low pressures used in conventional PZT deposition processes, particularly in the slightest of reducing ambients, and that the kinetics of the IrOx reduction in such conditions is quite fast. The present invention provides for depositing the PZT at lower temperatures in conditions where the metal oxide is thermodynamically stable, thereby mitigating reduction of the oxide electrode material. In addition to mitigating reduction of the lower electrode oxide material, the low temperature ferroelectric material formation aspects of the invention also facilitate integration of the ferroelectric capacitors in process flows that employ nickel silicide in the transistor level, whereby the benefits of such processes can be realized in devices having PZT based ferroelectric memory cells.
In accordance with one or more aspects of the invention, a method is provided for fabricating a ferroelectric capacitor in a semiconductor device wafer. The method comprises forming a lower electrode, depositing lead zirconate titanate (PZT) ferroelectric material on the lower electrode at a temperature below 450 degrees C. and thereafter forming an upper electrode on the PZT. The PZT deposition temperature may be between 300 and 450 degrees C. in certain implementations, preferably between 400 and 450 degrees C. The lower electrode may include Iridium Oxide (IrOx) of any suitable stoichiometry, wherein the lower PZT deposition temperature helps to mitigate reduction in the oxygen content of the IrOx, by which the IrOx helps to maintain the switching endurance of the resulting ferroelectric capacitor. In one implementation, the IrOx and the PZT are deposited ex-situ in different processing chambers, where the wafer may be pre-heated in the PZT deposition chamber in O2, O3, N2O, or other suitable non-reducing ambient so as to stabilize the deposited IrOx prior to beginning the PZT deposition. The method may further comprise formation of transistors with silicide structures that comprise nickel silicide or nickel silicide alloys at gate and/or source/drain terminals prior to constructing the capacitors, wherein the low PZT deposition temperatures of the invention mitigate pipe defects and other adverse thermal effects on the silicide structures. In further exemplary implementations, the method may comprise thermal crystallization annealing operations after all or a portion of the upper electrode is formed to facilitate crystallization of the previously deposited PZT material, for example, by rapid thermal annealing (RTA).
In accordance with another aspect of the invention, a method is provided for fabricating a ferroelectric memory cell in a semiconductor device wafer, comprising forming a transistor in the wafer and forming a silicide structure on a gate or source/drain of the transistor, where the silicide structure comprises nickel silicide or an alloy of nickel silicide. A dielectric is then formed over the transistor, and a conductive contact is provided that extends through the dielectric to the silicide structure. The method further comprises forming a lower electrode on at least a portion of the conductive contact, forming PZT ferroelectric material above and in contact with the lower electrode at a temperature below 450 degrees C., forming an upper electrode above and in contact with the PZT, and patterning the upper electrode, the PZT, and the lower electrode to form a patterned ferroelectric capacitor.
Yet another aspect of the invention provides a method of fabricating a ferroelectric memory cell in a semiconductor device wafer. The method comprises forming a transistor in the wafer, forming a silicide structure on the gate or one of the source/drains of the transistor that comprises nickel silicide or an alloy thereof, forming a dielectric over the transistor with a conductive contact extending through the dielectric to the silicide structure, forming a lower electrode on at least a portion of the conductive contact, forming PZT ferroelectric material above and in contact with the lower electrode, forming an upper electrode above and in contact with the PZT, and patterning the upper electrode, the PZT, and the lower electrode to form a patterned vertical ferroelectric capacitor.
Still another aspect of the invention provides a ferroelectric memory cell in a semiconductor device wafer, comprising a transistor formed in the wafer, a silicide structure in contact with a gate or source/drain of the transistor that comprises nickel suicide or an alloy of nickel silicide, a dielectric formed over the transistor, a conductive contact extending through the dielectric to the silicide structure, a lower electrode above and in contact with at least a portion of the conductive contact, a PZT ferroelectric material above and in contact with the lower electrode, and an upper electrode above and in contact with the PZT, where the upper electrode, the PZT, and the lower electrode are patterned to form a patterned vertical ferroelectric capacitor where neither the PZT nor the lower electrode extend above or laterally of any portion of the upper electrode.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.
The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout. The invention relates to the use of low deposition temperatures to form PZT ferroelectric material, by which the advantages of stable lower electrode IrOx material and nickel silicide structures can be achieved in the fabrication of semiconductor devices. The invention may be carried out in any type of semiconductor device, for example, devices having memory cells with ferroelectric cell capacitors or other devices in which ferroelectric capacitors are used. The various aspects and advantages of the invention are hereinafter illustrated and described in conjunction with the drawings, wherein the illustrated structures are not necessarily drawn to scale.
A pre-metal dielectric (PMD) 14 is provided above the substrate 4 to cover the cell transistor T, where any suitable dielectric material and thickness may be used for the layer 14. A conductive storage node contact 16a and a conductive bitline contact 16b are formed through the PMD layer 14 using any suitable materials and dimensions (e.g., tungsten (W), polysilicon, or other conductive material) to connect with the silicide structures 7 of the cell transistor source/drains 6, wherein the conductive polysilicon electrode of the gate 10 forms a wordline connection in the illustrated device 2. The vertical ferroelectric capacitor C is formed above the cell storage node source/drain contact 16a, including a first or lower electrode 18, 30, with an overlying ferroelectric material (PZT) 20, and a second or upper electrode 22 above the PZT 20. A multilayer sidewall diffusion barrier 46 is formed over the patterned ferroelectric capacitor C, including an aluminum oxide AlOX material and a silicon nitride material SiN. A first inter-level or inter-layer dielectric layer (ILD0) 24 is formed over the barrier 46, and conductive contacts 26 are formed through the dielectric 24 (and through the barrier 46) to couple with the upper capacitor electrode 22 (plateline) and with the bitline contact 16 in the PMD level 14.
As further illustrated in
The lower electrode may include a conductive diffusion barrier 30 formed on the storage node contact 16a, for example, depending on whether the PMD contact 16a requires protection during subsequent processing of the capacitor dielectric 20. In such a case, the conductive barrier 30 can be any suitable conductive material that prevents degradation of the contact 16a, such as TiAlN or other possible barriers (some of which have a slow oxidation rate compared to TiN) which include: TaSiN, TiSiN, TiN, TaN, HfN, ZrN, HfAlN, CrN, TaAlN, CrAlN, or any other conductive material, or stacks or combinations thereof, where the barrier 30 is preferably thin, such as having a thickness of about 100 nm or less in one example. The exemplary lower electrode 30, 18 comprises a conductive bilayer diffusion barrier 30a, 30b (collectively 30) formed over the contact 16a for protection thereof during subsequent processing, wherein the exemplary first barrier layer 30a is TiN of any suitable thickness (e.g., about 40 nm in one example), and the second barrier layer 30b is TiAlN of any suitable thickness, such as about 30 nm in the illustrated implementation. Alternatively, the second barrier layer 30b could be TiAlON, or a single barrier layer could be formed over all or a portion of the contact 16a, such as TiAlN having a thickness of about 60 nm in one example.
The other lower electrode layers 18 can be formed either on the barrier 30 or directly on the contact 16a and the PMD dielectric 14 so as to make electrical connection with the underlying contact 16a. Preferably, the lower electrode 18 has a thickness of about 25-100 nm, is stable in oxygen, and is comprised of a noble metal or conductive oxide such as Ir, IrOx, Pt, Pd, PdOx, Au, Ru, RuOx, Rh, RhOx, LaSrCoO3, (Ba,Sr)RuO3, LaNiO3 or stacks or combinations thereof. The preferred bottom electrode for a PZT capacitor dielectric is either 50 nm Ir or a stack comprised of 30 nm IrOx and 20 nm Ir. In the exemplary device 2, a lower Iridium (Ir) layer 18a is formed on the barrier 30 to any suitable thickness, such as about 20 nm in the illustrated example. A lower Iridium Oxide (IrOx) layer 18b is then formed over the lower Ir layer 18a to any suitable thickness, such as about 30 nm in the illustrated implementation. The IrOx layer 18b operates to improve switching endurance fatigue properties by curing oxygen vacancies in the overlying PZT material 20, wherein it is desirable to avoid or mitigate reduction of (e.g., loss of oxygen content from) the IrOx layer 18b during formation of the PZT 20.
The exemplary ferroelectric material 20 is PZT having any suitable thickness, such as about 300 to 1000 Å, preferably about 700 Å in one example, where the PZT is initially deposited at low temperature in accordance with the invention, so as to avoid or inhibit reduction of the IrOx material 18b, wherein the low PZT deposition temperature also helps to avoid pipe defects and other problems associated with the use of nickel silicide structures 7. The PZT 20 may be deposited using metal organic chemical vapor deposition (MOCVD) techniques at temperatures below 450 degrees C. so as to avoid reduction of the IrOx layer 18b, and also to mitigate thermal degradation of the nickel silicide structures 7, wherein pulsed or interrupted MOCVD deposition techniques and post-deposition rapid thermal annealing (RTA) may be employed to provide desired material properties of the PZT capacitor dielectric 20, as described in greater detail below.
The upper electrode 22 includes an upper IrOx layer 22a formed over the PZT 20 to any suitable thickness, such as about 100 nm or less, as well as an upper Ir layer 22b formed over the upper IrOx layer 22a to any suitable thickness, such as about 100 nm or less. A hardmask 32 is formed above the upper Ir layer 22b, for use in patterning the vertical capacitor stack C, where the hardmask 32 can be any suitable material such as TiN, TiAlN, etc. In combination with the PZT ferroelectric material 20, other materials may be substituted for the upper IrOx layer 22a, wherein it is advantageous to have a conductive oxide top electrode such as IrOx, RuOx, RhOx, PdOx, PtOx, AgOx, (Ba,Sr)RuO3, LaSrCoO3, LaNiO3, YBa2Cu3O7-x rather than a single pure noble metal so as to minimize degradation due to many opposite state write/read operations (fatigue). Moreover, it is advantageous to have the upper Ir layer 22b or other suitable noble metal layer above the upper oxide layer 22a to provide low resistance for connection of the upper electrode structure to the plateline contact 26 and the hardmask 32.
A conductive hardmask 32 is formed over the upper electrode 22, and is then patterned and used in selectively etching the upper and lower electrodes and the PZT 20 to define a patterned vertical ferroelectric capacitor structure C as shown in
Referring now to
In addition, while the exemplary semiconductor devices are illustrated herein with ferroelectric capacitors C formed in a dielectric layer or level (ILD0 24 in
Beginning at 102 in
At 110, an initial dielectric material is formed over the transistors, referred to herein as a pre-metal dielectric (PMD layer 14 in
At 114-132, ferroelectric capacitor layers are formed over the PMD layer 14 and the contacts 16 thereof (
In the illustrated implementation, a conductive diffusion barrier is first created at 114 and 116 comprising a TiN layer 30a formed at 114 over the PMD dielectric 14 and the PMD tungsten contacts 16 (
Referring also to
At 118, a lower electrode metal layer 18a is formed over the barrier 30 via a deposition process 162, as shown in
Referring also to
Furthermore, the deposited IrOx layer 18b is optionally pre-heated in the MOCVD chamber at 124 before beginning PZT deposition, in order to stabilize the IrOx 18b. Preferably, a pre-heating operation 170 is performed (
Referring also to
The capacitor dielectric 20 can be deposited in a generally amorphous phase at low temperatures below 450 degrees C., preferably above about 300 degrees C., more preferably between about 400 and 450 degrees C., wherein the PZT 20 may subsequently be crystallized using a post-deposition anneal, such as the optional anneal described below at 130. During deposition, moreover, the chamber pressure is preferably controlled to about 1 Torr or more, preferably about 1-10 Torr at temperatures between 400 and 450 degrees C., or at a pressure of about 10 Torr or more for deposition temperatures between 300 and 400 degrees C. Where the optional pre-heating was performed at 124 in the PZT deposition chamber, the PZT deposition can be started at 126 simply by starting the flow of the PZT precursors (liquids) into the chamber in the oxidizing (e.g., non-reducing) ambient.
The inventors have appreciated that the low temperature deposition of the PZT material 20 at 126 advantageously prevents or inhibits reduction of the oxygen content of the underlying IrOx material 18b, and further facilitates the use of nickel silicide or alloys of nickel silicide for the silicide structures 7. Furthermore, the crystallinity of the deposited PZT 20 can be controlled by the specific MOCVD deposition techniques at 126 and/or may be modified post-deposition, as described below, whereby the invention allows the advantages of low deposition temperature as well as control over the PZT crystallinity and other properties. In this regard, prior techniques involved much higher PZT deposition temperatures (e.g., 650 degrees C. or more in some cases) to control the as-deposited PZT properties, wherein the high PZT deposition temperature has been found to be undesirable for integration with nickel suicides 7 and also causes a reduction in the IrOx, resulting in degraded switching endurance fatigue properties of the resulting ferroelectric cell capacitor.
In another aspect of the invention, the PZT deposition process 172 can employ pulsed or interrupted MOCVD deposition, wherein the precursor flow is periodically interrupted (e.g., discontinued and then restarted, while the gas flow is continued) in order to give the deposited atoms a chance to move around during the low temperature deposition at 126. In the MOCVD deposition at 126, the ambient gases are kept flowing (e.g., as in the above-described optional pre-heat at 124), and the PZT deposition starts when liquid precursors, such as hydrocarbon-based hydroxyl compounds of lead, zirconium, and titanium (PZT) are introduced into the chamber pre-mixed in liquid form though a shower head type structure into an oxidizing gas, and the substrate is maintained at less than 450 C. The precursors break down in the oxidizing environment, leading to deposition of the resulting PZT film 20 over the IrOx 18b. In one example of such pulsed deposition at 126, the precursors are allowed to flow for about 30 seconds, and are then discontinued for about 60 seconds, and the process is repeated as needed to provide the desired thickness (e.g., 300 to 1000 Å, preferably about 700 Å in the illustrated example).
The inventors have appreciated that the low deposition temperature (e.g., below 450 degrees C.) can thus be used to mitigate reduction of the IrOx material 18b, wherein optional pulsed PZT deposition in a separate chamber at 126, the optional pre-heating at 124, and/or the post deposition crystallization annealing at 130 can be employed separately or in combination to help achieve the desired PZT crystallinity and orientation together with the desired lower IrOx properties. Further, the low PZT deposition temperature and the optional pulsed form of MOCVD deposition at 126 can help to control the PZT deposition rate and improve the crystallinity without needing the high temperatures that can cause problems with the nickel silicide structures 7, wherein the optional post-deposition annealing at 130 may not be needed.
Referring now to
Moreover, where the first upper electrode material 22a is an oxide, it is advantageous to have a noble metal layer 22b above it to help maintain low contact resistance between the subsequently formed metal plateline contact 26 and the oxide 22a. Thus, in the exemplary method 100, an upper Ir layer 22b or other suitable metal is deposited at 132. However, an optional crystallization anneal process may be performed at 130 (e.g., thermal process 180 in
Referring also to
Referring also to
Following formation of the barrier at 136, an inter-level dielectric (e.g., ILD0) is deposited at 138 (layer 24 in
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
